JP2006190991A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a group III-V nitride-based field effect transistor which has a T shaped gate electrode eliminating the need of electron beam exposure. <P>SOLUTION: The field effect transistor comprises a first semiconductor layer 14 made of a plurality of laminated semiconductor films and a second semiconductor layer 15 formed on the first semiconductor layer 14. Source and drain electrodes 17 and 18 mutually spaced from each other are formed on the second semiconductor layer 15. An opening with a side wall having an insulating film 16 formed thereon for exposing the first semiconductor layer 14 is formed in a region sandwiched by the source and drain electrodes 17 and 18 of the second semiconductor layer 15. A gate electrode 19 contacted with the insulating film 16 and also contacted with the first semiconductor layer 14 at the bottom of the opening is formed in the opening. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof, and more particularly to a high-power transistor and a high-frequency transistor using a nitride semiconductor and a manufacturing method thereof.

  A group III-V nitride compound semiconductor represented by gallium nitride (GaN) or the like, a so-called nitride semiconductor is a wide gap semiconductor, for example, a forbidden band at room temperature is 3.4 eV in gallium nitride (GaN), In aluminum nitride (AlN), it is 6.2 eV. Nitride semiconductors have the characteristics that the breakdown electric field is large and the saturation drift velocity of electrons is higher than that of compound semiconductors such as gallium arsenide (GaAs) or silicon (Si) semiconductors. For this reason, it has been attracting attention as a high-frequency and high-power transistor, and research and development are actively conducted.

In the heterojunction structure of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), charges are generated at the heterojunction interface due to spontaneous polarization and piezo polarization on the (0001) plane. A sheet carrier concentration of 1 × 10 ¹³ cm ⁻² or more can be obtained even when undoped due to charges generated at the heterojunction interface. By utilizing the two-dimensional electron gas at the heterojunction interface, a heterojunction field effect transistor having a large current density can be realized. Therefore, a field effect transistor using a nitride semiconductor is advantageous for high output.

  In general, shortening the gate length is the most effective means for improving the high frequency characteristics of the field effect transistor. For example, in order to improve the maximum oscillation frequency (fmax), it is necessary to increase the mutual conductance (gm) corresponding to the gain, reduce the capacitance around the gate electrode, and reduce the resistance of the gate electrode. is there.

  In conventional compound semiconductors based on gallium arsenide (GaAs) and indium phosphide (InP), a T-shaped or mushroom-type gate electrode structure and a gate electrode formation process have been proposed and put into practical use as a method for shortening the gate length. ing. Also for GaN-based semiconductors, T-shaped gates and the like have been studied, and improvements in high-frequency characteristics such as fmax have been reported.

  A GaN-based semiconductor tends to have a large parasitic resistance typified by ohmic contact resistance of a source electrode and a drain electrode. For this reason, in order to realize a field effect transistor with excellent high-frequency characteristics by effectively using a large saturation drift velocity, the maximum electric field below the gate electrode can be increased more than when a GaAs compound semiconductor is used. It needs to be bigger. Therefore, unless a device having a shorter gate length than that of a conventional compound semiconductor is realized, it is difficult to realize a device having a high frequency characteristic equivalent to or higher than that of a GaAs-based or InP-based device.

  FIG. 8 shows a cross-sectional structure of a short gate length field effect transistor using a nitride semiconductor such as GaN according to a conventional example. As shown in FIG. 8, an undoped GaN layer 803 and an n-type AlGaN layer 804 are sequentially formed on a sapphire substrate 801 with a low-temperature GaN buffer layer 802 interposed therebetween. On the n-type AlGaN layer 804, a source electrode 805 and a drain electrode 806 in which titanium (Ti) and aluminum (Al) are stacked are formed at an interval. A T-shaped gate electrode 807 in which nickel (Ni), platinum (Pt), and gold (Au) are stacked is formed between the source electrode 805 and the drain electrode 806.

  The gate length, which is the width of the portion where the T-shaped gate electrode 807 and the n-type AlGaN layer 804 are in contact, is about 150 nm. The T-shaped gate electrode 807 can be formed by, for example, forming a three-layer resist structure, electron beam evaporation, and lift-off. For example, a resist such as polymethylmethacrylate (PMMA) is used for the lower layer and the uppermost layer of a three-layer resist structure capable of electron beam exposure, and a polydimethylglutarimide (PMGI) resist is used for the second layer. After the uppermost PMMA resist is exposed to a width of about 1 μm, an opening is formed in the second layer PMGI resist using a developer. At this time, a bowl-shaped portion is formed in the uppermost PMMA resist. Subsequently, the lowermost PMMA resist exposed at the bottom of the opening is subjected to electron beam exposure with a width of 150 nm.

A GaN-based field effect transistor having a T-shaped gate electrode has high mutual conductance, reduced gate peripheral capacitance, low gate resistance, and can realize excellent high frequency characteristics (for example, non-patent literature) 1).
YFWu et al., "International Electron Devices Technical Meeting", 2003, p579.

  However, a conventional field effect transistor using a nitride semiconductor having a T-shaped gate electrode requires electron beam exposure in the process of forming the T-shaped gate electrode. In addition, three layers of photoresist are required, and there is a problem that the gate electrode formation process becomes expensive. In addition, the T-shaped gate electrode formation process has poor reproducibility, and the gate electrode tends to collapse, resulting in poor yield.

  The present invention solves the above-mentioned conventional problems, and makes it possible to realize a field effect transistor using a nitride semiconductor having a T-shaped gate electrode that does not require electron beam exposure in the manufacturing process, and a manufacturing method thereof. Objective.

  In order to achieve the above object, the present invention has a field effect transistor in which a T-shaped gate electrode sandwiched between semiconductor layers having an oxide film formed on the surface thereof is formed.

  Specifically, the first field effect transistor according to the present invention includes a first semiconductor layer formed by laminating a plurality of semiconductor films, and a second semiconductor layer formed in contact with the main surface of the first semiconductor layer. And a source electrode and a drain electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer and spaced apart from each other, and a source electrode and a drain electrode in the second semiconductor layer An opening formed in the region and exposing the first semiconductor layer; an insulating film formed on a sidewall of the opening; and a gate electrode in contact with the insulating film and in contact with an exposed portion from the opening in the first semiconductor layer It is characterized by having.

  According to the first field effect transistor, since the gate electrode is provided in contact with the insulating film formed on the sidewall of the opening and in contact with the first semiconductor layer at the bottom of the opening, the gate electrode is provided in the opening. It can be formed by embedding an electrode material. Therefore, a T-shaped gate electrode having a short gate length can be easily formed without requiring electron beam exposure. In addition, an insulating film is formed on the side wall of the opening, and the gate length can be made shorter than the width of the mask for forming the opening. In addition, the gate leakage current can be reduced.

  In the first field effect transistor, the first semiconductor layer preferably has a two-dimensional electron gas layer generated in a region below the gate electrode. With such a configuration, the carrier mobility in the channel of the transistor is increased, and a high-performance field effect transistor having a smaller series resistance and a larger mutual conductance can be realized.

  In the first field effect transistor, the insulating film is preferably an oxide film obtained by oxidizing the second semiconductor layer. With such a structure, the insulating film can be formed with high reproducibility and the thickness of the insulating film can be controlled with high accuracy. Therefore, the yield of field effect transistors can be improved.

  In the first field effect transistor, the insulating film is preferably formed so as to cover a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode and a portion excluding the bottom surface of the opening. With such a structure, the surface of the semiconductor layer between the source electrode and the drain electrode is entirely covered with an insulating film, and it is possible to form a field effect transistor with less leakage current and high reliability. Become.

  In the first field-effect transistor, it is preferable that the insulating film is thicker at the portion formed on the side wall of the opening than at the other portions. With such a configuration, the leakage current can be further reduced and the parasitic capacitance around the gate electrode can be reduced, so that a field effect transistor having more excellent high frequency characteristics can be realized.

  In the first field-effect transistor, it is preferable that at least one of the carrier concentration and the composition is different between the portion of the first semiconductor layer in contact with the gate electrode and the second semiconductor layer.

  A second field effect transistor according to the present invention includes a first semiconductor layer formed by laminating a plurality of semiconductor films, a second semiconductor layer formed in contact with the main surface of the first semiconductor layer, A source electrode and a drain electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer and spaced apart from each other; and a region between the source electrode and the drain electrode in the second semiconductor layer. And an opening that exposes the first semiconductor layer, and a gate electrode that is in contact with the exposed portion from the opening in the first semiconductor layer, the first semiconductor layer being sandwiched between the source electrode and the drain electrode It is preferable that the region has a protruding portion protruding in a convex shape in cross section.

  According to the second field effect transistor, since the first semiconductor layer has a protruding portion protruding in a cross-sectional shape in a region sandwiched between the source electrode and the drain electrode, the series resistance can be reduced. Therefore, the high frequency characteristics are improved. In addition, since the on-resistance can be reduced, the switching loss can also be reduced.

  The second field effect transistor preferably further includes an insulating film formed on the sidewall of the opening. With such a structure, the gate length can be made shorter than the width of the mask for forming the opening. In addition, the gate leakage current can be reduced.

  In the second field effect transistor, the protrusion preferably includes a two-dimensional electron gas layer generated so as to cross the side wall of the protrusion. By adopting such a configuration, the current flowing between the source and drain flows without passing through the potential barrier of the heterojunction that forms the two-dimensional electron gas, thereby realizing a high-performance field effect transistor with lower series resistance. It becomes possible.

  In the first and second field effect transistors, the first semiconductor layer and the second semiconductor layer are preferably made of a group III-V nitride semiconductor. With such a configuration, it is possible to realize a field effect transistor with a high breakdown voltage, a higher saturation drift speed, and a higher mutual conductance when the gate length is sufficiently shortened. A transistor can be realized.

In the first and second field effect transistors, the first semiconductor layer includes a gallium nitride film, and a general formula formed on the gallium nitride film is Al _x Ga _1-x N (where 0 <x ≦ 1 It is preferable to include the film | membrane represented by these.

In the first and second field effect transistors, the second semiconductor layer includes gallium nitride or a general formula of In _y Al _z Ga _(1-yz) N (where 0 <y <1, 0 <z <1, y + z <1) is preferable. By adopting such a configuration, it is possible to realize a high-performance field effect transistor with a smaller series resistance and no hetero-barrier at the interface between the second semiconductor layer and the first semiconductor layer. Become.

  In the first and second field effect transistors, the first semiconductor layer includes a gallium nitride film that is formed on the main surface of the substrate and whose main surface is a (11-20) plane having a plane orientation. It is preferable that the main surface is made of sapphire having a (1-102) plane of plane orientation. With such a structure, a transistor can be formed on a nonpolar surface, and a transistor which is not affected by a polarization electric field can be realized. Therefore, control of the threshold voltage is facilitated, and normally-off characteristics essential for the power switching element can be easily realized.

  In the first and second field effect transistors, the first semiconductor layer is formed on the main surface of the substrate whose main surface is the (0001) plane of the plane orientation, and the gate electrode is a crystal zone axis of the substrate. It is preferable to form linearly along the <11-20> direction. With this configuration, the step can be formed linearly when the second semiconductor layer is formed by regrowth, and the gate length can be made uniform when the gate electrode is formed so as to cover the step. Since it can be formed, a high-performance field-effect transistor with higher reproducibility can be realized.

  The field effect transistor manufacturing method according to the present invention includes a step (a) of forming a first semiconductor layer in which a plurality of semiconductor films are stacked on a substrate, and a mask is selectively formed on the first semiconductor layer. Forming a second semiconductor layer on the first semiconductor layer using a mask; and removing the mask to form an opening in the second semiconductor layer. A step (d) of forming, a step (e) of forming a gate electrode in a region including the opening of the second semiconductor layer so as to be in contact with the first semiconductor layer exposed from the opening, and a second semiconductor And (f) forming a source electrode and a drain electrode in regions on both sides of the gate electrode on the layer.

  According to the method for manufacturing a field effect transistor of the present invention, the step of forming the second semiconductor layer on the first semiconductor layer using the mask, and the opening in the second semiconductor layer by removing the mask. Since the recess structure of the gate electrode can be formed by regrowth, the threshold voltage and the drain current are determined by the thickness of the first semiconductor layer. Therefore, since the thickness of the first semiconductor layer can be precisely controlled by epitaxial growth, a field effect transistor with good reproducibility and low series resistance can be realized.

  The method for producing a field effect transistor of the present invention includes a step (h) of oxidizing the surface of the second semiconductor layer to form an insulating film after the step (c) and before the step (e). Furthermore, it is preferable to provide. With such a configuration, the gate electrode is in contact with the second semiconductor layer with an insulating film interposed therebetween, so that the gate leakage current can be further reduced and compared with the case where the gate electrode is in direct contact with the second semiconductor layer. Parasitic capacitance can be reduced.

  The method for producing a field effect transistor of the present invention preferably further includes a step (g) of reducing the width of the mask in the gate length direction by etching between the step (b) and the step (c). With such a configuration, the line width of the first semiconductor layer exposed after oxidation can be further reduced, and a high-performance field effect transistor with a short gate length can be reliably realized.

  In the manufacturing method of the field effect transistor of the present invention, the width of the mask in the gate length direction is formed smaller than the thickness in the step (b), and isotropic etching is performed in the width direction and the thickness direction in the step (g). Preferably it is done. With such a configuration, the line width of the mask layer can be easily reduced.

  In the method of manufacturing a field effect transistor according to the present invention, in the step (a), the first semiconductor layer is preferably formed so as to have a projecting portion having a convex section in a region between the source electrode and the drain electrode.

  In the field effect transistor manufacturing method of the present invention, the first semiconductor layer and the second semiconductor layer are preferably made of a III-V nitride semiconductor.

  According to the field effect transistor and the method of manufacturing the same according to the present invention, a nitride field effect transistor having a T-shaped gate electrode that does not require electron beam exposure in the manufacturing process can be realized.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional configuration of a field effect transistor (FET) according to the first embodiment. As shown in FIG. 1, an undoped GaN film 12 and an n-type doped AlGaN film 13 are sequentially stacked on a substrate 10 made of sapphire with a buffer layer 11 made of AlN interposed. A layer 14 and a second semiconductor layer 15 made of n-doped AlGaN are sequentially formed.

  On the second semiconductor layer 15, a source electrode 17 and a drain electrode 18 in which Ti, Al, Ni, and Au are sequentially stacked are formed at intervals. In the region outside the source electrode 17 and the drain electrode 18, the AlGaN film 13 and part of the GaN film 12 of the second semiconductor layer 15 and the first semiconductor layer 14 are selectively etched for element isolation. Yes.

  In a region sandwiched between the source electrode 17 and the drain electrode 18 of the second semiconductor layer 15, an opening for exposing the AlGaN film 13 is provided. The insulating film 16 covers the side wall of the opening, the upper surface of the second semiconductor layer 15, and the surface of the portion of the first semiconductor layer etched for element isolation. A T-shaped gate electrode 19 made of palladium silicon (PdSi) in contact with the AlGaN film 13 at the bottom of the opening is formed in the opening where the insulating film 16 is formed on the side wall.

  In the FET of this embodiment, the T-shaped gate electrode 19 can be formed by embedding a metal material in the opening as will be described later. Therefore, a gate electrode having a short gate length and a large cross-sectional area can be easily formed without using electron beam lithography.

In the FET of this embodiment, an insulating film 16 made of an oxide film (AlGaNO _x , where 0 <x ≦ 3) formed by oxidizing AlGaN is formed between the second semiconductor layer 15 and the gate electrode 19. ing. As a result, the value of the leak current flowing through the second semiconductor layer 15 between the gate electrode 19 and the source electrode 17 and the drain electrode 18 can be suppressed to be small, for example, the breakdown voltage between the gate and the source is improved. Can do.

FIG. 2 shows a method of manufacturing the field effect transistor according to the first embodiment in the order of steps. First, as shown in FIG. 2A, a thickness of 0.5 μm is formed on the (0001) plane of the sapphire substrate 10 by metal organic chemical vapor deposition (MOCVD). After forming the AlN buffer layer 11, an undoped GaN film 12 having a thickness of 3 μm and an AlGaN film 13 having a thickness of 25 nm are sequentially grown to form a first semiconductor layer 14. On the (0001) plane of the plane orientation, which is the heterojunction interface between the GaN film 12 and the AlGaN film 13, charges are generated due to spontaneous polarization and piezo polarization. Therefore, even when the AlGaN film 13 is undoped, 1 × 10 A two-dimensional electron gas having a sheet carrier concentration of ¹³ cm ⁻² is formed. In the present embodiment, the AlGaN film 13 is doped with Si to form an n-type having a carrier concentration of about 4 × 10 ¹⁸ cm ⁻³ , and the sheet carrier concentration is further increased.

  Even if the vicinity of the interface is undoped to prevent Si diffusion to the interface to improve carrier mobility, or the vicinity of the surface is undoped and the leakage current of the Schottky electrode formed so as to be in contact with the AlGaN film 13 is reduced. Good.

Next, as shown in FIG. 2 (b), the first semiconductor layer 14 in which the GaN film 12 and the AlGaN film 13 are stacked is subjected to dry etching such as ICP (Inductive-Coupled Plasma) etching except for the transistor region. This part of the AlGaN film 13 and part of the undoped GaN film 12 are selectively removed to form a mesa portion. Subsequently, for example, a SiO ₂ film mask having a thickness of 200 nm is formed on the first semiconductor layer 14 by chemical vapor deposition (CVD) using SiH ₄ and O ₂ , and then reactive ion etching ( SiO ₂ is selectively removed using Reactive Ion Etching (RIE) or the like, and a mask 25 is formed in the gate electrode formation region and the stepped portion. Further, the line width is narrowed by etching the mask 25 by RIE or the like. Thereby, the width in the gate length direction can be narrowed, and it becomes easy to form a gate electrode having a short gate length.

Next, using the mask 25 patterned as shown in FIG. 2C, for example, the second semiconductor layer 15 having a thickness of 50 nm is selectively grown by MOCVD. The carrier concentration in the regrown second semiconductor layer 15 is set to a high concentration of, for example, 1 × 10 ¹⁹ cm ⁻³ .

  Next, as shown in FIG. 2D, the mask 25 provided in the gate electrode formation region is covered with a photoresist or the like, and wet-etched with an aqueous HF solution or the like, whereby the mask 25 remaining in the stepped portion. Only remove. Subsequently, a mask 27 made of Si is formed on the source electrode formation region and the drain electrode formation region on the upper surface of the second semiconductor layer 15 by, for example, electron beam evaporation and a lift-off method. Subsequently, the mask 27 is etched by RIE or the like to reduce the line width of the mask 27. In this embodiment, the width of the mask 27 is set smaller than the thickness, and the line width can be narrowed by isotropic gas etching or the like.

Next, as shown in FIG. 2E, the first semiconductor layer 14 and the second semiconductor layer 15 on which the mask 25 made of SiO ₂ and the mask 27 made of Si are formed are formed in an O ₂ atmosphere at 1000 ° C., for example. The surface of the first semiconductor layer 14 and the second semiconductor layer 15 is selectively oxidized to form an insulating film 16 by performing a heat treatment for 4 hours. Since Si diffuses from the mask 27 to the second semiconductor layer 15 side in the oxidation step, the Si concentration on the surface of the second semiconductor layer 15 increases, and the ohmic contact resistance of the source electrode and the drain electrode can be greatly reduced.

  Since the oxidation rate in the (0001) plane of the plane orientation is smaller than the oxidation rate of the (1-100) plane or the (11-20) plane that is a plane perpendicular to the (0001) plane, The thickness of the insulating film 16 formed on the side surface of the semiconductor layer 15 is about five times thicker than the thickness of the insulating film 16 formed on the upper surface of the second semiconductor layer 15 that is the (0001) plane. Here, the “−” sign of the crystal plane index represents the inversion of one index following the sign.

  Next, as shown in FIG. 2F, the mask 25 and the mask 27 are wet-etched with, for example, a hydrofluoric acid solution. Subsequently, the source electrode 17 and the drain electrode 18 in which, for example, Ti, Al, Ni, and Au are stacked are formed on the portion where the mask 27 has been formed.

Next, as shown in FIG. 2G, a gate electrode 19 made of T-shaped PdSi is formed in the portion where the mask 25 has been formed. In the oxidation process, since the insulating film 16 grows in the lateral direction, the width of the opening for forming the gate electrode 19 can be made smaller than the width of the mask 25. For example, even when the width of the mask 25 made of SiO ₂ is about 200 nm, the width of the opening formed after the oxidation step is reduced to about 100 nm. By forming the insulating film 16, a field effect transistor having a shorter gate length can be realized as compared with the case where the gate electrode is directly formed in the opening.

According to the FET of this embodiment and the manufacturing method thereof, an FET having a short gate length of about 100 nm can be formed by an optical stepper without using electron beam lithography. Therefore, it is possible to manufacture a GaN-based FET having a T-shaped short gate that has lower cost and better high-frequency characteristics than conventional ones. Further, since the entire surface of the element other than the electrode is covered with an oxide film made of AlGaNO _x, it is possible to realize an FET having improved element isolation characteristics and a small leakage current.

  The Al composition of the AlGaN film 13 and the second semiconductor layer 15 may be about 25%, but in order to increase the sheet carrier concentration using a two-dimensional electron gas at the heterojunction interface between the AlGaN film 13 and the GaN film 12. The Al composition may be 40% or more. Further, by making the Al composition of the second semiconductor layer 15 higher than the Al composition of the AlGaN film 13, the source electrode and drain electrode side to the channel side at the interface between the AlGaN film 13 and the second semiconductor layer 15. The electron barrier is no longer generated. As a result, the source resistance of the FET can be reduced.

The second semiconductor layer 15 may be a quaternary mixed crystal semiconductor made of InAlGaN. For example, when the Al composition of the AlGaN film 13 is 25% and the second semiconductor layer is In _0.09 Al _0.33 Ga _0.58 N, the polarization of the AlGaN film 13 and the second semiconductor layer 15 becomes equal. Thereby, depletion of electrons at the interface between the AlGaN film 13 and the second semiconductor layer 15 is suppressed, so that the series resistance can be reduced. Further, since InAlGaN has a low electron affinity, the contact resistance between the electrode made of Ti and Al can be reduced.

In order to further reduce the source resistance and the ohmic contact resistance of the source and drain electrodes, the second semiconductor layer 15 is preferably doped with high-concentration Si of 1 × 10 ¹⁹ cm ⁻³ or more as an impurity. At the time of regrowth, since it is desirable that the linearity of the epitaxial growth side surface is good, the direction of the gate finger is desirably the <11-20> direction of the crystallographic axis of the GaN film 12. Here, the “−” sign of the plane index of the zone axis represents the inversion of one index following the sign.

  Further, the crystal of the substrate 10 made of sapphire and the crystal of the GaN film 12 grown thereon are rotated by 30 ° in the (0001) plane of the plane orientation, so that the crystal zone axis of the sapphire substrate is <1-100. It is preferable to form gate fingers in the> direction. Although element isolation is performed by combining step formation and selective oxidation, it may be formed by increasing resistance by ion implantation of boron (B) or the like.

(Second Embodiment)
The second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a cross-sectional configuration of the FET according to the second embodiment. In FIG. 3, the same components as those in FIG.

As shown in FIG. 3, the FET of this embodiment is characterized in that a protrusion 31 is formed in the first semiconductor layer 14. A buffer layer 11 made of AlN is formed on a substrate 10 made of GaN having a very low dislocation density of about 1 × 10 ⁶ cm ⁻² . An undoped GaN film 12 and an n-type AlGaN film 13 are sequentially deposited on the buffer layer 11 to form a first semiconductor layer 14. A protrusion 31 having a width of about 1 μm is formed in a part of the structure of the first semiconductor layer 14 in which the GaN film 12 and the AlGaN film 13 are stacked. The second semiconductor layer 15 made of n-type GaN is regrown so as to cover the upper surface and side surfaces of the protruding portion 31. The regrown second semiconductor layer 15 has an opening exposing the AlGaN film 13, and the upper surface of the second semiconductor layer 15 and the sidewall of the opening are oxidized to form an insulating film 16. . A T-shaped gate electrode 19 made of PdSi is formed in the opening in which the insulating film 16 is formed on the side wall.

In the present embodiment, Si having a high concentration of about 1 × 10 ¹⁹ cm ⁻³ is doped so as to cover the side surface of the protruding portion 31 formed by selectively etching the first semiconductor layer 15. A resistive second semiconductor layer 15 is formed. For this reason, since the current does not flow beyond the heterojunction interface between the AlGaN film 13 and the GaN film 12, the effect of reducing the series resistance can be improved.

  Similarly to the first embodiment, the insulating film 16 formed on the side of the gate electrode 19 can reduce the leakage current flowing between the gate electrode 19 and the source electrode 17 and drain electrode 18. Thereby, the breakdown voltage between the gate and the source can be improved.

  FIG. 4 shows a method of manufacturing an FET according to the second embodiment in the order of steps. As shown in FIG. 4A, first, a buffer layer 11 made of AlN having a thickness of 0.5 μm and a thickness of 3 μm are formed on the (0001) plane of the substrate 10 made of GaN by MOCVD. An undoped GaN film 12 and an n-type AlGaN film 13 having a thickness of 25 nm are sequentially formed.

  When forming the first semiconductor layer 15 in which the GaN film 12 and the AlGaN film 13 are stacked, the vicinity of the interface is undoped to prevent the diffusion of Si to the interface, thereby improving the carrier mobility or the vicinity of the surface Alternatively, the leakage current of the Schottky electrode formed so as to be in contact with the AlGaN film 13 may be reduced.

Next, as shown in FIG. 4B, the AlGaN film is formed on the first semiconductor layer 15 in the source electrode formation region and the drain electrode formation region by dry etching such as ICP etching, and in portions other than the transistor formation region. 13 and a part of the GaN film 12 are selectively removed to form the protrusion 31. Subsequently, a SiO ₂ film having a film thickness of, for example, 200 nm is formed on the first semiconductor layer 15 by the CVD method, and then patterned to form a gate electrode formation region, a source electrode formation region, and a drain electrode formation region outside. A mask 25 covering the region is formed. Further, the line width is narrowed by etching the mask 25 by RIE or the like.

Next, as shown in FIG. 4C, a second semiconductor layer 15 having a thickness of 50 nm and made of n-type GaN is selectively grown on the first semiconductor layer 14 on which the mask 25 is formed by MOCVD. . The carrier concentration of the second semiconductor layer 15 is set to a high concentration of about 1 × 10 ¹⁹ cm ⁻³ . Subsequently, the mask 25 in the gate electrode formation region is covered with a photoresist or the like, and only the mask 25 remaining in the region outside the source electrode formation region and the drain electrode formation region is removed by wet etching with an HF aqueous solution or the like.

  Next, as shown in FIG. 4D, a mask 27 made of Si is formed in the source electrode formation region and the drain electrode formation region on the upper surface of the second semiconductor layer 15 by, for example, electron beam evaporation and a lift-off method.

Subsequently, as shown in FIG. 4E, the first semiconductor layer 14 and the second semiconductor layer 15 on which the mask 25 made of SiO ₂ and the mask 27 made of Si are formed are formed in an O ₂ atmosphere at 1000 ° C., for example. By performing heat treatment for 4 hours, the surfaces of the first semiconductor layer 15 and the second semiconductor layer 15 are selectively oxidized to form the insulating film 16. Since this oxidation process diffuses Si from the mask 27 toward the n-type second semiconductor layer 15 and increases the Si concentration on the surface of the second semiconductor layer 15, the ohmic contact resistance of the source electrode 17 and the drain electrode 18 is increased. Can be greatly reduced. In this embodiment, since the ohmic electrode is formed on the GaN, the ohmic contact resistance can be reduced as compared with the case where the ohmic electrode is formed on the AlGaN, and a contact resistance of 5 × 10 ⁻⁶ Ωcm ² or less. realizable.

  Next, as shown in FIG. 4F, the mask 25 and the mask 27 are wet-etched using, for example, a hydrofluoric acid solution, and then the portion of the second semiconductor layer 15 where the mask 27 is formed, for example, Ti and Al. A source electrode 17 and a drain electrode 18 in which Ni and Au are laminated are formed.

Next, as shown in FIG. 4G, a T-shaped gate electrode 19 made of PdSi is formed in the portion where the mask 25 is formed. In the oxidation process, since the insulating film 16 grows in the lateral direction, the width of the opening for forming the gate electrode 19 can be made smaller than the width of the mask 25. For example, even when the width of the mask 25 made of SiO ₂ is about 200 nm, the width of the opening formed after the oxidation step is reduced to about 100 nm. By forming the insulating film 16, a field effect transistor having a shorter gate length can be realized as compared with the case where the gate electrode is directly formed in the opening.

  According to the FET of this embodiment and the manufacturing method thereof, an FET having a short gate length of about 100 nm can be formed by an optical stepper without using electron beam lithography. Therefore, it is possible to manufacture a GaN-based FET having a T-shaped short gate that has lower cost and better high-frequency characteristics than conventional ones. In addition, since the entire surface of the element other than the electrode is covered with the selective oxide film, it is possible to realize an FET with improved element isolation characteristics and a small leakage current.

In the FET of this embodiment, a stack of Ti, Al, Ni, and Au is used for the source electrode 17 and the drain electrode 18, and the source electrode 17 and the drain electrode 18 are in contact with the upper surface of the second semiconductor layer 15. The amount is formed. The second semiconductor layer 15 below the source electrode 17 and the drain electrode 18 has a surface layer doped with Si at a high concentration, and the ohmic contact resistance is reduced to about 2 × 10 ⁻⁶ Ωcm ² .

  The FET of the present embodiment can pass a current through the two-dimensional electron gas channel without going through the AlGaN / GaN hetero barrier. In addition, the ionization energy of Si is smaller in GaN than in AlGaN, and the carrier concentration can be increased. Furthermore, the ohmic contact resistance of the source electrode and the drain electrode can be made smaller when formed on GaN than when formed on AlGaN. It becomes possible to realize a field effect transistor having a smaller series resistance.

  In addition, it is desirable that the linearity of the regrowth surface can be further improved by setting the direction of the gate finger to the <11-20> direction of the zonal axis of the GaN film.

Note that the second semiconductor layer 15 may be a quaternary mixed crystal semiconductor made of In _0.09 Al _0.33 Ga _0.58 N or the like. Thereby, the electron affinity is reduced, and the contact resistance between the electrode made of Ti and Al can be reduced.

(Third embodiment)
The third embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows a cross-sectional configuration of the FET according to the third embodiment. In FIG. 5, the same components as those of FIG.

As shown in FIG. 5, the FET of this embodiment is characterized in that a heterostructure made of AlN and GaN is used. By using a heterostructure composed of AlN and GaN, the sheet carrier concentration after forming the heterojunction can be reduced to 1 × 10 ¹² cm ⁻² . Further, the threshold voltage can be controlled by changing the AlN film thickness by an internal electric field accompanying polarization in the AlN film. By making the film thinner, the threshold voltage can be set to a positive voltage, so that a normally-off FET can be formed.

  FIG. 6 shows the result of measurement of the relationship between the drain current and gate voltage of the FET of this embodiment. The FET in this embodiment shows normally-off characteristics with a threshold voltage of around 0V. On the other hand, in the case of the FET having the heterojunction structure composed of AlGaN and GaN shown in the second embodiment, the normally-on characteristic with a threshold voltage of about −2V was shown. In FIG. 6, the thickness of the AlN film and the AlGaN film was 25 nm.

In this embodiment, GaN is not used for the substrate, but a crystal growth mask made of SiO ₂ is used, and crystal defects are reduced by regrowth called ELO (Epitaxial lateral Overgrowth). Specifically, a crystal growth mask made of SiO ₂ is formed in a stripe shape parallel to the gate electrode, for example, on a substrate made of sapphire, and an undoped GaN film is regrown thereon, thereby causing a dislocation density of 1 × 10 6. It can be reduced to about ⁶ cm ^-2 .

FIG. 7 shows a method of manufacturing an FET according to the second embodiment in the order of steps. First, as shown in FIG. 7A, a buffer layer 11 made of AlN having a thickness of 1 μm is formed on the (0001) plane of the substrate 10 made of sapphire by MOCVD, and then CVD is used. A crystal growth mask 65 made of SiO ₂ having a thickness of 100 nm is formed.

  Next, as shown in FIG. 7B, the crystal growth mask 65 is patterned, for example, in a stripe shape having a width of 10 μm and an opening of 2 μm, and an undoped layer having a thickness of 3 μm is formed thereon using the MOCVD method. A GaN film 12 and an undoped AlN film 63 are sequentially formed.

Next, as shown in FIG. 7C, the AlN film 63 is formed on the first semiconductor layer 15 by dry etching such as ICP etching in the source electrode formation region and the drain electrode formation region and in the portion other than the transistor formation region. And a part of the GaN film 12 are selectively removed to form the protrusion 31. Subsequently, a SiO ₂ film having a film thickness of, for example, 200 nm is formed on the first semiconductor layer 15 by the CVD method, and then patterned to form a gate electrode formation region, a source electrode formation region, and a drain electrode formation region outside. A mask 25 covering the region is formed. Further, the line width is narrowed by etching the mask 25 by RIE or the like.

Next, as shown in FIG. 7D, a second semiconductor layer 15 having a thickness of 50 nm and made of n-type GaN is selectively grown on the first semiconductor layer 14 on which the mask 25 is formed by MOCVD. . The carrier concentration of the second semiconductor layer 15 is set to a high concentration of about 1 × 10 ¹⁹ cm ⁻³ . Subsequently, the mask 25 in the gate electrode formation region is covered with a photoresist or the like, and only the mask 25 remaining in the region outside the source electrode formation region and the drain electrode formation region is removed by wet etching with an HF aqueous solution or the like.

  Next, as shown in FIG. 7D, a mask 27 made of Si is formed in the source electrode formation region and the drain electrode formation region on the upper surface of the second semiconductor layer 15 by, for example, electron beam evaporation and a lift-off method.

Subsequently, as shown in FIG. 7E, the epitaxial growth layer on which the mask 25 made of SiO ₂ and the mask 27 made of Si are formed is heat-treated in an O ₂ atmosphere at 1000 ° C. for 4 hours, for example, thereby Selectively oxidize. This oxidation process diffuses Si from the mask 27 toward the n-type second semiconductor layer 15 and increases the Si concentration on the surface of the second semiconductor layer 15, greatly increasing the ohmic contact resistance of the source and drain electrodes. Can be reduced. In the first embodiment, the source electrode and the drain electrode are formed on the AlGaN film. However, in this embodiment, since the electrode is formed on the GaN film, the ohmic contact resistance can be further reduced. A contact resistance of 10 ⁻⁶ Ωcm ² or less can be realized.

  Next, as shown in FIG. 7F, the mask 25 and the mask 27 are wet-etched using, for example, a hydrofluoric acid solution, and then the portion of the second semiconductor layer 15 where the mask 27 is formed, for example, Ti and Al. A source electrode 17 and a drain electrode 18 in which Ni and Au are laminated are formed.

Next, as shown in FIG. 7G, a T-shaped gate electrode 19 made of PdSi is formed in the portion where the mask 25 is formed. Since the oxide film grows in the lateral direction in the oxidation step, the width of the opening for forming the gate electrode 19 can be made smaller than the width of the mask 25. For example, even when the width of the mask 25 made of SiO ₂ is about 200 nm, the width of the opening formed after the oxidation step is reduced to about 100 nm. By forming the insulating film 16, a field effect transistor having a shorter gate length can be realized as compared with the case where the gate electrode is directly formed in the opening.

  According to the FET of this embodiment and the manufacturing method thereof, an FET having a short gate length of about 100 nm can be formed by an optical stepper without using electron beam lithography. Therefore, it is possible to manufacture a GaN-based FET having a T-shaped short gate that has lower cost and better high-frequency characteristics than conventional ones. In addition, since the entire surface of the element other than the electrode is covered with the selective oxide film, it is possible to realize an FET with improved element isolation characteristics and a small leakage current.

  In addition, since it has a heterostructure composed of AlN and GaN, a normally-off operation that is indispensable as a high-power transistor can be realized while keeping the on-resistance small by reducing the thickness of the AlN film 63.

(One Modification of Third Embodiment)
A modification of the third embodiment will be described below with reference to the drawings. FIG. 8 shows a cross-sectional configuration of a semiconductor device according to a modification of the third embodiment. In FIG. 8, the same components as those in FIG.

  As shown in FIG. 8, in the semiconductor device of this modification, the first semiconductor layer 14 and the second semiconductor layer 15 are formed on the R plane which is the (1-102) plane of the plane orientation of the substrate 40 made of sapphire. Is formed. The main surfaces of the first semiconductor layer 14 and the second semiconductor layer 15 formed on the R-plane of the substrate 40 are A-planes that are (11-20) planes of the plane orientation. In the A plane, polarization does not occur perpendicular to the plane, so that no carriers are generated at the undoped heterointerface. The AlN film 63 has a very large forbidden band of 6.2 eV, so that it can generate carriers at the heterointerface for the first time when a positive voltage is applied to the gate, and has a MIS (Metal-Insulator-Semiconuctor) type structure. It becomes. Therefore, a so-called normally-off operation can be easily realized, a large positive voltage of, for example, 5 V or more can be applied to the gate electrode, and the drain current can be increased. Note that the width of the protrusion 31 is preferably narrow in order to reduce the on-resistance and the parasitic resistance.

  In this modification, the surface orientation of the main surface of the substrate is (11-20), but it may be a nonpolar surface such as the (1-100) surface.

  In each embodiment and modification, the gate electrode is formed so as to be in contact with the oxide film formed on the surface of the second semiconductor layer. After the oxide film is removed, T is formed in the opening of the second semiconductor layer. The letter-shaped gate may be formed by patterning by a photolithography process. In this case, the gate electrode may not be in contact with the sidewall of the opening. In addition, although the opening is formed by forming the second semiconductor layer after forming the mask, the opening may be formed by etching after forming the second semiconductor layer. When the opening is formed by etching, depending on the configuration of the semiconductor layer, the second semiconductor layer may be left on the bottom surface of the opening without penetrating the second semiconductor layer.

In addition to sapphire and GaN, the substrate may be SiC, ZnO, Si, GaAs, GaP, InP, LiGaO ₂ , LiAlO _2, or a mixed crystal of LiGaO ₂ and LiAlO ₂ . The buffer layer is not only an AlN layer, but Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) as long as a good GaN crystal can be formed on the buffer layer. A nitride semiconductor represented by the following may be used.

  As long as desired transistor characteristics can be realized, the first semiconductor layer 14 may be freely selected in terms of the number of layers, composition, stacking order, etc. of the semiconductor film. The crystal growth method of the epitaxially grown layer is replaced by MOCVD instead of MOCVD. (Molecular Beam Epitaxy: MBE) or Hydride Vapor Phase Epitaxy (HVPE) may be used. The epitaxial growth layer may contain a group V element such as As or P or a group III element such as B as a constituent element.

  The field effect transistor and the method for manufacturing the same according to the present invention can realize a nitride field effect transistor having a T-shaped gate electrode that does not require electron beam exposure in the manufacturing process. Useful as a method.

It is sectional drawing which shows the field effect transistor which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the 1st Embodiment of this invention in process order. It is sectional drawing which shows the field effect transistor which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the 2nd Embodiment of this invention in process order. It is sectional drawing which shows the field effect transistor which concerns on the 3rd Embodiment of this invention. It is a graph which shows the relationship between the drain current and gate voltage of the field effect transistor which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the 3rd Embodiment of this invention in process order. It is sectional drawing which shows the field effect transistor which concerns on the modification of the 3rd Embodiment of this invention. It is sectional drawing which shows the field effect transistor which concerns on a prior art example.

Explanation of symbols

10 substrate 11 buffer layer 12 GaN film 13 AlGaN film 14 first semiconductor layer 15 second semiconductor layer 16 oxide film 17 source electrode 18 drain electrode 19 gate electrode 25 mask 27 mask 31 protrusion 40 substrate 63 AlN film 65 crystal growth mask

Claims (20)

A first semiconductor layer formed by laminating a plurality of semiconductor films;
A second semiconductor layer formed in contact with the main surface of the first semiconductor layer;
A source electrode and a drain electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer and spaced from each other;
An opening formed in a region sandwiched between the source electrode and the drain electrode in the second semiconductor layer, and exposing the first semiconductor layer;
An insulating film formed on the sidewall of the opening;
A field effect transistor comprising: a gate electrode in contact with the insulating film and in contact with an exposed portion from the opening in the first semiconductor layer.   The field effect transistor according to claim 1, wherein the first semiconductor layer has a two-dimensional electron gas layer generated in a region below the gate electrode.   The field effect transistor according to claim 1, wherein the insulating film is an oxide film obtained by oxidizing the second semiconductor layer.   4. The electric field according to claim 1, wherein the insulating film is formed to cover a region sandwiched between the source electrode and the drain electrode in the second semiconductor layer. 5. Effect transistor.   The field effect transistor according to claim 4, wherein the insulating film has a thickness of a portion formed on a side wall of the opening portion larger than a thickness of other portions.   6. The portion of the first semiconductor layer that is in contact with the gate electrode and the second semiconductor layer are different in at least one of carrier concentration and composition. The field effect transistor according to 1. A first semiconductor layer formed by laminating a plurality of semiconductor films;
A second semiconductor layer formed in contact with the main surface of the first semiconductor layer;
A source electrode and a drain electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer and spaced from each other;
An opening formed in a region sandwiched between the source electrode and the drain electrode in the second semiconductor layer, and exposing the first semiconductor layer;
A gate electrode in contact with an exposed portion from the opening in the first semiconductor layer,
The field effect transistor according to claim 1, wherein the first semiconductor layer has a protruding portion protruding in a convex section in a region sandwiched between the source electrode and the drain electrode.   The field effect transistor according to claim 7, further comprising an insulating film formed on a sidewall of the opening.   The field effect transistor according to claim 7, wherein the protrusion includes a two-dimensional electron gas layer generated so as to cross the side wall of the protrusion.   The field effect transistor according to any one of claims 1 to 9, wherein the first semiconductor layer and the second semiconductor layer are made of a group III-V nitride semiconductor. The first semiconductor layer includes a gallium nitride film, and a film formed on the gallium nitride film and having a general formula of Al _x Ga _1-x N (where 0 <x ≦ 1) The field effect transistor according to claim 10, comprising: The second semiconductor layer is represented by gallium nitride or a general formula of In _y Al _z Ga _(1-yz) N (where 0 <y <1, 0 <z <1, y + z <1). The field effect transistor according to claim 10, wherein the field effect transistor is a compound. The first semiconductor layer includes a gallium nitride film formed on the main surface of the substrate and the main surface being a (11-20) plane having a plane orientation,
The field effect transistor according to claim 10, wherein the substrate is made of sapphire whose principal surface is a (1-102) plane having a plane orientation. The first semiconductor layer is formed on a main surface of a substrate whose main surface is a (0001) plane having a plane orientation,
11. The field effect transistor according to claim 10, wherein the gate electrode is formed linearly along the <11-20> direction of the zone axis of the substrate. Forming a first semiconductor layer in which a plurality of semiconductor films are stacked on a substrate;
A step (b) of selectively forming a mask on the first semiconductor layer;
Forming a second semiconductor layer on the first semiconductor layer using the mask (c);
Forming an opening in the second semiconductor layer by removing the mask (d);
Forming a gate electrode in a region including the opening of the second semiconductor layer so as to be in contact with the first semiconductor layer exposed from the opening;
And (f) forming a source electrode and a drain electrode in regions on both sides of the gate electrode on the second semiconductor layer, respectively.   The method further comprises the step (h) of oxidizing the surface of the second semiconductor layer to form an insulating film after the step (c) and before the step (e). The method of manufacturing a field effect transistor according to claim 15.   The electric field according to claim 16, further comprising a step (g) of reducing a width in a gate length direction of the mask by etching between the step (b) and the step (c). Effect transistor manufacturing method. In the step (b), the width of the mask in the gate length direction is formed smaller than the thickness,
18. The method of manufacturing a field effect transistor according to claim 17, wherein isotropic etching is performed in the width direction and the thickness direction in the step (g).   19. The step (a), wherein the first semiconductor layer is formed so as to have a projecting portion having a convex cross section in a region between the source electrode and the drain electrode. 2. A method for producing a field effect transistor according to item 1.   20. The method of manufacturing a field effect transistor according to claim 15, wherein the first semiconductor layer and the second semiconductor layer are made of a group III-V nitride semiconductor.

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