JP2010165987A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device composed of nitride semiconductors which has excellent reliability and normally-off characteristics without any fluctuation in characteristics while simplifying a manufacturing process. <P>SOLUTION: The semiconductor device includes: a channel layer 103 composed of a nitride semiconductor; an electron supply layer 104 formed on the channel layer 103 and composed of a nitride semiconductor whose band gap energy is larger than that of the channel layer 103; a p-type semiconductor layer 105 selectively formed on the electron supply layer 104; a gate electrode 106 formed on the p-type semiconductor layer 105; and a source electrode 107 and a drain electrode 108 which are respectively formed on both side areas of the gate electrode 106 so as to be in contact with at least the electron supply layer 104. The p-type semiconductor layer 105 is composed of a hexagonal II-VI group compound semiconductor, for example, p-type ZnO. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device made of a nitride semiconductor and a manufacturing method thereof.

  Gallium nitride (GaN) -based nitride semiconductors have a high dielectric breakdown field and a high saturation drift velocity because of their large band gap compared to compound semiconductors such as silicon (Si) semiconductors or gallium arsenide (GaAs). Therefore, it is attracting attention for application of electronic devices such as high voltage power devices and high-speed high-power transistors.

In particular, this GaN-based nitride semiconductor is generally formed in the (0001) plane of the plane orientation, for example, in a heterojunction made of AlGaN / GaN, it is 10 ¹³ cm ⁻² or more due to the influence of polarization even if it is undoped. A great feature is that a high sheet carrier concentration can be obtained. Thereby, an AlGaN / GaN heterojunction field effect transistor (HFET) with a large drain current can be realized. Thus, power switching elements are promising as an application field of GaN-based electronic devices that take advantage of the feature of being capable of large current operation. In order to put this into practical use, there is a strong demand for a high breakdown voltage and a normally-off configuration that prevents current from flowing when no voltage is applied to the gate electrode.

Hereinafter, a junction field effect transistor in which a p-type GaN layer is formed in a gate portion will be described as a structure that achieves both a normally-off type and a low on-resistance (see, for example, Patent Document 1).
FIG. 7 shows a cross-sectional configuration of a junction field effect transistor that realizes normally-off according to a conventional example. As shown in FIG. 7, a barrier layer 4 made of AlGaN is formed on the upper surface of the channel layer 2 made of GaN. A source electrode 12 and a drain electrode 14 are formed on the n-type barrier layer 4, and a gate with a p-type base layer 6 made of p-type GaN interposed between the source electrode 12 and the drain electrode 14. An electrode 16 is formed.

Here, after the p-type base layer 6 is formed on the barrier layer 4, the region excluding the gate electrode formation region in the p-type base layer 6 is selectively etched by dry etching using chlorine gas or the like. .
Japanese Patent Laying-Open No. 2005-244072 (FIG. 1)

  However, it is difficult for the conventional junction field effect transistor to selectively etch p-type GaN constituting the p-type base layer 6 and AlGaN constituting the barrier layer 4. For this reason, a part of the p-type base layer 6 remains without being etched, or conversely, over-etching of the barrier layer 4 occurs. As a result, there arises a problem that the electric characteristics of the transistors vary and the manufacturing yield deteriorates.

  An object of the present invention is to solve the above-mentioned conventional problems and to realize a semiconductor device made of a nitride semiconductor having normally-off characteristics with excellent characteristics and no variation in characteristics while simplifying the manufacturing process. Objective.

  In order to achieve the above object, a first semiconductor device according to the present invention is configured to use a hexagonal II-VI group compound semiconductor for a p-type semiconductor layer provided below a gate electrode.

  Specifically, a first semiconductor device according to the present invention is formed on a first semiconductor layer made of a nitride semiconductor and the first semiconductor layer, and has a band gap energy larger than that of the first semiconductor layer. A second semiconductor layer made of a nitride semiconductor, a p-type third semiconductor layer made of a hexagonal II-VI group compound semiconductor and selectively formed on the second semiconductor layer; A gate electrode formed on the semiconductor layer, and a source electrode and a drain electrode formed on regions on both sides of the gate electrode.

  According to the first semiconductor device of the present invention, since the hexagonal p-type II-VI compound semiconductor is used as the third semiconductor layer on which the gate electrode is formed, the lower side of the third semiconductor layer is used. It becomes easy to selectively process the formed second semiconductor layer made of a nitride semiconductor. Therefore, a normally-off field effect transistor with small variations in electrical characteristics and excellent reliability can be realized.

In the first semiconductor device of the present invention, Zn _1-x Mg _x O (where x is 0 ≦ x <1) can be used for the third semiconductor layer.

  In the first semiconductor device of the present invention, the second semiconductor layer may have a recess, and the third semiconductor layer may be formed to cover the bottom surface of the recess.

  As described above, the structure in which the gate electrode formation region in the second semiconductor layer that is the electron supply layer is dug out allows the gate threshold voltage to be reduced without lowering the carrier concentration of the first semiconductor layer that is the channel layer. Can be shifted to the positive voltage side. As a result, it is possible to achieve both normally-off and reduction of on-resistance, and it is possible to suppress the current collapse phenomenon.

  In the first semiconductor device of the present invention, the third semiconductor layer may have a stacked structure including at least two layers.

  In this case, since the band gap energy in the third semiconductor layer can be changed, for example, by the Mg content in ZnMgO, the gate threshold voltage can be controlled in a wider range.

In the first semiconductor device of the present invention, when Zn _1-x Mg _x O (where x is 0 ≦ x <1) is used for the third semiconductor layer, Mg in the third semiconductor layer The value of the composition x is substantially constant, and the second semiconductor layer and the third semiconductor layer are preferably lattice-matched.

  Thus, the crystallinity of the third semiconductor layer can be improved.

In the case where the first semiconductor device of the present invention uses Zn _1-x Mg _x O (where x is 0 ≦ x <1) in the third semiconductor layer, the third semiconductor layer includes The Mg composition x may be formed so as to increase from the second semiconductor layer side toward the gate electrode side.

  In this case, the lattice constant of the third semiconductor layer increases from the second semiconductor layer side to the gate electrode side, so that the stacked layer made of ZnO / ZnMgO does not generate cracks in the third semiconductor layer. Since the structure can be formed, the gate threshold voltage can be controlled by the composition design of ZnMgO.

  In the second semiconductor device according to the present invention, a compound semiconductor having a delafossite structure or a chalcogenide structure containing oxygen or sulfur as a constituent element is used for the p-type semiconductor layer provided below the gate electrode.

  Specifically, a second semiconductor device according to the present invention is formed on a first semiconductor layer made of a nitride semiconductor and the first semiconductor layer, and has a band gap energy higher than that of the first semiconductor layer. A second semiconductor layer made of a large nitride semiconductor, a compound semiconductor having a delafossite structure or a chalcogenide structure selectively formed on the second semiconductor layer and containing oxygen or sulfur as a constituent element, and p A third semiconductor layer of the type; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed in regions on both sides of the gate electrode. .

  According to the second semiconductor device of the present invention, a p-type compound semiconductor compound semiconductor having a delafossite structure or a chalcogenide structure containing oxygen or sulfur as a constituent element is used as the third semiconductor layer in which the gate electrode is formed. Therefore, it becomes easy to selectively process the second semiconductor layer made of the nitride semiconductor formed below the third semiconductor layer. Therefore, a normally-off field effect transistor with small variations in electrical characteristics and excellent reliability can be realized.

  In the second semiconductor device of the present invention, the third semiconductor layer preferably includes a transition metal element as a constituent element.

  In this case, the transition metal is preferably Cu.

In the second semiconductor device of the present invention, the third semiconductor layer is preferably any one of CuAlO ₂ , SrCu ₂ O ₂ , LaCuOS, and LaCuOSe.

  The first method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first semiconductor layer made of a nitride semiconductor on a substrate, and a first semiconductor layer on the first semiconductor layer. A step (b) of forming a second semiconductor layer made of a nitride semiconductor having a band gap energy larger than that of the semiconductor layer, and a hexagonal II-VI group compound on the second semiconductor layer and p A step (c) of forming a third semiconductor layer of the mold, a step (d) of selectively removing a region excluding the gate electrode formation region in the third semiconductor layer after the step (c), And (e) a step of selectively forming a gate electrode on the three semiconductor layers.

  According to the first method for manufacturing a semiconductor device of the present invention, a p-type third semiconductor layer made of a hexagonal II-VI group compound and formed on the second semiconductor layer is formed. A region excluding the gate electrode formation region in the semiconductor layer is selectively removed. For this reason, the third semiconductor layer can be selectively etched with respect to the second semiconductor layer made of a nitride semiconductor formed below the third semiconductor layer. As a result, a normally-off field effect transistor with small variations in electrical characteristics and excellent reliability can be realized.

  The second method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first semiconductor layer made of a nitride semiconductor on a substrate; A step (b) of forming a second semiconductor layer made of a nitride semiconductor having a band gap energy larger than that of the first semiconductor layer; and a delafolite containing oxygen or sulfur as a constituent element on the second semiconductor layer. Step (c) of forming compound semiconductor of site structure or chalcogenide structure and forming p-type third semiconductor layer, and region after gate electrode formation region in third semiconductor layer after step (c) A step (d) of selectively removing the gate electrode and a step (e) of selectively forming a gate electrode on the third semiconductor layer.

  According to the second method for manufacturing a semiconductor device of the present invention, the p-type third layer is made of a compound semiconductor having a delafossite structure or a chalcogenide structure containing oxygen or sulfur as a constituent element on the second semiconductor layer. After that, the region excluding the gate electrode formation region in the third semiconductor layer is selectively removed. For this reason, the third semiconductor layer can be selectively etched with respect to the second semiconductor layer made of a nitride semiconductor formed below the third semiconductor layer. As a result, a normally-off field effect transistor with small variations in electrical characteristics and excellent reliability can be realized.

  In the first or second method for manufacturing a semiconductor device of the present invention, in the step (d), the third semiconductor layer is preferably removed by wet etching.

  Thus, the third semiconductor layer can be etched with high selectivity, and damage caused by etching can be reduced.

  In the manufacturing method of the first or second semiconductor device of the present invention, in the step (c), the third semiconductor layer can be formed by a physical vapor deposition method.

  In the manufacturing method of the first or second semiconductor device of the present invention, after the step (d), the source electrode and the drain electrode are respectively formed in regions on both sides of the third semiconductor layer in the second semiconductor layer. The process (f) to perform may be further provided.

  In the manufacturing method of the first or second semiconductor device of the present invention, in the step (f), the source electrode and the drain electrode may be formed so as to be in contact with the first semiconductor layer.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to realize a semiconductor device having normally-off characteristics that suppresses variations in electrical characteristics and has a high manufacturing yield.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a semiconductor device according to a first embodiment of the present invention, and schematically shows a cross-sectional configuration of a heterojunction field effect transistor.

As shown in FIG. 1, the field effect transistor according to the first embodiment is sequentially formed on the main surface of a substrate 101 on which a group III nitride semiconductor such as silicon, sapphire, or gallium nitride (GaN) can grow. The buffer layer 102 made of GaN or aluminum nitride (AlN), the channel layer 103 made of undoped GaN having a thickness of about 3 μm, and the electrons made of Al _0.15 Ga _0.85 N having a thickness of 25 nm. And a supply layer 104.

  A p-type semiconductor layer 105 made of zinc oxide (ZnO) having a thickness of 200 nm and containing p-type impurities is selectively formed on the electron supply layer 104. On the p-type semiconductor layer 105, a gate electrode 106 made of, for example, palladium (Pd) is provided in ohmic contact with the p-type semiconductor layer 105. Further, a source electrode 107 and a drain electrode 108 made of titanium (Ti) / aluminum (Al) are provided on both sides of the p-type semiconductor layer 105 on the electron supply layer 104. Note that the source electrode 107 and the drain electrode 108 may be formed such that the electron supply layer 104 is dug so that the lower portions of the electrodes 107 and 108 are in contact with the channel layer 103.

  Further, around the element formation region, an element isolation region 109 having high resistance is formed by implanting ions such as boron (B).

  Hereinafter, a method of manufacturing the field effect transistor configured as described above will be described with reference to FIGS.

First, as shown in FIG. 2A, a buffer layer 102, a channel layer 103 made of undoped GaN, and the like are formed on the main surface of the substrate 101 by, for example, metal organic chemical vapor deposition (MOCVD). The electron supply layer 104 made of Al _0.15 Ga _0.85 N is sequentially epitaxially grown.

  Next, as shown in FIG. 2B, element isolation is performed by implanting boron ions, for example, into the region from the electron supply layer 104 to the channel layer 103 around the element formation region in the epitaxially grown semiconductor layer. Region 109 is formed.

  Next, as shown in FIG. 2C, the electron supply layer 104 including the element isolation region 109 is formed by a physical vapor deposition method such as a sputtering method or a pulsed laser deposition (PLD) method. Then, a p-type ZnO layer 105A having a thickness of 200 nm is formed. Here, for example, nitrogen (N) or arsenic (As) can be used as the p-type dopant. Since ZnO has a lattice constant close to that of GaN or AlN, the p-type ZnO layer 105A excellent in crystallinity and flatness can be formed on the electron supply layer 104 made of AlGaN.

Next, as shown in FIG. 2D, a region except the gate electrode formation region in the p-type ZnO layer 105A is selectively etched by a lithography method and a wet etching method using nitric acid (HNO ₃ ). A p-type semiconductor layer 105 is formed from the p-type ZnO layer 105A. At this time, since GaN and AlGaN which are nitride semiconductors are not etched by nitric acid, only the p-type ZnO layer 105A can be selectively etched. Accordingly, it is possible to prevent deterioration in manufacturing yield and variation in electrical characteristics due to etching residue of the p-type ZnO layer 105A or overetching of the electron supply layer 104. In addition, wet etching can reduce defects generated at the etching interface as compared with dry etching.

  Next, a resist pattern (not shown) having openings in the electrode formation regions of the source electrode and the drain electrode is formed on the electron supply layer 104 including the p-type semiconductor layer 105 by lithography. Subsequently, a laminated film made of Ti / Al is deposited on the resist pattern including the opening by an electron beam vapor deposition method, and then the resist pattern is removed, and a so-called lift-off method is shown in FIG. Thus, the source electrode 107 and the drain electrode 108 made of Ti / Al are formed. Subsequently, a gate electrode 106 made of Pd is selectively formed on the p-type semiconductor layer 105 by an electron beam evaporation method and a lift-off method.

In the first embodiment, p-type Zn _1-x Mg _x O containing Mg (where x is 0 ≦ x <1) may be used for the p-type semiconductor layer 105. At this time, it is preferable that the value of the Mg composition x is substantially constant, and the p-type semiconductor layer 105 made of p-type Zn _1-x Mg _x O and the electron supply layer 104 made of AlGaN are lattice-matched. Thus, even when the composition of the electron supply layer 104 is changed, the p-type semiconductor layer 105 is lattice-matched to the electron supply layer 104 by adjusting the Mg content of the p-type semiconductor layer 105. Therefore, the crystallinity of the p-type semiconductor layer 105 is improved.

  Here, the value of the Mg composition x being substantially constant does not necessarily have to be strictly constant, and no lattice mismatch occurs between the p-type semiconductor layer 105 and the electron supply layer 104. The degree may vary. For example, the maximum value and the minimum value of the Mg composition x are within ± 5% of the average value of the composition x (that is, when the average value of the composition x is 0.5, x = 0. 525 to 0.475), and more preferably within ± 1%. When the Mg composition x = 0, that is, when the p-type semiconductor layer 105 does not contain Mg, the Mg content may be equal to or less than the background of the measured value.

As described above, according to the first embodiment, the p-type semiconductor layer 105 bonded to the gate electrode 106 has a hexagonal II-VI group compound semiconductor such as p-type Zn _1-x Mg _x O (provided that By forming x, 0 ≦ x <1, it is easy to selectively pattern the electron supply layer 104 made of AlGaN formed below the p-type semiconductor layer 105. It becomes like this. As a result, it is possible to obtain a junction field effect transistor having normally-off characteristics with high manufacturing yield while suppressing variation in electrical characteristics of the transistors.

(First modification of the first embodiment)
Hereinafter, a first modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 is a semiconductor device according to a first modification of the first embodiment of the present invention, and schematically shows a cross-sectional configuration of a heterojunction field effect transistor. In FIG. 3, the same components as those shown in FIG.

In the first modification, the electron supply layer 104A made of Al _0.15 Ga _0.85 N has a thickness of 50 nm, and the p-type semiconductor layer 105 is formed in a recess 104a having a depth of 30 nm, for example. Is provided.

  The p-type semiconductor layer 105 made of p-type ZnO having a thickness of 200 nm is formed so that the lower portion thereof is filled in the recess 104a provided in the electron supply layer 104A.

  Hereinafter, a method of manufacturing the field effect transistor configured as described above will be described with reference to FIGS.

First, as shown in FIG. 4A, an electron supply made of a buffer layer 102, a channel layer 103 made of undoped GaN, and Al _0.15 Ga _0.85 N is formed on the main surface of the substrate 101 by, eg, MOCVD. The layer 104A is epitaxially grown sequentially.

  Next, as shown in FIG. 4B, a recess 104a having a depth of 30 nm is formed in the electron supply layer 104A having a thickness of 50 nm by lithography and dry etching.

  Next, as shown in FIG. 4C, element isolation is performed by implanting boron ions, for example, into the region from the electron supply layer 104A to the channel layer 103 around the element formation region in the epitaxially grown semiconductor layer. Region 109 is formed.

  Next, as shown in FIG. 4D, a p-type ZnO layer 105A having a thickness of 200 nm is formed on the electron supply layer 104A including the element isolation region 109 and the recess 104a by, for example, sputtering or PLD. To do.

Next, as shown in FIG. 4E, a region except the gate electrode formation region in the p-type ZnO layer 105A is selectively etched by a lithography method and a wet etching method using HNO ₃ to form p-type ZnO. A p-type semiconductor layer 105 is formed from the layer 105A. At this time, as described above, since GaN and AlGaN are not etched with nitric acid, only the p-type ZnO layer 105A can be selectively etched.

  Next, as shown in FIG. 4F, similarly to the first embodiment, the source electrode 107 made of Ti / Al and the regions on both sides of the p-type semiconductor layer 105 on the electron supply layer 104A and A drain electrode 108 is formed. Subsequently, a gate electrode 106 made of Pd is selectively formed on the p-type semiconductor layer 105.

  As described above, according to the first modification, the recess 104a is formed in the region below the gate electrode 106 in the electron supply layer 104A, and the lower portion of the p-type semiconductor layer 105 is formed in the formed recess 104a. As a result, the gate threshold voltage can be shifted to the positive voltage side without lowering the carrier concentration in the channel layer 103, so that normally-off can be more reliably performed.

(Second modification of the first embodiment)
Hereinafter, a second modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 is a semiconductor device according to a second modification of the first embodiment of the present invention, and schematically shows a cross-sectional configuration of a heterojunction field effect transistor. In FIG. 5, the same components as those shown in FIG.

In the second modification, p-type Zn _1-x Mg _x O is provided between the p-type semiconductor layer 105 made of p-type ZnO and the gate electrode 106 (where x is 0 <x <1). A layer 110 is provided.

Here, the thickness of the p-type semiconductor layer 105 is, for example, 20 nm, and the thickness of the Zn _1-x Mg _x O layer 110 is, for example, 180 nm.

  In this manner, since zinc magnesium oxide (ZnMgO) has a larger band gap energy than zinc oxide (ZnO), the amount of increase (increase) in potential energy at the lower portion of the gate electrode 106 can be increased. For this reason, the normally-off state in which the gate threshold voltage is shifted to the positive voltage side can be more reliably realized.

A p-type semiconductor layer 105 made of p-type ZnO is provided on the electron supply layer 104 side made of AlGaN, and a Zn _1-x Mg _x O layer 110 is provided on the gate electrode 106 side. As a result, the value of the Mg composition x in the Zn _1-x Mg _x O layer 110 increases from the electron supply layer 104 side to the gate electrode 106 side. Since ZnMgO has a larger lattice constant than ZnO, a laminated structure made of ZnO / ZnMgO can be formed without generating cracks. Therefore, the gate threshold voltage can be controlled by the composition design of the Zn _1-x Mg _x O layer 110.

In order to form the Zn _1-x Mg _x O layer 110, after a p-type semiconductor layer 105 made of p-type ZnO is grown, a predetermined amount of Mg is added to the raw material on the p-type semiconductor layer 105. Just grow.

  As described above, a normally-off type field effect transistor capable of high withstand voltage and large current operation can be realized.

(Third Modification of First Embodiment)
Hereinafter, a third modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 6 is a semiconductor device according to a third modification of the first embodiment of the present invention, and schematically shows a cross-sectional configuration of a heterojunction field effect transistor. In FIG. 6, the same components as those shown in FIG. 1 and FIG.

In the third modified example, as in the first modified example, the electron supply layer 104A made of Al _0.15 Ga _0.85 N has a thickness of 50 nm, and further, in the formation region of the p-type semiconductor layer 105 For example, a recess 104a having a depth of 30 nm is provided.

The p-type semiconductor layer 105 made of p-type ZnO having a thickness of 20 nm is formed so that the lower portion thereof is filled in the recess 104a provided in the electron supply layer 104A. Further, similarly to the second modification, a p-type Zn _1-x Mg _x O (where x is 0 <x <1) layer 110 having a thickness of 180 nm on the p-type semiconductor layer 105. Is provided.

  In this way, since ZnMgO has a larger band gap energy than ZnO, the amount of increase (increase) in potential energy at the lower portion of the gate electrode 106 can be increased, and the gate threshold voltage is shifted to the positive voltage side. The normally-off state can be realized more reliably.

A p-type semiconductor layer 105 made of p-type ZnO is provided on the electron supply layer 104 side made of AlGaN, and a Zn _1-x Mg _x O layer 110 is provided on the gate electrode 106 side. As a result, the value of the Mg composition x in the Zn _1-x Mg _x O layer 110 increases from the electron supply layer 104 side to the gate electrode 106 side. Since ZnMgO has a larger lattice constant than ZnO, a laminated structure made of ZnO / ZnMgO can be formed without generating cracks. Therefore, the gate threshold voltage can be controlled by the composition design of the Zn _1-x Mg _x O layer 110.

  Further, by digging a region below the gate electrode 106 in the electron supply layer 104 to form the recess 104a, the gate threshold voltage can be shifted to the positive voltage side without reducing the carrier concentration in the channel layer 103. it can.

  As described above, a normally-off type field effect transistor capable of high withstand voltage and large current operation can be realized.

  In the first embodiment and the modification thereof, the p-type ZnO layer is used for the p-type semiconductor layer 105. However, the present invention is not limited to this, and the crystal structure is hexagonal and other p-type II-VI. For example, zinc sulfide (ZnS), cadmium sulfide (CdS), cadmium selenide (CdSe), or the like can be used.

  In the first embodiment and the modifications thereof, the p-type ZnO layer is used as the p-type semiconductor layer 105. However, the present invention is not limited to this, and a hexagonal p-type II-VI group compound semiconductor other than ZnO is used. Also good. In the case of hexagonal crystal, the crystal structure is the same as that of the second semiconductor layer made of a nitride semiconductor, so that lattice matching is easy even when it is formed directly on the second semiconductor layer. For example, zinc sulfide (ZnS), cadmium sulfide (CdS), cadmium selenide (CdSe), or the like can be used.

In the first embodiment and its modifications, the p-type semiconductor layer 105 may be made of another p-type compound semiconductor containing oxygen or sulfur as a constituent element, and the p-type layer is selectively etched similarly to ZnO. Can be easily realized. Furthermore, it is more desirable to use a compound semiconductor having a delafossite structure or a chalcogenide structure containing a transition metal as a constituent element. For example, by using CuAlO ₂ , SrCu ₂ O ₂ , LaCuOS, LaCuOSe, or the like, good bonding with the second nitride semiconductor layer can be realized, and p-type conversion can also be realized relatively easily.

  The semiconductor device and the manufacturing method thereof according to the present invention can realize a junction field effect transistor having a normally-off characteristic that suppresses variations in electrical characteristics and has a high manufacturing yield, and a semiconductor device made of a nitride semiconductor and its manufacturing Useful for methods and the like.

1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention. (A)-(e) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a composition sectional view showing a semiconductor device concerning the 1st modification of a 1st embodiment of the present invention. (A)-(f) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on the 1st modification of the 1st Embodiment of this invention. It is a structure sectional view showing a semiconductor device concerning the 2nd modification of a 1st embodiment of the present invention. It is a structure sectional view showing a semiconductor device concerning the 3rd modification of a 1st embodiment of the present invention. It is a structure sectional view showing a junction field effect transistor concerning a conventional example.

101 Substrate 102 Buffer layer 103 Channel layer 104 Electron supply layer 104a Recess 105 P-type semiconductor layer 106 Gate electrode 107 Source electrode 108 Drain electrode 109 Element isolation region 110 Zn _1-x Mg _x O layer

Claims (16)

A first semiconductor layer made of a nitride semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a nitride semiconductor having a band gap energy larger than that of the first semiconductor layer;
A p-type third semiconductor layer selectively formed on the second semiconductor layer and made of a hexagonal II-VI group compound semiconductor;
A gate electrode formed on the third semiconductor layer;
A semiconductor device comprising a source electrode and a drain electrode formed in regions on both sides of the gate electrode. 2. The semiconductor device according to claim 1, wherein the third semiconductor layer is made of Zn _1-x Mg _x O (where x is 0 ≦ x <1). The second semiconductor layer has a recess;
The semiconductor device according to claim 1, wherein the third semiconductor layer is formed so as to cover a bottom surface of the recess.   The semiconductor device according to claim 1, wherein the third semiconductor layer has a stacked structure including at least two layers. The value of the Mg composition x in the third semiconductor layer is substantially constant;
5. The semiconductor device according to claim 2, wherein the second semiconductor layer and the third semiconductor layer are lattice-matched.   The value of the Mg composition x in the third semiconductor layer is formed so as to increase from the second semiconductor layer side toward the gate electrode side. 2. The semiconductor device according to claim 1. A first semiconductor layer made of a nitride semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a nitride semiconductor having a band gap energy larger than that of the first semiconductor layer;
A p-type third semiconductor layer which is selectively formed on the second semiconductor layer, is made of a compound semiconductor having a delafossite structure or a chalcogenide structure containing oxygen or sulfur as a constituent element;
A gate electrode formed on the third semiconductor layer;
A semiconductor device comprising a source electrode and a drain electrode formed in regions on both sides of the gate electrode.   The semiconductor device according to claim 7, wherein the third semiconductor layer includes a transition metal element as a constituent element.   The semiconductor device according to claim 8, wherein the transition metal is Cu. The semiconductor device according to claim 9, wherein the third semiconductor layer is any one of CuAlO ₂ , SrCu ₂ O ₂ , LaCuOS, and LaCuOSe. A step (a) of forming a first semiconductor layer made of a nitride semiconductor on a substrate;
Forming a second semiconductor layer made of a nitride semiconductor having a band gap energy larger than that of the first semiconductor layer on the first semiconductor layer;
A step (c) of forming a p-type third semiconductor layer comprising a hexagonal II-VI group compound on the second semiconductor layer;
A step (d) of selectively removing a region excluding the gate electrode formation region in the third semiconductor layer after the step (c);
And a step (e) of selectively forming a gate electrode on the third semiconductor layer. A step (a) of forming a first semiconductor layer made of a nitride semiconductor on a substrate;
Forming a second semiconductor layer made of a nitride semiconductor having a band gap energy larger than that of the first semiconductor layer on the first semiconductor layer;
A step (c) of forming a p-type third semiconductor layer comprising a compound semiconductor having a delafossite structure or a chalcogenide structure containing oxygen or sulfur as a constituent element on the second semiconductor layer;
A step (d) of selectively removing a region excluding the gate electrode formation region in the third semiconductor layer after the step (c);
And a step (e) of selectively forming a gate electrode on the third semiconductor layer.   13. The method of manufacturing a semiconductor device according to claim 11, wherein in the step (d), the third semiconductor layer is removed by wet etching.   13. The method of manufacturing a semiconductor device according to claim 11, wherein in the step (c), the third semiconductor layer is formed by a physical vapor deposition method. After the step (d),
The step (f) of forming a source electrode and a drain electrode in regions on both sides of the third semiconductor layer in the second semiconductor layer, respectively, is further provided. Semiconductor device manufacturing method.   16. The method of manufacturing a semiconductor device according to claim 15, wherein in the step (f), the source electrode and the drain electrode are formed so as to be in contact with the first semiconductor layer.

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