JP7484785B2 - NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - Patent application - Google Patents

Description

This disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Nitride semiconductors have characteristics such as a high saturation electron velocity and a wide band gap. For this reason, various studies are being conducted on utilizing these characteristics to apply nitride semiconductors to high-voltage and high-output semiconductor devices. For example, the band gap of GaN, a type of nitride semiconductor, is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV). For this reason, GaN has a high breakdown field strength and is extremely promising as a material for semiconductor devices for power supplies that operate at high voltages and obtain high output.

As semiconductor devices using nitride semiconductors, there have been many reports on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in the case of GaN-based HEMTs, AlGaN/GaN-HEMTs that use GaN as the channel layer and AlGaN as the barrier layer have attracted attention.

Technology has been proposed to suppress current collapse in GaN-based HEMTs.

JP 2012-248570 A JP 2017-85057 A

However, in recent years, operating frequencies and operating voltages have become higher, making it difficult to sufficiently suppress current collapse even with conventional technology.

The objective of the present disclosure is to provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device that can suppress current collapse.

According to one embodiment of the present disclosure, there is provided a nitride semiconductor device having an electron transit layer, an electron supply layer provided on the electron transit layer and having a first band gap, a first barrier layer provided on the electron supply layer and having a second band gap, a quantum well layer provided on the first barrier layer and having a third band gap, a second barrier layer provided on the quantum well layer and having a fourth band gap, and an insulating layer provided on the second barrier layer, wherein the second band gap is larger than the first band gap, the fourth band gap is equal to or larger than the second band gap, the third band gap is smaller than the second band gap and the fourth band gap, and the first barrier layer is thinner than the second barrier layer.

This disclosure makes it possible to suppress current collapse.

1 is a cross-sectional view showing a structure of a nitride semiconductor device according to a first embodiment. FIG. 2 is a diagram showing a band structure of the nitride semiconductor device according to the first embodiment. 4 is a cross-sectional view showing the function and effect of the nitride semiconductor device according to the first embodiment. FIG. 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a nitride semiconductor device according to a first embodiment. 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment. 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment. FIG. 11 is a diagram showing the results of a simulation for the first example. FIG. 13 is a diagram showing the results of a simulation for the second example. FIG. 13 is a diagram showing a discrete package according to a second embodiment. FIG. 13 is a wiring diagram showing a PFC circuit according to a third embodiment. FIG. 13 is a wiring diagram showing a power supply device according to a fourth embodiment. FIG. 13 is a wiring diagram showing an amplifier according to a fifth embodiment.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description.

First Embodiment
First, a first embodiment will be described. The first embodiment relates to a nitride semiconductor device including a GaN-based HEMT. Fig. 1 is a cross-sectional view showing the structure of the nitride semiconductor device according to the first embodiment. Fig. 2 is a diagram showing the band structure of the nitride semiconductor device according to the first embodiment.

As shown in FIG. 1, the nitride semiconductor device 100 according to the first embodiment has a substrate 110 and a semiconductor stack 120 of nitride semiconductors provided on the substrate 110. The semiconductor stack 120 has, for example, an initial layer 121, a buffer layer 122, an electron transit layer 123, an electron supply layer 124, and a cap layer 125.

The substrate 110 is, for example, a Si substrate whose upper surface is a (111) surface. The initial layer 121 is provided on the substrate 110. The initial layer 121 is, for example, an AlN layer having a thickness of 100 nm to 200 nm. The buffer layer 122 is provided on the initial layer 121. The buffer layer 122 is, for example, an Al _x4 Ga _1-x4 N layer having a thickness of 400 nm to 600 nm. The Al composition x4 of the buffer layer 122 is, for example, 0.2 at the lower surface of the buffer layer 122 and 0.8 at the upper surface, and increases stepwise from the lower surface to the upper surface. The electron transit layer 123 is provided on the buffer layer 122. The electron transit layer 123 is, for example, a GaN layer (i-GaN layer) having a thickness of 100 nm to 1000 nm and not intentionally doped with impurities. The electron supply layer 124 is provided on the electron transit layer 123. The electron supply layer 124 is, for example, an n-type Al _x5 Ga _1-x5 N layer (n-AlGaN layer) having a thickness of 20 nm to 100 nm. The Al composition x5 of the electron supply layer 124 is, for example, 0.2 to 0.3. The electron supply layer 124 is doped with, for example, Si at a concentration of about 5×10 ¹⁸ cm ⁻³ . The electron supply layer 124 has a first band gap.

The cap layer 125 is provided on the electron supply layer 124. The cap layer 125 has a first barrier layer 126, a quantum well layer 127, and a second barrier layer 128.

The first barrier layer 126 is provided on the electron supply layer 124. The first barrier layer 126 is composed of, for example, In _y1 Al _x1 Ga _1-x1-y1 N (0.20≦x1≦1.00, 0.00≦y1≦0.15). The first barrier layer 126 has a second band gap, and the second band gap of the first barrier layer 126 is larger than the first band gap of the electron supply layer 124. The thickness of the first barrier layer 126 is, for example, about 1 nm to 5 nm. The first barrier layer 126 may be doped with an n-type impurity such as Si.

The quantum well layer 127 is provided on the first barrier layer 126. The quantum well layer 127 is made of, for example, In _y3 Al _x3 Ga _1-x3-y3 N (0.00≦x3≦0.30, 0.00≦y3≦0.80). The quantum well layer 127 has a third band gap, which is smaller than the second band gap of the first barrier layer 126. The quantum well layer 127 has a thickness of, for example, about 1 nm to 10 nm. The quantum well layer 127 may be doped with an n-type impurity such as Si.

The second barrier layer 128 is provided on the quantum well layer 127. The second barrier layer 128 is made of, for example, In _y2 Al _x2 Ga _1-x2-y2 N (0.40≦x2≦1.00, 0.00≦y2≦0.15, x1≦x2). The second barrier layer 128 has a fourth band gap, and the fourth band gap of the second barrier layer 128 is equal to or larger than the second band gap of the first barrier layer 126. Preferably, the fourth band gap is larger than the second band gap. The first barrier layer 126 is thinner than the second barrier layer 128. The thickness of the second barrier layer 128 is, for example, about 1 nm to 10 nm. The second barrier layer 128 may be doped with an n-type impurity such as Si.

An element isolation region that defines an element region is formed in the semiconductor laminated structure 120, and a source recess 160s and a drain recess 160d are formed in the cap layer 125 and the electron supply layer 124 in the element region. The recesses 160s and 160d are formed from the upper surface of the cap layer 125 to the middle of the thickness direction of the electron supply layer 124. A source electrode 1s is formed in the recess 160s, and a drain electrode 1d is formed in the recess 160d. An insulating layer 170 that covers the source electrode 1s and the drain electrode 1d is formed on the cap layer 125. A gate electrode 1g is formed on the insulating layer 170 between the source electrode 1s and the drain electrode 1d.

The source electrode 1s and the drain electrode 1d include, for example, a Ti film having a thickness of 50 nm to 150 nm and an Al film having a thickness of 100 nm to 500 nm thereon. The gate electrode 1g includes, for example, a Ni film having a thickness of 10 nm to 50 nm and an Au film having a thickness of 300 nm to 500 nm thereon. The insulating layer 170 is, for example, a film of an oxide, nitride or oxynitride of Si, Al, Hf, Zr, Ti, Ta or W, and is preferably a film of Si nitride (SiN). The thickness of the insulating layer 170 is, for example, 2 nm to 500 nm, and is preferably about 100 nm.

Here, the effects of the nitride semiconductor device 100 will be described. Figure 3 is a cross-sectional view showing the effects of the nitride semiconductor device according to the first embodiment.

In the nitride semiconductor device 100, a two-dimensional electron gas (2DEG) 131 is generated near the interface between the electron transit layer 123 and the electron supply layer 124. In the on-state, electrons 132 move from the source electrode 1s toward the drain electrode 1d through the 2DEG 131. When the potential difference between the source electrode 1s and the drain electrode 1d increases, electrons 132 having a large enough energy to move toward the insulating layer 170 are generated in the 2DEG 131 between the gate electrode 1g and the drain electrode 1d.

When the electron 132 moves toward the insulating layer 170 and is captured by the interface state 133 that exists at the interface between the cap layer 125 and the insulating layer 170, the state in which the electron 132 is captured is maintained, causing a current collapse.

In contrast, in this embodiment, even if the electron 132 moves toward the insulating layer 170, the electron 132 enters the quantum well layer 127 before reaching the interface between the cap layer 125 and the insulating layer 170. Since the quantum well layer 127 functions as a quantum channel, the electron 132 that has entered the quantum well layer 127 can move as a free electron. Therefore, the electron 132 that has entered the quantum well layer 127 moves toward the drain electrode 1d within the quantum well layer 127 due to the potential difference between the source electrode 1s and the drain electrode 1d.

Also, the electron 132 that has entered the quantum well layer 127 may exit the quantum well layer 127. In this embodiment, the fourth band gap of the second barrier layer 128 is equal to or greater than the second band gap of the first barrier layer 126, and the first barrier layer 126 is thinner than the second barrier layer 128. Therefore, even if the electron 132 that has entered the quantum well layer 127 exits the quantum well layer 127, the electron 132 is highly likely to return to the 2DEG 131 side rather than moving to the interface state 133 side. The electron 132 that has returned to the 2DEG 131 side moves toward the drain electrode 1d due to the potential difference between the source electrode 1s and the drain electrode 1d.

In this way, according to this embodiment, even if the interface state 133 exists, it is possible to suppress the capture of the electrons 132 by the interface state 133 and suppress current collapse.

When trying to reduce the interface state 133 in order to suppress current collapse, the degree of freedom in selecting the material for the insulating layer 170 is narrowed, but in this embodiment, current collapse can be suppressed even if the interface state 133 exists. This allows for a wider degree of freedom in selecting the material for the insulating layer 170. Therefore, current collapse can be suppressed while using a material for the insulating layer 170 that provides excellent voltage resistance. In other words, it is possible to achieve both improved voltage resistance and suppression of current collapse.

Next, a method for manufacturing the nitride semiconductor device 100 according to the first embodiment will be described. Figures 4 to 6 are cross-sectional views showing the method for manufacturing the nitride semiconductor device 100 according to the first embodiment.

First, as shown in FIG. 4, a semiconductor laminated structure 120 including an initial layer 121, a buffer layer 122, an electron transit layer 123, an electron supply layer 124, a first barrier layer 126, a quantum well layer 127, and a second barrier layer 128 is formed on a Si substrate 110. The first barrier layer 126, the quantum well layer 127, and the second barrier layer 128 are included in a cap layer 125. The semiconductor laminated structure 120 can be formed by a crystal growth method such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

When forming the semiconductor laminated structure 120 by MOCVD, for example, a mixed gas of trimethylindium (TMI) gas as an In source, trimethylaluminum (TMA) gas as an Al source, trimethylgallium (TMG) gas as a Ga source, and ammonia (NH ₃ ) gas as an N source is used. At this time, the presence or absence of supply of TMI gas, TMA gas, and TMG gas and their flow rates are appropriately set according to the composition of the nitride semiconductor layer to be grown. The flow rate of NH ₃ gas, which is a raw material common to each nitride semiconductor layer, is, for example, about 100 ccm to 10 LM.

When forming an AlN layer as the initial layer 121, for example, the V/III ratio (the ratio of the flow rate of TMA gas to the flow rate of NH ₃ gas) in the source gas is set to about 1000 to 2000, the growth temperature is set to about 1000° C., and the pressure is set to about 50 Torr.

When forming an Al _x4 Ga _1-x4 N layer in which the Al composition x4 changes as the buffer layer 122, for example, the V/III ratio in the source gas (the ratio of the total flow rate of TMA gas and TMG gas to the flow rate of NH ₃ gas) is set to about 500 to 1000, the growth temperature is set to about 1000°C, and the pressure is set to about 50 Torr. In addition, the Al composition x4 is gradually reduced by adjusting the flow rate ratio of TMA gas and TMG gas while growing the AlGaN layer. The smaller the flow rate ratio of TMA gas to TMG gas, the lower the Al composition x4.

When forming a GaN layer as the electron transit layer 123, for example, the V/III ratio (the ratio of the flow rate of TMG gas to the flow rate of NH ₃ gas) in the source gas is set to about 500 to 3000, the growth temperature is set to about 1000° C., and the pressure is set to about 200 Torr.

When forming an AlGaN layer as the electron supply layer 124, for example, the V/III ratio in the source gas (the ratio of the total flow rate of TMA gas and TMG gas to _NH3 gas) is set to about 1000 to 3000, the growth temperature is set to about 730° C., and the pressure is set to about 50 Torr.

When forming an AlGaN layer as the first barrier layer 126, for example, the V/III ratio in the source gas (the ratio of the total flow rate of TMA gas and TMG gas to _NH3 gas) is set to about 500 to 5000, the growth temperature is set to about 1000° C., and the pressure is set to about 100 Torr.

When forming a GaN layer as the quantum well layer 127, for example, the V/III ratio (ratio of TMG gas to NH ₃ gas) in the source gas is about 500 to 5000, the growth temperature is about 1000° C., and the pressure is about 100 Torr.

When forming an AlGaN layer as the second barrier layer 128, for example, the V/III ratio in the source gas (the ratio of the total flow rate of TMA gas and TMG gas to _NH3 gas) is set to about 500 to 5000, the growth temperature is set to about 1000° C., and the pressure is set to about 100 Torr.

Next, as shown in FIG. 5, the cap layer 125 and the surface portion of the electron supply layer 124 are removed in the region below the source electrode 1s and the region below the drain electrode 1d. This removal can be performed, for example, by dry etching using a resist mask. As a result, a source recess 160s and a drain recess 160d that expose the electron supply layer 124 are formed in the semiconductor stack 120.

Then, a source electrode 1s is formed in the recess 160s, and a drain electrode 1d is formed in the recess 160d. The source electrode 1s and the drain electrode 1d can be formed by, for example, a lift-off method. That is, the region where the source electrode 1s is to be formed and the region where the drain electrode 1d is to be formed are exposed, and a photoresist pattern covering the other regions is formed, and a metal film is formed by deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In forming the metal film, for example, a Ti film with a thickness of 50 nm to 150 nm is formed, and an Al film with a thickness of 100 nm to 500 nm is formed thereon. Next, for example, a heat treatment (for example, rapid thermal annealing (RTA)) is performed at 400° C. to 1000° C. (for example, 600° C.) in an N ₂ atmosphere to obtain an ohmic contact.

Next, as shown in FIG. 6, an insulating layer 170 is formed on the cap layer 125 to cover the source electrode 1s and the drain electrode 1d. The insulating layer 170 can be formed by, for example, a plasma CVD method. The insulating layer 170 may be formed by an atomic layer deposition (ALD) method or a sputtering method. Next, a gate electrode 1g is formed on the insulating layer 170 between the source electrode 1s and the drain electrode 1d. The gate electrode 1g can be formed by, for example, a lift-off method. That is, a photoresist pattern is formed to expose the area where the gate electrode 1g is to be formed, and a metal film is formed by deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In forming the metal film, for example, a Ni film having a thickness of 10 nm to 50 nm is formed, and an Au film having a thickness of 300 nm to 500 nm is formed on the Ni film.

In this manner, the nitride semiconductor device 100 according to the first embodiment can be manufactured.

The first barrier layer 126 preferably contains a higher concentration of n-type impurities than the second barrier layer 128. When the first barrier layer 126 contains a higher concentration of n-type impurities than the second barrier layer 128, the change in the conduction band in the thickness direction of the first barrier layer 126 becomes steeper, and the electrons 132 that have entered the quantum well layer 127 are more likely to return to the 2DEG 131.

In addition, when the electron transit layer 123 is made of GaN, it is preferable that the quantum well layer 127 is made of GaN or a nitride semiconductor having a larger lattice constant than GaN. The lattice constants of the first barrier layer 126 and the second barrier layer 128 containing Al are smaller than the lattice constant of the electron transit layer 123 made of GaN. Therefore, if the quantum well layer 127 is made of GaN or a nitride semiconductor having a larger lattice constant than GaN, it is easier to reduce the difference in lattice constant between the cap layer 125 and the electron transit layer 123.

Here, we will explain the simulation performed by the inventor of this application. In this simulation, the relationship between drain voltage and drain current was calculated for the following two example transistors.

The first example is an example following the embodiment. In the first condition, the electron supply layer 124 is an _Al0.3Ga0.7N layer having a thickness of ₁₅ nm, the first barrier layer 126 is an _Al0.4Ga0.6N layer having a thickness of ₃ nm, the quantum well layer 127 is a GaN layer having a thickness of 5 nm, and the second barrier layer 128 is an _Al0.6Ga0.4N layer having a thickness of ₅ nm. In the second example, the electron supply layer 124 is an _Al0.3Ga0.7N layer having a thickness of ₁₅ nm, and a GaN layer having a thickness of 3 nm is used instead of the cap layer 125.

Then, for the first and second examples, the relationship between the drain voltage and the drain current when the gate voltage Vg was 0V and -2V was calculated under the first condition simulating a pulse measurement and the second condition simulating a direct current (DC) measurement. Under the first condition, a pulsed stress voltage was applied to calculate the relationship between the drain voltage and the drain current. Specifically, under the first condition, a drain voltage of 50V and a gate voltage of -5V were applied to the transistor as the voltage in the stress state, and the drain current was calculated when the drain voltage was changed from that stress state. Under the second condition, a DC voltage was applied, and the drain current was calculated when the drain voltage was changed without applying a stress voltage to the transistor. The results are shown in Figures 7 and 8. Figure 7 shows the results of the simulation for the first example, and Figure 8 shows the results of the simulation for the second example.

In pulse measurements, the drain current before recovery from the stress state is recorded. Therefore, when the same drain voltage is applied, the difference between the drain current under the second condition (DC measurement) and the drain current under the first condition (pulse measurement) corresponds to the current decrease due to current collapse. As shown in Figures 7 and 8, in the second example, the drain current under the first condition is significantly smaller than the drain current under the second condition, whereas the difference in drain current in the first example is slight. This shows that, according to the first example, the effective amount of drain current increases when the transistor is operated at high frequency, resulting in a high RF output.

Second Embodiment
Next, a second embodiment will be described. The second embodiment relates to a discrete package of a HEMT. Fig. 9 is a diagram showing the discrete package according to the second embodiment.

In the second embodiment, as shown in FIG. 9, the back surface of a semiconductor device 1210 having a structure similar to that of the first embodiment is fixed to a land (die pad) 1233 using a die attachment agent 1234 such as solder. A wire 1235d such as an Al wire is connected to a drain pad 1226d to which a drain electrode 1d is connected, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to a source pad 1226s connected to a source electrode 1s, and the other end of the wire 1235s is connected to a source lead 1232s independent from the land 1233. A wire 1235g such as an Al wire is connected to a gate pad 1226g connected to a gate electrode 1g, and the other end of the wire 1235g is connected to a gate lead 1232g independent from the land 1233. The land 1233 and the semiconductor device 1210 are packaged in the mold resin 1231 so that a portion of the gate lead 1232g, a portion of the drain lead 1232d, and a portion of the source lead 1232s protrude.

Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attachment agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. After that, sealing is performed using mold resin 1231 by the transfer molding method. Next, the lead frame is separated.

Third Embodiment
Next, a third embodiment will be described. The third embodiment relates to a PFC (Power Factor Correction) circuit including a HEMT. Fig. 10 is a wiring diagram showing the PFC circuit according to the third embodiment.

The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an alternating current (AC) power supply 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. The AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. A direct current (DC) power supply is connected between both terminals of the capacitor 1255. In this embodiment, a semiconductor device having a structure similar to that of the first embodiment is used for the switch element 1251.

When manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252 and the choke coil 1253, etc., using, for example, solder.

Fourth Embodiment
Next, a fourth embodiment will be described. The fourth embodiment relates to a power supply device including a HEMT, suitable for use as a server power supply. Fig. 11 is a wiring diagram showing the power supply device according to the fourth embodiment.

The power supply device is provided with a high-voltage primary circuit 1261, a low-voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

The primary side circuit 1261 includes a PFC circuit 1250 according to the third embodiment, and an inverter circuit, for example a full-bridge inverter circuit 1260, connected between both terminals of a capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 includes multiple (four in this example) switch elements 1264a, 1264b, 1264c, and 1264d.

The secondary circuit 1262 is provided with multiple (here, three) switch elements 1265a, 1265b, and 1265c.

In this embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260 are made of semiconductor devices having the same structure as in the first embodiment. On the other hand, the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262 are made of ordinary MIS type FETs (field effect transistors) using silicon.

Fifth Embodiment
Next, a fifth embodiment will be described. The fifth embodiment relates to an amplifier including a HEMT. Fig. 12 is a wiring diagram showing the amplifier according to the fifth embodiment.

The amplifier includes a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of the first embodiment, and amplifies the input signal mixed with the AC signal. Note that in this embodiment, for example, by switching a switch, the output signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-output amplifier. The high-frequency amplifier can be used, for example, in a transmitting/receiving device for a mobile phone base station, a radar device, and a microwave generating device.

In the present disclosure, the substrate may be a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate. The substrate may be conductive, semi-insulating, or insulating. When an electron transport layer can be formed on the substrate,
A substrate may be used as the underlayer.

The structures of the gate electrode, source electrode, and drain electrode are not limited to those in the above-described embodiment. For example, they may be composed of a single layer. Furthermore, the method of forming them is not limited to the lift-off method. Furthermore, if ohmic characteristics are obtained, the heat treatment after the formation of the source electrode and drain electrode may be omitted. Heat treatment may be performed after the formation of the gate electrode.

In the above embodiment, a MIS (metal-insulator-semiconductor) gate structure is used as the gate electrode structure, but a Schottky gate structure may also be used.

Although the preferred embodiments have been described above in detail, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

Various aspects of this disclosure are summarized below as appendices.

(Appendix 1)
An electron transport layer;
an electron supply layer provided on the electron transit layer and having a first band gap;
a first barrier layer disposed on the electron supply layer and having a second band gap;
a quantum well layer disposed on the first barrier layer and having a third bandgap;
a second barrier layer disposed on the quantum well layer and having a fourth bandgap;
an insulating layer provided on the second barrier layer;
having
the second bandgap is larger than the first bandgap;
the fourth band gap is equal to or greater than the second band gap;
the third band gap is smaller than the second band gap and the fourth band gap;
The nitride semiconductor device according to claim 1, wherein the first barrier layer is thinner than the second barrier layer.
(Appendix 2)
2. The nitride semiconductor device according to claim 1, wherein the second barrier layer is made of a nitride semiconductor.
(Appendix 3)
3. The nitride semiconductor device according to claim 1, wherein the fourth band gap is larger than the second band gap.
(Appendix 4)
4. The nitride semiconductor device according to claim 1, wherein the first barrier layer contains an n-type impurity at a higher concentration than the second barrier layer.
(Appendix 5)
the electron transport layer is made of GaN;
5. The nitride semiconductor device according to claim 1, wherein the quantum well layer is made of GaN or a nitride semiconductor having a lattice constant larger than that of GaN.
(Appendix 6)
the first barrier layer is composed of In _y1 Al _x1 Ga _1-x1-y1 N (0.20≦x1≦1.00, 0.00≦y1≦0.15);
6. The nitride semiconductor device according to claim 1, wherein the second barrier layer is made of In _y2 Al _x2 Ga _1-x2-y2 N (0.40≦x2≦1.00, 0.00≦y2≦0.15, x1≦x2).
(Appendix 7)
forming an electron supply layer having a first band gap on the electron transit layer;
forming a first barrier layer having a second band gap on the electron supply layer;
forming a quantum well layer having a third bandgap on the first barrier layer;
forming a second barrier layer over the quantum well layer, the second barrier layer having a fourth bandgap;
forming an insulating layer over the second barrier layer;
having
the second bandgap is larger than the first bandgap;
the fourth band gap is equal to or greater than the second band gap;
the third band gap is smaller than the second band gap and the fourth band gap;
2. A method for manufacturing a nitride semiconductor device, wherein the first barrier layer is thinner than the second barrier layer.
(Appendix 8)
7. An amplifier comprising the semiconductor device according to claim 1.
(Appendix 9)
A power supply device comprising the semiconductor device according to any one of claims 1 to 6.

100: nitride semiconductor device 110: substrate 123: electron transit layer 124: electron supply layer 125: cap layer 126: first barrier layer 127: quantum well layer 128: second barrier layer 131: 2DEG
132: Electron 133: Interface state 170: Insulating layer

Claims (6)

An electron transport layer;
an electron supply layer provided on the electron transit layer and having a first band gap;
a first barrier layer disposed on the electron supply layer and having a second band gap;
a quantum well layer disposed on the first barrier layer and having a third bandgap;
a second barrier layer disposed on the quantum well layer and having a fourth bandgap;
an insulating layer provided on the second barrier layer;
having
the second bandgap is larger than the first bandgap;
the fourth band gap is equal to or greater than the second band gap;
the third band gap is smaller than the second band gap and the fourth band gap;
The nitride semiconductor device according to claim 1, wherein the first barrier layer is thinner than the second barrier layer. The nitride semiconductor device according to claim 1, characterized in that the second barrier layer is made of a nitride semiconductor. The nitride semiconductor device according to claim 1 or 2, characterized in that the fourth band gap is larger than the second band gap. The nitride semiconductor device according to any one of claims 1 to 3, characterized in that the first barrier layer contains a higher concentration of n-type impurities than the second barrier layer. the electron transport layer is made of GaN;
5. The nitride semiconductor device according to claim 1, wherein the quantum well layer is made of GaN or a nitride semiconductor having a lattice constant larger than that of GaN. forming an electron supply layer having a first band gap on the electron transit layer;
forming a first barrier layer having a second band gap on the electron supply layer;
forming a quantum well layer having a third bandgap on the first barrier layer;
forming a second barrier layer over the quantum well layer, the second barrier layer having a fourth bandgap;
forming an insulating layer over the second barrier layer;
having
the second bandgap is larger than the first bandgap;
the fourth band gap is equal to or greater than the second band gap;
the third band gap is smaller than the second band gap and the fourth band gap;
2. A method for manufacturing a nitride semiconductor device, wherein the first barrier layer is thinner than the second barrier layer.

Images