JP2001102577A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001102577A JP2001102577A JP27825599A JP27825599A JP2001102577A JP 2001102577 A JP2001102577 A JP 2001102577A JP 27825599 A JP27825599 A JP 27825599A JP 27825599 A JP27825599 A JP 27825599A JP 2001102577 A JP2001102577 A JP 2001102577A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- region
- type
- semiconductor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 124
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 230000010354 integration Effects 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 abstract description 18
- 239000000969 carrier Substances 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000011084 recovery Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置、特に
電力用のスーパージャンクション素子に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a power super junction device.
【０００２】[0002]
【従来の技術】図７は、従来の縦型スーパージャンクシ
ョンＭＯＳＦＥＴの素子構造を示した断面図である。2. Description of the Related Art FIG. 7 is a sectional view showing a device structure of a conventional vertical super junction MOSFET.
【０００３】この素子の基本構造は、ｎ+ 型半導体基板
に形成されたｎ+ 型ドレイン層１、その上にエピタキシ
ャル成長されたｎ- 型ベース層（図示せず）、ｐ型ベー
ス層３、ｎ+ 型ソース層４、ｐ+ 型層５、ドレイン電極
６、ソース電極７、ゲート電極８、ゲート絶縁膜９、ｎ
- 型ベース層内でｎ型低濃度層１０及びｐ型低濃度層１
１が交互に繰り返し配置された補助領域によって構成さ
れている。The basic structure of this device is as follows: an n + -type drain layer 1 formed on an n + -type semiconductor substrate; an n − -type base layer (not shown) epitaxially grown thereon; + Type source layer 4, p + type layer 5, drain electrode 6, source electrode 7, gate electrode 8, gate insulating film 9, n
- n-type by type base layer low-concentration layer 10 and the p-type low concentration layer 1
1 are constituted by auxiliary areas alternately and repeatedly arranged.
【０００４】なお、図では、ｎ型低濃度層１０の左半分
及びｐ型低濃度層１１の右半分に対応した領域からなる
単位領域のみ示しているが、実際には隣接する単位領域
どおしが単位領域間の境界面で面対称になるようにして
複数配置されている。FIG. 1 shows only a unit region consisting of a region corresponding to the left half of the n-type low-concentration layer 10 and the right half of the p-type low-concentration layer 11; A plurality of ladders are arranged so as to be plane-symmetric at the boundary between the unit areas.
【０００５】ｎ型低濃度層１０とｐ型低濃度層１１とが
交互に繰り返し配置された補助領域の効果については、
例えば「Ｔ．Ｆｕｊｉｈｉｒａ，Ｊｐｎ．Ｊ．Ａｐｐ
ｌ．Ｐｈｙｓ．Ｖｏｌ．３６（１９９７）ｐｐ．６２５
４−６２６２」に開示されている。これによれば、補助
領域のｎ型低濃度層１０とｐ型低濃度層１１の繰り返し
方向のキャリア積分量が、概略５×１０12ｃｍ-2以下で
ほぼ同一になるように設計すれば、これらの低濃度層間
に逆方向電圧が印加された場合に、これらの低濃度層は
完全に空乏化するというものである。The effect of the auxiliary region in which the n-type low-concentration layers 10 and the p-type low-concentration layers 11 are alternately and repeatedly arranged is described below.
For example, see "T. Fujihira, Jpn. J. App.
l. Phys. Vol. 36 (1997) pp. 625
4-6262 ". According to this, if the carrier integration amount in the repetition direction of the n-type low-concentration layer 10 and the p-type low-concentration layer 11 in the auxiliary region is designed to be substantially the same at about 5 × 10 12 cm −2 or less, When a reverse voltage is applied between these low-concentration layers, these low-concentration layers are completely depleted.
【０００６】この原理によれば、例えばｎ型低濃度層１
０の濃度をｎ- 型ベース層の濃度の１００倍に設定して
も、ｎ型低濃度層１０の幅を狭くしてキャリア積分量が
５×１０12ｃｍ-2以下になるように調整すれば、補助領
域ではブレークダウンが起こらないことになる。したが
って、このような補助領域をｎ+ 型ドレイン層１とｐ型
ベース層３とに挟まれた領域に形成すれば、この部分の
抵抗を著しく低減することが可能となる。According to this principle, for example, the n-type low concentration layer 1
Even if the concentration of 0 is set to 100 times the concentration of the n − -type base layer, the width of the n-type low-concentration layer 10 is narrowed and the carrier integration amount is adjusted to be 5 × 10 12 cm −2 or less. Thus, no breakdown occurs in the auxiliary area. Therefore, if such an auxiliary region is formed in a region sandwiched between the n + -type drain layer 1 and the p-type base layer 3, the resistance at this portion can be significantly reduced.
【０００７】また、この補助領域はその厚さ方向の長さ
に比例して耐圧が増加するという性質を持っているの
で、オン抵抗は耐圧に直線的に比例する。一方、補助領
域のない場合には、ｎ- 型ベース層の濃度を減らしなが
ら厚さを増加させないと耐圧が増加しないので、オン抵
抗は耐圧の２乗に比例して著しく増加する。したがっ
て、高耐圧が要求される素子になるほど、補助領域を設
けたことによるオン抵抗の低減効果が大きくなる。Further, since the auxiliary region has a property that the breakdown voltage increases in proportion to the length in the thickness direction, the on-resistance is linearly proportional to the breakdown voltage. On the other hand, when there is no auxiliary region, the breakdown voltage does not increase unless the thickness is increased while decreasing the concentration of the n − -type base layer, so that the on-resistance increases significantly in proportion to the square of the breakdown voltage. Therefore, the effect of reducing the on-resistance due to the provision of the auxiliary region increases as the element requires a higher breakdown voltage.
【０００８】また、補助領域のｐ型低濃度層１１はｐ型
ベース層３と接続されてソース電極７とほぼ等電位に設
定されており、補助領域のｎ型低濃度層１０はｎ+ 型ド
レイン層１と接続されてドレイン電極６とほぼ等電位に
設定されている。したがって、縦型ＭＯＳＦＥＴがター
ンオフし始めると、補助領域内部のキャリアは速やかに
素子外部へ吐き出されて空乏層が広がり、高速にターン
オフすることが可能となる。The p-type low-concentration layer 11 in the auxiliary region is connected to the p-type base layer 3 and is set at substantially the same potential as the source electrode 7, and the n-type low-concentration layer 10 in the auxiliary region is n + -type. It is connected to the drain layer 1 and is set at substantially the same potential as the drain electrode 6. Therefore, when the vertical MOSFET starts to turn off, the carriers in the auxiliary region are quickly discharged to the outside of the element, the depletion layer expands, and it is possible to turn off at high speed.
【０００９】また、このような素子の製造方法は、
「Ｇ．Ｄｅｂｏｙ ｅｔ ａｌ．，ＩＥＤＭ９８（１９
９８）ｐｐ．６８３−６８５」に開示されている。A method for manufacturing such an element is as follows.
"G. Deboy et al., IEDM 98 (19
98) pp. 683-685 ".
【００１０】これによれば、ｎ+ 型半導体基板上に例え
ば厚さ１０μｍのエピタキシャル層を形成して、補助領
域のｎ型低濃度層１０及びｐ型低濃度層１１が形成され
る領域に、イオン注入によって選択的に不純物を導入す
る。さらに、エピタキシャル層を形成して同様の工程を
行ない、これを素子の耐圧・厚さに応じて数回繰り返
す。According to this, an epitaxial layer having a thickness of, for example, 10 μm is formed on the n + type semiconductor substrate, and the region where the n-type low concentration layer 10 and the p-type low concentration layer 11 of the auxiliary region are formed is formed. Impurities are selectively introduced by ion implantation. Further, an epitaxial layer is formed and the same steps are performed, and this is repeated several times according to the breakdown voltage and thickness of the device.
【００１１】次に、ｐ型ベース層３などのイオン注入を
行った後、熱拡散により、それぞれのエピタキシャル層
内部に形成されたイオン注入層から不純物を拡散させ
て、互いの層のｎ型低濃度層１０及びｐ型低濃度層１１
が接続されるようにする。その後、ｎ+ 型ソース層４、
ｐ+ 型層５、ゲート絶縁膜９、ゲート電極８、ソース電
極７、ドレイン電極６などを形成し、素子を完成させ
る。Next, after ion implantation of the p-type base layer 3 and the like is performed, impurities are diffused from the ion-implanted layers formed inside the respective epitaxial layers by thermal diffusion, and the n-type low Concentration layer 10 and p-type low concentration layer 11
To be connected. After that, the n + type source layer 4,
The p + type layer 5, the gate insulating film 9, the gate electrode 8, the source electrode 7, the drain electrode 6, and the like are formed to complete the device.
【００１２】上述したような製造方法を用いることによ
り、比較的簡単に補助領域を形成することができる。By using the manufacturing method as described above, the auxiliary region can be formed relatively easily.
【００１３】しかしながら、上述した従来の素子構造で
は、「Ｐ．Ｍ．Ｓｈｅｎｏｙ ｅｔａｌ．，ＩＳＰＳＤ
９９（１９９９）ｐｐ．９９−１０２」に開示されてい
るように、補助領域のｎ型低濃度層１０とｐ型低濃度層
１１のキャリア積分量がずれると、ターンオフ時間や内
蔵逆導通ダイオードの逆回復時間が大きく変動するとと
もに、耐圧が著しく低下するという問題が生じる。However, in the above-mentioned conventional element structure, “PM Shenoy et al., ISPSD
99 (1999) pp. 99-102, when the carrier integration amount of the n-type low concentration layer 10 and the p-type low concentration layer 11 in the auxiliary region is shifted, the turn-off time and the reverse recovery time of the built-in reverse conduction diode greatly fluctuate. At the same time, there arises a problem that the withstand voltage is significantly reduced.
【００１４】また、エピタキシャル成長は高温で行なう
ので、最初に行なったエピタキシャル成長層中に導入さ
れている不純物がしだいに拡散するため、補助領域下部
のキャリア積分量がずれやすいという問題が生じる。In addition, since the epitaxial growth is performed at a high temperature, the impurity introduced into the epitaxially grown layer which is firstly diffused gradually, so that there is a problem that the carrier integration amount under the auxiliary region tends to shift.
【００１５】また、従来の素子構造では、補助領域のｐ
型低濃度層１１がｎ+ 型ドレイン層１に接しているの
で、この部分の空乏層はｐ型低濃度層１１内部にしか広
がらない。一方、補助領域のｎ型低濃度層１０は比較的
濃度の低いｐ型ベース層３に接しているので、この部分
の空乏層はｎ型低濃度層１０内部だけでなく、ｐ型ベー
ス層３内部にも広がる。その結果、ｐ型低濃度層１１と
ｎ+ 型ドレイン層１が接している部分の電界強度が高く
なり、この部分で素子全体の耐圧が制限されるという問
題が生じる。In the conventional device structure, the p of the auxiliary region
Since the low-concentration type layer 11 is in contact with the n + -type drain layer 1, the depletion layer in this portion extends only inside the p-type low-concentration layer 11. On the other hand, since the n-type low-concentration layer 10 in the auxiliary region is in contact with the p-type base layer 3 having a relatively low concentration, the depletion layer in this portion is not only in the n-type low-concentration layer 10 but also in the p-type base layer 3. Spreads inside. As a result, the electric field strength at the portion where the p-type low-concentration layer 11 and the n + -type drain layer 1 are in contact with each other is increased, and there is a problem that the breakdown voltage of the entire device is limited at this portion.
【００１６】２次元数値計算の結果によれば、補助領域
の長さＬが３５０μｍ、補助領域のｎ型低濃度層１０及
びｐ型低濃度層１１の幅Ｗｎ及びＷｐがともに３．５μ
ｍ、ｎ型低濃度層１０及びｐ型低濃度層１１の濃度Ｃｎ
及びＣｐがともに３×１０15ｃｍ-3の場合に、素子の耐
圧は４９５０Ｖであった。局部的な電界集中のない理想
的な素子の耐圧は、半導体の絶縁破壊電界強度と補助領
域の長さとの積で表される７０００Ｖになるはずなの
で、この素子構造では７０％の耐圧しか得られないこと
になる。According to the result of the two-dimensional numerical calculation, the length L of the auxiliary region is 350 μm, and the widths Wn and Wp of the n-type low concentration layer 10 and the p-type low concentration layer 11 in the auxiliary region are both 3.5 μm.
Concentration Cn of m, n-type low concentration layer 10 and p-type low concentration layer 11
When both Cp and Cp were 3 × 10 15 cm −3 , the breakdown voltage of the device was 4950V. Since the withstand voltage of an ideal device without local electric field concentration should be 7000 V, which is represented by the product of the breakdown field strength of the semiconductor and the length of the auxiliary region, this device structure can provide only a withstand voltage of 70%. Will not be.
【００１７】[0017]
【発明が解決しようとする課題】このように、スーパー
ジャンクション素子は、オン抵抗の低減や高速ターンオ
フといった優れた性能を有している。しかしながら、従
来のスーパージャンクション素子は、補助領域のｎ型低
濃度層とｐ型低濃度層のキャリア積分量がずれると、タ
ーンオフ時間や内蔵逆導通ダイオードの逆回復時間が大
きく変動するとともに、耐圧が著しく低下するという問
題があった。また、ｐ型低濃度層とｎ+ 型ドレイン層が
接している部分の電界強度が高くなり、この部分で素子
全体の耐圧が制限されるという問題もあった。As described above, the super junction element has excellent performance such as reduction of on-resistance and high-speed turn-off. However, in the conventional super junction element, when the carrier integration amount of the n-type low-concentration layer and the p-type low-concentration layer in the auxiliary region deviates, the turn-off time and the reverse recovery time of the built-in reverse conducting diode greatly fluctuate, and the breakdown voltage also increases. There has been a problem that it is significantly reduced. Further, there is also a problem that the electric field strength is increased in a portion where the p-type low concentration layer and the n + -type drain layer are in contact, and the withstand voltage of the entire device is limited in this portion.
【００１８】本発明は上記従来の課題に対してなされた
ものであり、従来の素子に比べて耐圧及びターンオフ特
性を向上させることが可能な半導体装置を提供すること
を目的としている。The present invention has been made to solve the above-mentioned conventional problems, and has as its object to provide a semiconductor device capable of improving the breakdown voltage and the turn-off characteristics as compared with the conventional elements.
【００１９】[0019]
【課題を解決するための手段】本発明に係る半導体装置
は、以下の構成を有している。なお、本発明の理解を容
易にするため、後述する実施形態において説明する図面
の参照番号を付して本発明の構成を示す。A semiconductor device according to the present invention has the following configuration. In order to facilitate understanding of the present invention, the configuration of the present invention is indicated by reference numerals of the drawings described in the embodiments described later.
【００２０】本発明は、第１導電型の不純物が含有され
た第１の半導体領域（１）と、前記第１の半導体領域
（１）と離間して形成され第２導電型の不純物が含有さ
れた第２の半導体領域（３）と、前記第１の半導体領域
（１）と前記第２の半導体領域（３）との間に設けら
れ、第１導電型の不純物が含有された第１の半導体層
（１０）と第２導電型の不純物が含有された第２の半導
体層（１１）とが前記第１の半導体領域（１）と第２の
半導体領域（３）とが対向する方向と交差する方向に交
互に繰り返し配置された第３の半導体領域（１０、１
１）と、を有する半導体装置であって、交互に繰り返し
配置された前記第１の半導体層（１０）及び第２の半導
体層（１１）の繰り返し方向のキャリア積分量が、第２
の半導体層（１１）の方が第１の半導体層（１０）より
も大きくなるように構成され、前記第１の半導体領域
（１）と前記第３の半導体領域（１０、１１）の少なく
とも第２の半導体層（１１）との間に前記第１の半導体
領域（１）よりも第１導電型の不純物濃度の低い第４の
半導体領域（１３）が形成されていることを特徴とす
る。According to the present invention, a first semiconductor region (1) containing a first conductivity type impurity and a second conductivity type impurity formed separately from the first semiconductor region (1) are contained. The second semiconductor region (3), and the first semiconductor region (1) provided between the first semiconductor region (1) and the second semiconductor region (3) and containing a first conductivity type impurity. Direction in which the first semiconductor region (1) and the second semiconductor region (3) face each other with the semiconductor layer (10) and the second semiconductor layer (11) containing impurities of the second conductivity type. Semiconductor regions (10, 1, 1) alternately and repeatedly arranged in a direction intersecting
1) wherein the first semiconductor layer (10) and the second semiconductor layer (11) alternately and repeatedly arranged have a carrier integration amount in the repetition direction of the second semiconductor layer (10) and the second semiconductor layer (11).
The semiconductor layer (11) is configured to be larger than the first semiconductor layer (10), and at least the first semiconductor region (1) and the third semiconductor region (10, 11) A fourth semiconductor region (13) having a first conductivity type lower in impurity concentration than the first semiconductor region (1) is formed between the second semiconductor layer (11) and the second semiconductor layer (11).
【００２１】本発明では、第３の半導体領域（補助領
域）の第２の半導体層の繰り返し方向のキャリア積分量
（Ｑ２）が第１の半導体層の繰り返し方向のキャリア積
分量（Ｑ１）よりも大きくなるようにしている（Ｑ２＞
Ｑ１）ので、ターンオフの際に第１の半導体層が空乏化
した後にも第２の半導体層の中央部には非空乏化領域が
残存している。そのため、電流がこの非空乏化領域を通
って排出されることになり、高速にターンオフすること
が可能となる（特に、ｎ型に比べてｐ型のキャリアの移
動度が小さいことから、第１の半導体層がｎ型で第２の
半導体層がｐ型である場合に、効果が大きい）。製造プ
ロセス等に起因するキャリア積分量の変動が多少あって
としても、Ｑ２とＱ１との大小関係が逆転しない程度に
Ｑ２及びＱ１の値を設定しておけば、ターンオフ時間の
揃った素子を容易に製造することが可能となる。In the present invention, the carrier integration amount (Q2) of the third semiconductor region (auxiliary region) in the repetition direction of the second semiconductor layer is larger than the carrier integration amount (Q1) of the first semiconductor layer in the repetition direction. (Q2>
Because of Q1), even after the first semiconductor layer is depleted at the time of turn-off, a non-depleted region remains in the center of the second semiconductor layer. Therefore, a current is discharged through the non-depleted region, and it is possible to turn off at a high speed (in particular, since the mobility of the p-type carrier is smaller than that of the n-type, the first The effect is great when the semiconductor layer is n-type and the second semiconductor layer is p-type. Even if there is some variation in the amount of carrier integration due to the manufacturing process or the like, if the values of Q2 and Q1 are set so that the magnitude relationship between Q2 and Q1 does not reverse, elements with uniform turn-off times can be easily manufactured. Can be manufactured.
【００２２】また、第２の半導体層の中央部に非空乏化
領域が残存することから、第２の半導体領域の電位が非
空乏化領域を介して第１の半導体領域の近傍まで達する
ことになるが、第１の半導体領域と第３の半導体領域と
の間に第１の半導体領域よりも不純物濃度の低い第４の
半導体領域が形成されているので、空乏層が不純物濃度
の低い第４の半導体領域の内部に広がって電界を緩和
し、高耐圧化をはかることが可能となる。Further, since the non-depleted region remains in the center of the second semiconductor layer, the potential of the second semiconductor region reaches the vicinity of the first semiconductor region via the non-depleted region. However, since the fourth semiconductor region having a lower impurity concentration than the first semiconductor region is formed between the first semiconductor region and the third semiconductor region, the depletion layer has a fourth impurity region having a lower impurity concentration. It is possible to reduce the electric field by expanding into the inside of the semiconductor region, thereby increasing the breakdown voltage.
【００２３】前記発明において、前記第３の半導体領域
（１０、１１）の第２の半導体層（１１）は、前記第１
の半導体領域（１）側の方が前記第２の半導体領域
（３）側よりも不純物濃度が低くなるように構成された
複数の半導体層からなることが好ましい。In the above invention, the second semiconductor layer (11) of the third semiconductor region (10, 11) is formed by the first semiconductor layer (10).
The semiconductor region (1) side preferably includes a plurality of semiconductor layers configured to have a lower impurity concentration than the second semiconductor region (3) side.
【００２４】このような構成により、第３の半導体領域
（補助領域）の第２の半導体層における第１の半導体領
域に近い側の領域が容易に空乏化するため、第２の半導
体領域の電位の影響をより一層抑制することが可能とな
り、高耐圧化をより一層高めることが可能となる。ま
た、第２の半導体領域に近い側の領域では、第２の半導
体層は比較的低抵抗となるので、排出電流が制限されて
ターンオフの高速性が損なわれることはない。With such a structure, the region of the third semiconductor region (auxiliary region) on the side closer to the first semiconductor region in the second semiconductor layer is easily depleted, so that the potential of the second semiconductor region is reduced. Can be further suppressed, and higher withstand voltage can be further enhanced. Further, in the region near the second semiconductor region, the second semiconductor layer has a relatively low resistance, so that the discharge current is limited and the high-speed turn-off is not impaired.
【００２５】また、前記発明において、前記第４の半導
体領域（１３）は、前記第１の半導体領域（１）と前記
第３の半導体領域（１０、１１）との間に形成されたバ
ッファ領域であってもよい。In the above invention, the fourth semiconductor region (13) may include a buffer region formed between the first semiconductor region (1) and the third semiconductor region (10, 11). It may be.
【００２６】このような構成により、第３の半導体領域
（補助領域）の第２の半導体層が比較的高濃度となるこ
とによって内蔵逆導通ダイオードの逆回復電流が大きく
なっても、バッファ領域にキャリアを蓄積することでソ
フトリカバリ特性が得られ、電圧振動を効果的に防止す
ることが可能となる。With such a configuration, even if the reverse recovery current of the built-in reverse conducting diode becomes large due to the relatively high concentration of the second semiconductor layer in the third semiconductor region (auxiliary region), the buffer region is formed in the buffer region. By accumulating carriers, soft recovery characteristics can be obtained, and voltage oscillation can be effectively prevented.
【００２７】[0027]
【発明の実施の形態】以下、本発明の実施形態を図面を
参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２８】なお、以下の実施形態では、第１導電型を
ｎ型とし、第２導電型をｐ型とした場合を示している
が、第１導電型をｐ型とし、第２導電型をｎ型とするこ
とも可能である。In the following embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type is shown, but the first conductivity type is p-type and the second conductivity type is p-type. It is also possible to use an n-type.
【００２９】（第１の実施形態）図１は、本発明の第１
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET.
【００３０】なお、基本的な素子構造や基本的な製造方
法については、すでに図７を用いて説明した従来の縦型
スーパージャンクションＭＯＳＦＥＴとほぼ同様であ
り、図７に示した構成要素に対応する構成要素について
は同一の参照番号を付し、ここではこれらの詳細な説明
は省略する（図２〜図５に示した第２〜第５の実施形態
についても同様）。The basic element structure and the basic manufacturing method are almost the same as those of the conventional vertical super junction MOSFET already described with reference to FIG. 7, and correspond to the components shown in FIG. The same reference numerals are given to the components, and the detailed description thereof is omitted here (the same applies to the second to fifth embodiments shown in FIGS. 2 to 5).
【００３１】本実施形態の縦型スーパージャンクション
ＭＯＳＦＥＴでは、補助領域（第３の半導体領域）のｐ
型低濃度層（第２の半導体層）１１のキャリア積分量Ｑ
ｐは、ｎ型低濃度層（第１の半導体層）１０のキャリア
積分量Ｑｎよりも大きくなる（Ｑｐ＞Ｑｎ）ように設定
されている。また、これらのキャリア積分量は、Ｑｐ及
びＱｎともに、５×１０12ｃｍ-2以下となるように設定
されている。また、ｐ型低濃度層１１とｎ+ 型ドレイン
層（第１の半導体領域）１との間には、ｎ- 型層（第４
の半導体領域）１３が形成されている。In the vertical super junction MOSFET of the present embodiment, the p of the auxiliary region (third semiconductor region)
Integral Q of the low-concentration type layer (second semiconductor layer) 11
p is set to be larger than the carrier integral Qn of the n-type low concentration layer (first semiconductor layer) 10 (Qp> Qn). In addition, these carrier integration amounts are set so that both Qp and Qn are 5 × 10 12 cm −2 or less. Further, between the p-type low concentration layer 11 and the n + -type drain layer (first semiconductor region) 1, an n − -type layer (fourth
Semiconductor region 13) is formed.
【００３２】本実施形態によれば、ターンオフが開始し
てｎ型低濃度層１０が完全に空乏化しても、ｐ型低濃度
層１１の中央部付近（図では左端付近の領域に対応）に
非空乏化領域が残り、ｎ型に比べて移動度の小さいｐ型
のキャリア（ホール）による電流が、この非空乏化領域
を通って排出されるので、高速ターンオフを実現するこ
とができる。According to the present embodiment, even when the turn-off starts and the n-type low concentration layer 10 is completely depleted, the vicinity of the center of the p-type low concentration layer 11 (corresponding to the region near the left end in the figure). The non-depleted region remains, and the current due to the p-type carriers (holes) having a lower mobility than the n-type is discharged through the non-depleted region, so that a high-speed turn-off can be realized.
【００３３】ターンオフ時間は、ＱｐとＱｎとの大小関
係が逆転してＱｎ＞Ｑｐとなると急に遅くなるが、予め
マージンを見込んでＱｐ＞Ｑｎとなるように設定してあ
れば、多少のプロセス変動があってもＱｐ＞Ｑｎの関係
が保持されるので、ターンオフ時間が大きくばらつくよ
うなことはない。例えば、プロセス変動によってＱｐと
Ｑｎとの差が５％程度ばらつく場合があり得るが、Ｑｐ
がＱｎよりも７〜８％程度多くなるように設定しておけ
ば、プロセス変動があっても確実にＱｐ＞Ｑｎの関係を
維持することができる。The turn-off time suddenly becomes slower when Qn> Qp because the magnitude relationship between Qp and Qn is reversed, but if the margin is set in advance so that Qp> Qn, some turn-off time may be required. Even if there is a fluctuation, the relationship of Qp> Qn is maintained, so that the turn-off time does not greatly vary. For example, the difference between Qp and Qn may vary by about 5% due to process variation.
Is set to be about 7 to 8% larger than Qn, it is possible to reliably maintain the relationship of Qp> Qn even if there is a process variation.
【００３４】また、ｐ型低濃度層１１の中央部付近に非
空乏化領域が残ることから、ｐ型低濃度層１１の中央部
の下部領域の電位が非空乏化領域を介してｐ型ベース層
３の電位と同電位となり、ｎ+ 型ドレイン層１との境界
部付近で電界強度が高くなるという問題が考えられる。
本実施形態では、ｎ- 型層１３によって空乏層を広げる
ことができるため、電界が緩和されて高耐圧を維持する
ことができ、このような問題を防止することができる。Further, since a non-depleted region remains near the center of the p-type low-concentration layer 11, the potential of the lower region at the center of the p-type low-concentration layer 11 is increased via the non-depleted region to the p-type base. There is a problem that the potential becomes the same as the potential of the layer 3 and the electric field intensity increases near the boundary with the n + -type drain layer 1.
In the present embodiment, since the depletion layer can be expanded by the n − -type layer 13, the electric field is alleviated, a high breakdown voltage can be maintained, and such a problem can be prevented.
【００３５】なお、ｎ型低濃度層１０とｐ型低濃度層１
１との接合終端領域については、補助領域の端部に半分
のキャリア積分量を持つｐ型低濃度層１１を配置し、通
常のｎ- 型ベース層に対するガードリングやＲＥＳＵＲ
Ｆなどの接合終端構造を適用することが望ましい。The n-type low concentration layer 10 and the p-type low concentration layer 1
1, a p-type low-concentration layer 11 having a half carrier integration amount is arranged at the end of the auxiliary region, and a guard ring or RESUR for a normal n − -type base layer is provided.
It is desirable to apply a junction termination structure such as F.
【００３６】（第２の実施形態）図２は、本発明の第２
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET.
【００３７】本実施形態では、第１の実施形態の素子構
造に加えてさらに、補助領域のｐ型低濃度層１１の下部
領域にｐ- 型層１４を形成している。In the present embodiment, in addition to the element structure of the first embodiment, a p − -type layer 14 is formed in a lower region of the p-type low-concentration layer 11 in the auxiliary region.
【００３８】本実施形態によれば、ｐ- 型層１４がそれ
よりも高不純物濃度のｐ型低濃度層１１より早く空乏化
されるので、ｐ型ベース層３と同電位の領域が入り込ま
ない。その結果、電界が緩和されてより高耐圧を維持す
ることが可能となる。According to the present embodiment, the p − -type layer 14 is depleted faster than the p-type low-concentration layer 11 having a higher impurity concentration, so that a region having the same potential as the p-type base layer 3 does not enter. . As a result, the electric field is alleviated and a higher breakdown voltage can be maintained.
【００３９】なお、図に示した例では、ｐ型低濃度層は
二つの濃度領域としているが、下層側に行くにしたがっ
て不純物濃度が低くなるような３以上の濃度領域を設け
るようにしてもよい。Although the p-type low-concentration layer has two concentration regions in the example shown in the figure, three or more concentration regions may be provided so that the impurity concentration becomes lower toward the lower layer. Good.
【００４０】また、図に示した例では、ｎ型低濃度層１
０は均一濃度となるように形成されているが、ｐ型低濃
度層１１の濃度変化に合わせて、下層側に行くにしたが
って低濃度になるようにしてもよい。Further, in the example shown in FIG.
Although 0 is formed so as to have a uniform concentration, the concentration may become lower toward the lower layer side in accordance with the change in the concentration of the p-type low concentration layer 11.
【００４１】このような構成によれば、数回のエピタキ
シャル成長によって素子を形成する際に、高温に晒され
る時間が長く熱拡散によるＱの変動量の大きな補助領域
下部が低濃度に、高温に晒される時間が短くＱの変動量
の小さな補助領域上部が高濃度に形成されるので、オン
抵抗を低く保ったまま高耐圧化をはかることが可能とな
る。According to such a configuration, when the device is formed by epitaxial growth several times, the lower part of the auxiliary region, which is exposed to a high temperature for a long time and has a large variation in Q due to thermal diffusion, is exposed to a low concentration and exposed to a high temperature. Since the upper part of the auxiliary region having a small variation in Q is formed with a high concentration for a short period of time, it is possible to increase the breakdown voltage while keeping the on-resistance low.
【００４２】（第３の実施形態）図３は、本発明の第３
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET.
【００４３】本実施形態では、ｎ+ 型ドレイン層１と補
助領域との間に、ｎ+ 型ドレイン層よりも低濃度のｎ型
バッファ層１５が形成されている。In this embodiment, an n-type buffer layer 15 having a lower concentration than the n + -type drain layer is formed between the n + -type drain layer 1 and the auxiliary region.
【００４４】本実施形態によれば、ｐ型ベース層３及び
ｐ型低濃度層１１をアノード層とし、ｎ+ 型ドレイン層
１及びｎ型低濃度層１０をカソード層とする内蔵逆導通
ダイオードの逆回復特性を、ソフトリカバリにすること
ができる。また、ｐ型低濃度層１１だけでなくｎ型バッ
ファ層１５内部にも空乏層が広がるので、電界が緩和さ
れ、素子耐圧を向上させることが可能となる。According to this embodiment, a built-in reverse conducting diode having the p-type base layer 3 and the p-type low concentration layer 11 as an anode layer and the n + -type drain layer 1 and the n-type low concentration layer 10 as a cathode layer. The reverse recovery characteristic can be a soft recovery. Further, since the depletion layer spreads not only in the p-type low-concentration layer 11 but also in the n-type buffer layer 15, the electric field is alleviated, and the withstand voltage of the element can be improved.
【００４５】本発明に係るスーパージャンクションＭＯ
ＳＦＥＴでは、Ｑｐ＞Ｑｎとしたために逆回復電流が大
きくなり、ダイオードの電圧が回復する際に、電流減少
率に比例する電圧の跳ね上がりが発生して、電圧振動を
引き起こすという問題を生じやすい。このような場合で
も、ｎ型バッファ層１５を形成することによってキャリ
アが蓄積され、逆回復時のテール領域での電流減少率が
減少して電圧の跳ね上がりが低減されるという効果があ
る。The super junction MO according to the present invention
In the SFET, since Qp> Qn, the reverse recovery current becomes large, and when the voltage of the diode recovers, a voltage jump proportional to the current decrease rate occurs, which tends to cause a problem of causing voltage oscillation. Even in such a case, by forming the n-type buffer layer 15, carriers are accumulated, and there is an effect that the current decrease rate in the tail region at the time of reverse recovery is reduced and the voltage jump is reduced.
【００４６】なお、キャリア蓄積の観点からは、ｎ型バ
ッファ層１５の厚さをキャリアの拡散長以上に設定する
ことが望ましい。例えば、ｎ型バッファ層１５の厚さ
は、耐圧４５００Ｖの素子では７５μｍ程度となるよう
にする。From the viewpoint of carrier accumulation, it is desirable to set the thickness of the n-type buffer layer 15 to be equal to or longer than the carrier diffusion length. For example, the thickness of the n-type buffer layer 15 is set to about 75 μm in a device having a withstand voltage of 4500 V.
【００４７】（第４の実施形態）図４は、本発明の第４
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET.
【００４８】本実施形態では、第３の実施形態の素子構
造に加えてさらに、ｐ- 型層１４が形成されている。す
なわち、本実施形態は、第２の実施形態と第３の実施形
態を併せたような構造を有しており、したがって、第２
の実施形態及び第３の実施形態で得られるそれぞれの効
果を得ることができる。In the present embodiment, a p − type layer 14 is further formed in addition to the element structure of the third embodiment. That is, the present embodiment has a structure as a combination of the second embodiment and the third embodiment, and
The respective effects obtained in the third embodiment and the third embodiment can be obtained.
【００４９】（第５の実施形態）図５は、本発明の第５
の実施形態に係る縦型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した断面図である。(Fifth Embodiment) FIG. 5 shows a fifth embodiment of the present invention.
Vertical super junction MOSF according to the embodiment of the present invention
It is sectional drawing which showed the element structure of ET.
【００５０】本実施形態では、第２の実施形態の素子構
造に加えてさらに、ｎ型バッファ層１５が形成されてお
り、本実施形態によっても、第２の実施形態及び第３の
実施形態で得られる効果と同様の効果を得ることができ
る。In the present embodiment, an n-type buffer layer 15 is further formed in addition to the element structure of the second embodiment. According to the present embodiment, the n-type buffer layer 15 is formed in the second embodiment and the third embodiment. The same effect as the obtained effect can be obtained.
【００５１】（第６の実施形態）図６は、本発明の第６
の実施形態に係る横型スーパージャンクションＭＯＳＦ
ＥＴの素子構造を示した斜視図である。(Sixth Embodiment) FIG. 6 shows a sixth embodiment of the present invention.
Super junction MOSF according to the embodiment of the present invention
It is the perspective view which showed the element structure of ET.
【００５２】なお、基本的な原理については図１等に示
した縦型スーパージャンクションＭＯＳＦＥＴと同様で
あり、図１等に示した構成要素に対応する構成要素につ
いては同一の参照番号を付している。The basic principle is the same as that of the vertical super-junction MOSFET shown in FIG. 1 and the like. Components corresponding to the components shown in FIG. 1 and the like are denoted by the same reference numerals. I have.
【００５３】第１〜第５の実施形態で説明した縦型スー
パージャンクションＭＯＳＦＥＴでは、ドレイン電極６
を半導体基板の一方の主面側に、ソース電極７を半導体
基板の他方の主面側にそれぞれ形成した構造であった
が、本実施形態の横型スーパージャンクションＭＯＳＦ
ＥＴでは、ドレイン電極６及びソース電極７は半導体基
板の同一主面側に形成されている。In the vertical type super junction MOSFET described in the first to fifth embodiments, the drain electrode 6
Is formed on one main surface of the semiconductor substrate, and the source electrode 7 is formed on the other main surface of the semiconductor substrate.
In ET, the drain electrode 6 and the source electrode 7 are formed on the same main surface side of the semiconductor substrate.
【００５４】このような横型スーパージャンクションＭ
ＯＳＦＥＴにおいても、縦型スーパージャンクションＭ
ＯＳＦＥＴと同様、補助領域におけるｐ型低濃度層１１
のキャリア積分量Ｑｐとｎ型低濃度層１０のキャリア積
分量Ｑｎとの関係をＱｐ＞Ｑｎとなるように設定すると
ともに、ｐ型低濃度層１１とｎ+ 型ドレイン層１との間
にｎ- 型層１３を設けることにより、縦型スーパージャ
ンクションＭＯＳＦＥＴと同様の効果を得ることが可能
となる。Such a horizontal super junction M
In OSFET, vertical super junction M
Like the OSFET, the p-type low concentration layer 11 in the auxiliary region
Is set so that Qp> Qn, and n is located between the p-type low-concentration layer 11 and the n + -type drain layer 1. - by providing the mold layer 13, it is possible to obtain the same effect as the vertical superjunction MOSFET.
【００５５】なお、図６に示した横型スーパージャンク
ションＭＯＳＦＥＴは、図１に示した第１の実施形態の
縦型スーパージャンクションＭＯＳＦＥＴに対応する構
造となっているが、その他の実施形態において説明した
縦型スーパージャンクションＭＯＳＦＥＴに対応する構
造を横型スーパージャンクションＭＯＳＦＥＴに適用す
ることも可能である。Although the horizontal super junction MOSFET shown in FIG. 6 has a structure corresponding to the vertical super junction MOSFET of the first embodiment shown in FIG. 1, the vertical super junction MOSFET described in the other embodiments is used. It is also possible to apply a structure corresponding to the type super junction MOSFET to a lateral type super junction MOSFET.
【００５６】以上、本発明の実施形態を説明したが、本
発明は上記実施形態に限定されるものではない。例え
ば、上記実施形態では、基本となる素子構造をＭＯＳＦ
ＥＴとしたが、ＳＩＴなど他の素子構造に対して適用す
ることも可能である。その他、本発明はその趣旨を逸脱
しない範囲内において種々変形して実施することが可能
である。Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment. For example, in the above embodiment, the basic element structure is MOSF
Although ET has been described, the present invention can be applied to other element structures such as SIT. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.
【００５７】[0057]
【発明の効果】本発明によれば、補助領域の一方の半導
体層のキャリア積分量Ｑ１と他方の半導体層のキャリア
積分量Ｑ２との関係がＱ２＞Ｑ１となるようにしたの
で、ターンオフの際に他方の半導体層に非空乏化領域が
残存し、この非空乏化領域を通って電流が排出されるこ
とになり、ターンオフを高速化することが可能となる。
また、ドレイン側の高不純物濃度領域と補助領域との間
に低不純物濃度領域を設けることにより、空乏層が低不
純物濃度領域に広がって電界を緩和するため、高耐圧化
をはかることが可能となる。According to the present invention, the relationship between the carrier integral Q1 of one semiconductor layer in the auxiliary region and the carrier integral Q2 of the other semiconductor layer is such that Q2> Q1. Then, a non-depleted region remains in the other semiconductor layer, and current is discharged through this non-depleted region, so that turn-off can be speeded up.
Further, by providing a low impurity concentration region between the high impurity concentration region on the drain side and the auxiliary region, the depletion layer spreads to the low impurity concentration region and relaxes the electric field, so that a high breakdown voltage can be achieved. Become.
【図１】本発明の第１の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 1 is a sectional view showing an element structure of a vertical super junction MOSFET according to a first embodiment of the present invention.
【図２】本発明の第２の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 2 is a sectional view showing an element structure of a vertical super junction MOSFET according to a second embodiment of the present invention.
【図３】本発明の第３の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 3 is a sectional view showing an element structure of a vertical super junction MOSFET according to a third embodiment of the present invention.
【図４】本発明の第４の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 4 is a sectional view showing an element structure of a vertical super junction MOSFET according to a fourth embodiment of the present invention.
【図５】本発明の第５の実施形態に係る縦型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した断面図。FIG. 5 is a sectional view showing an element structure of a vertical super junction MOSFET according to a fifth embodiment of the present invention.
【図６】本発明の第６の実施形態に係る横型スーパージ
ャンクションＭＯＳＦＥＴの素子構造を示した斜視図。FIG. 6 is a perspective view showing an element structure of a lateral super junction MOSFET according to a sixth embodiment of the present invention.
【図７】従来技術に係る縦型スーパージャンクションＭ
ＯＳＦＥＴの素子構造を示した断面図。FIG. 7 shows a vertical super junction M according to the prior art.
FIG. 4 is a cross-sectional view illustrating an element structure of an OSFET.
１…ｎ+ 型ドレイン層（第１の半導体領域） ３…ｐ型ベース層（第２の半導体領域） ４…ｎ+ 型ソース層 ５…ｐ+ 型層 ６…ドレイン電極 ７…ソース電極 ８…ゲート電極 ９…ゲート絶縁膜 １０…ｎ型低濃度層（第１の半導体層） １１…ｐ型低濃度層（第２の半導体層） １３…ｎ- 型層（第４の半導体領域） １４…ｐ- 型層 １５…ｎ型バッファ層（第４の半導体領域）DESCRIPTION OF SYMBOLS 1 ... n + type drain layer (1st semiconductor region) 3 ... p-type base layer (2nd semiconductor region) 4 ... n + type source layer 5 ... p + type layer 6 ... drain electrode 7 ... source electrode 8 ... Gate electrode 9 Gate insulating film 10 n-type low concentration layer (first semiconductor layer) 11 p-type low concentration layer (second semiconductor layer) 13 n - type layer (fourth semiconductor region) 14. p − type layer 15... n type buffer layer (fourth semiconductor region)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 八幡 彰博 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 (72)発明者 中村 和敏 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝研究開発センター内 Ｆターム(参考） 5F040 DA00 EB01 EB13 EE01 EE05 EF13 EF18 EM01 EM02 EM03 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihiro Yawata 1st station, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba R & D Center (72) Inventor Kazutoshi Nakamura Komukai, Sai-ku, Kawasaki-shi, Kanagawa No. 1 Toshiba Town F-term in Toshiba R & D Center (reference) 5F040 DA00 EB01 EB13 EE01 EE05 EF13 EF18 EM01 EM02 EM03
Claims (2)
導体領域と、 前記第１の半導体領域と離間して形成され第２導電型の
不純物が含有された第２の半導体領域と、 前記第１の半導体領域と前記第２の半導体領域との間に
設けられ、第１導電型の不純物が含有された第１の半導
体層と第２導電型の不純物が含有された第２の半導体層
とが前記第１の半導体領域と第２の半導体領域とが対向
する方向と交差する方向に交互に繰り返し配置された第
３の半導体領域と、 を有する半導体装置であって、 交互に繰り返し配置された前記第１の半導体層及び第２
の半導体層の繰り返し方向のキャリア積分量が、第２の
半導体層の方が第１の半導体層よりも大きくなるように
構成され、 前記第１の半導体領域と前記第３の半導体領域の少なく
とも第２の半導体層との間に前記第１の半導体領域より
も第１導電型の不純物濃度の低い第４の半導体領域が形
成されていることを特徴とする半導体装置。A first semiconductor region containing an impurity of a first conductivity type; and a second semiconductor region formed separately from the first semiconductor region and containing an impurity of a second conductivity type. A first semiconductor layer provided between the first semiconductor region and the second semiconductor region and containing a first conductivity type impurity; and a second semiconductor layer containing a second conductivity type impurity. A third semiconductor region in which a semiconductor layer and a third semiconductor region are alternately and repeatedly arranged in a direction intersecting a direction in which the first semiconductor region and the second semiconductor region face each other. The first semiconductor layer and the second
The second semiconductor layer is configured to have a larger carrier integration amount in the repetition direction of the semiconductor layer than the first semiconductor layer, and at least the first semiconductor region and the third semiconductor region A semiconductor device, wherein a fourth semiconductor region having a first conductivity type impurity concentration lower than that of the first semiconductor region is formed between the second semiconductor layer and the second semiconductor layer.
は、前記第１の半導体領域側の方が前記第２の半導体領
域側よりも不純物濃度が低くなるように構成された複数
の半導体層からなることを特徴とする請求項１に記載の
半導体装置。2. The semiconductor device according to claim 1, wherein the second semiconductor layer of the third semiconductor region has a plurality of semiconductor layers configured to have a lower impurity concentration on the first semiconductor region side than on the second semiconductor region side. 2. The semiconductor device according to claim 1, comprising a semiconductor layer.
Priority Applications (1)
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|---|---|---|---|
| JP27825599A JP3507732B2 (en) | 1999-09-30 | 1999-09-30 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27825599A JP3507732B2 (en) | 1999-09-30 | 1999-09-30 | Semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2001102577A true JP2001102577A (en) | 2001-04-13 |
| JP3507732B2 JP3507732B2 (en) | 2004-03-15 |
Family
ID=17594796
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27825599A Expired - Lifetime JP3507732B2 (en) | 1999-09-30 | 1999-09-30 | Semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3507732B2 (en) |
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