JP2001196604A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge a depletion layer in a small dead space at the n(-) side of a termination region, and to suppress increase of leakage currents. SOLUTION: At least, two narrow p(++) auxiliary FLR 24 having concentration for preventing punch-through are formed in a p(+) FLR by using a p(+) main FLR 23 having a shallow junction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a structure of a diode and a transistor.

[0002]

2. Description of the Related Art In a power semiconductor device, a termination region is provided outside a switching region, which is a region through which a current flows, in order to release a line of electric force in a non-conductive state to the outside of the semiconductor. As a termination region, in MOSFETs and IGBTs, SiC is generally formed not on the end face of the element but on the surface of a peripheral region.

In order to ensure a high withstand voltage, it is necessary to reduce the electric field intensity in the termination region. For this reason, the literature: International Conference of Silicon Carbid
e III-Nitrides and Related Materials 199
7, p. 136, the termination structure is JTE (Junction Termination Extensio).
There is an attempt to adopt the method n). FIG. 2 is a schematic cross-sectional view showing the structure of the JTE, which is an example in which the structure is combined with a junction FET.

As can be seen from FIG. 2, the feature of the JTE structure is that strip-shaped p-type regions 21 and 22 whose concentrations are sequentially reduced are formed outside the gate p (+) 25 in contact with each other.

The highest electric field strength at the surface is due to p
This is a bonding interface between the mold region and the n-termination region. By lowering the concentration of the p-type region in contact with the junction interface, the extent of the depletion layer to the p-type region is increased, the electric field intensity on the surface is reduced, and the rate of dielectric breakdown is suppressed.

[0006]

In order to minimize the electric field strength at the p (+) / n junction, the concentration of the p-layer should be reduced to the same level as that of the n-layer. However, in consideration of manufacturing variations, the lower limit of the concentration of the p region is about twice that of the n layer.

[0007] The electric field reduction effect by reducing the concentration of the p-type region so far is as follows from the Poisson equation when the extension of the depletion layer at the p (+) / n junction is approximated only to the n-side.
It is at most 2/3 of the power of 1/2, and is reduced only to about 80%. Therefore, in the Si high withstand voltage element, the FLR is provided outside the gate p (+) region 25 without contacting the p (+) region.
A structure in which a plurality of band-shaped p (+) regions called (Field Limiting Ring) are arranged is adopted.

The width of FLR is several μm to 10 μm for Si.
μm order is used. Exceeding this does not affect the characteristics, but the p (+) FLR becomes a dead space, which is not preferable because the useless area increases.

On the other hand, in the case of SiC, the insulation electric field strength is S
Since i is about 7 times as large as i, the width of the FLR can be narrowed accordingly, and can be from 1 μm or less to about 2 to 3 μm.

The p (+) FLR is formed by selectively implanting boron (B) or aluminum (Al). Since the diffusion coefficient of SiC is significantly smaller than that of Si, diffusion by heat treatment is small, but 50% or more of the implantation depth is implanted in the lateral direction due to the lateral expansion at the time of ion implantation.

In the case of a withstand voltage of 3,000 V, the peak concentration of the gate p (+) is set to 5 × 10
^{If it is 17} cm- ³ , a junction depth of about 1 μm is required.
Even if the lateral diffusion is 50%, it will be 1 μm wider than the designed value. This value is comparable to the design width of the p (+) FLR, and in some cases becomes larger than the design width. Therefore, when a junction exceeding 1 μm is applied to the FLR, there is a disadvantage that a dead space that is not originally required must be secured. Occurs.

In order to prevent this, it is necessary to make the junction depth shallow. In this case, punch-through occurs in the p (+) FLR, and the depletion layer can be expanded to the n (-) side of the termination region. Disappears.

An object of the present invention is to provide a semiconductor device such as SiC having a higher dielectric breakdown electric field than Si.
An object of the present invention is to propose a semiconductor device having a structure in which a depletion layer can be expanded with a small dead space on the n (−) side of a termination region and an increase in leak current can be suppressed.

[0014]

The gist of the present invention for solving the above problems is as follows.

A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration, and a first or second conductivity type formed on the first main surface of the base and having a lower resistance than the base. A first layer, a first electrode formed on the surface of the first layer, a second region formed on the second main surface of the base and having a conductivity type different from that of the base, and formed on the second region. A semiconductor device having a terminated second electrode, and having a termination region surrounding the periphery of the second region, wherein the termination region has at least one first band-shaped region having a second conductivity type, A semiconductor device is characterized in that two or more second band-shaped regions having a relatively high concentration and a concentric shape are formed in the first band-shaped region.

That is, in the present invention, p (+) having a shallow junction is used.
At least two narrow p (++) auxiliary FLRs having a concentration that does not punch through within the p (+) main FLR using the main FLR
This is the one formed.

In the p (+) main FLR, a higher concentration of narrow p
(++) An auxiliary FLR is provided to prevent punch-through even when the p (+) main FLR is a shallow junction, and to expand a depletion layer in the n (-) region of termination.

The p (++)-assisted FLR is formed by ion implantation. However, as the concentration increases, the number of defects created at the time of ion implantation increases, and recovery becomes difficult even by heat treatment. When a high electric field is applied to the defective portion, the breakdown voltage is degraded. In the present invention, the p (++) auxiliary FLR which is a high concentration region is
Since the electric field is formed in the lower concentration p (+) main FLR, the electric field is relaxed by the p (+) main FLR, and is not directly applied to the p (++) auxiliary FLR, thereby preventing the withstand voltage deterioration. It becomes possible.

Since at least two p (++) auxiliary FLRs are provided, the lines of electric force escape from the auxiliary FLR to the outside of the element. As a result, the width of the main FLR is equivalently reduced, and the dead space can be reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on embodiments.

[Embodiment 1] FIG. 1 shows the SiC of this embodiment.
It is a schematic cross section of a junction FET. In the figure, a high-concentration n (+) substrate 11 serving as a drain region, an n (-) epitaxial layer 12 serving as a drift layer are formed thereon, and an n (+) source region 14 and a ring-shaped p (+) An FLR 23, a high concentration p (++) auxiliary FLR 24, a guard ring / gate p (+) region 25, a drain electrode 33, a source electrode 34, a gate electrode 35, an n (+) channel stopper 41, and a field plate 42 are formed. I have.

In this embodiment, p (++)-assisted FLR24
Has a structure in which two are arranged in each main FLR 23. The main FLR23 has a peak concentration of 2 × 10 ¹⁷ cm to ³ and a depth of 0.
The auxiliary FLR 24 had a peak concentration of 5 × 10 ¹⁸ cm to ³ , a depth of 0.3 μm, a width of 2 μm, and an interval of 2 μm.

When only the main FLR 23 is used, the spread of the depletion layer to the p (+) side when 3,000 V is applied is about 1.4 μm, punch-through occurs, and the depletion layer to the n (−) side. Spread is small.

On the other hand, in the part of the auxiliary FLR 24,
Punch through does not occur because of the higher concentration of p (++) than the main FLR23.

Since the electric flux lines are distributed while avoiding only the auxiliary FLR 24, the main FLR 23 does not become a dead space with respect to the expansion of the depletion layer, and the depletion layer can be effectively expanded. . In particular, since the auxiliary FLR 24 can be made shallow, its width can be made narrow,
It is possible to narrow the area that becomes a dead space.
Therefore, the auxiliary FLRs 24 can be divided and arranged, and the lines of electric force can be distributed between the auxiliary FLRs 24. This is also effective in reducing the dead space.

Further, since the high concentration p (++) is not in direct contact with the n (-) layer, no electric field peak is applied to the auxiliary FLR 24.

In the high-concentration region, a defect that cannot be completely recovered by the heat treatment may be formed. As the concentration increases, the density of irrecoverable defects increases. In this embodiment, since the structure is such that the high electric field region and the high defect density region can be separated from each other, it is possible to suppress an increase in leak current due to the high electric field, and to obtain good reverse characteristics.

Further, in this embodiment, the main FLR2
The depth of 3 was made shallower than the gate p (+) region 25 in the conduction region. The gate p (+) region 25 is also formed by ion implantation, but it is necessary to increase the implantation energy to form a deep junction.

In the case of high-energy ion implantation, as in the case of high-doping implantation, defects that cannot be completely recovered by heat treatment are easily formed. Therefore, the leak current increases as the electric field intensity increases.

Generally, in a pn junction formed with a curvature, the electric field intensity has a peak in a region where the curvature is large (the radius of curvature is small). On the other hand, in the case of ion implantation, the impurity distribution has a Gaussian distribution-like shape, but its width is known to increase as the implantation energy increases. Therefore, the curvature of the pn junction becomes smaller in the high energy ion implantation.

In this embodiment, the main FLR 23 has a depth smaller than that of the gate p (+) region 25. Therefore, the main FLR 23 is characterized in that it is larger in comparison with the curvature of the pn junction. Can be set not to the p (+) gate region, which is a deep pn junction where there is a concern about residual defects, but to the main FLR where there is no concern about defects. Therefore, even if a deep pn junction is formed in the conduction region, an increase in leakage current can be suppressed.

Embodiment 2 FIG. 3 is a schematic sectional view showing a buried gate type junction FET of this embodiment. In the figure, a surface side gate p (+) region 26 and a buried gate p (+) region 27 are formed. In this embodiment, a channel is formed between the surface gate region 26 and the buried gate region 27.

As in the first embodiment, the auxiliary FLR 24
The two FLRs are arranged in the LR 23 and the main FLR
Is shallower than the guard ring and gate p (+) region. Therefore, an excessive dead space is not required, and the depletion layer forms n on the termination surface.
It can be efficiently spread to the (-) side, and the increase in leak current can be suppressed.

Embodiment 3 FIG. 4 is a schematic sectional view showing a planar type MOSFET according to this embodiment. In the figure, an oxide film 40 for forming a guard ring / p well region 28 and a MOS interface is formed. In the case of the planar type, since the gate oxide film is formed on the surface, the n-type inversion layer as the channel is formed on the surface of the p-well region.

Also in the present embodiment, the structure is such that two auxiliary FLRs 24 are arranged in each main FLR 23, and
The LR has a depth smaller than the guard ring and gate p (+) region. Therefore, the depletion layer does not require an excessive dead space, and
It can be efficiently spread to the (-) side, and the increase in leak current can be suppressed.

[Embodiment 4] FIG. 5 is a schematic sectional view showing a trench type MOSFET according to this embodiment. In the p-well region 28, a channel is formed on the trench side wall of the p-well region 28 because the vicinity of the interface with the oxide film 40 is inverted to the n-type.

The current flows from the n (+) source region 14 through the trench sidewall which is the inversion layer of the p-well region 28 which is the channel, and passes through the n (-) type epitaxial layer 1 which is the drift layer.
2 to an n (+) substrate 11 which is a drain region.

Also in this embodiment, the structure is such that two auxiliary FLRs 24 are arranged in each main FLR 23, and
(The depth of LR is set as a guard ring and gate p-well) Region 28
The structure was shallower. Therefore, the depletion layer can efficiently spread to the n (-) side of the termination surface without requiring an excessive dead space, and an increase in leak current can be suppressed.

As described above, in the first to fourth embodiments, the auxiliary FL
Although the structure in which two R24s are arranged for each main FLR 23 has been described, the same applies to three or more R24s, and can be changed according to the photolithography process accuracy.

In order to improve the distribution of the lines of electric force,
By using a structure in which the number of auxiliary FLRs 24 is different for each main FLR 23, it is possible to further improve the breakdown voltage or reduce the leak current, but the number of auxiliary FLRs 24 is two or more from the viewpoint of eliminating dead space. It is necessary.

The structure of this embodiment can be applied to other FETs and diodes, and similar effects can be obtained.

[Embodiment 5] FIG. 6 is a schematic circuit diagram of an inverter device using a diode and an FET to which the present invention is applied.

In the figure, 51, 52, 53, 54, 5
Reference numerals 5 and 56 denote FETs according to the present invention. 61, 62, 63, 64, 65 and 66 are diodes according to the present invention.

MOSFETs 51 and 52, 53 and 54, 5
5 and 56 are set as one set, and two MOs in each set are set.
A device in which the SFETs are switched complementarily and each group is independently switched to obtain the current / voltage input to the input terminal 1 and the input terminal 2 independently from the output 1 to the output 3. It is.

Specifically, it is a three-phase inverter that uses a DC voltage as an input and a three-phase AC as an output. In that case,
A load such as a three-phase inductor is connected to the output terminals 1 to 3.

Since the diode and the transistor according to the present invention use a semiconductor such as SiC having a small on-loss and can obtain a high breakdown voltage with a low leakage current, by using the semiconductor device of the present invention for an inverter device,
The loss generated by the semiconductor device can be reduced, and the efficiency of a system using the inverter device can be improved.

Although the above embodiments have been described with reference to the SiC element, the present invention is not limited to this. The present invention can be applied to other cases where a semiconductor material having an avalanche breakdown field larger than Si is used. It is also useful for wide gap semiconductors such as GaN).

[0048]

According to the present invention, since the dead space in the termination region of the semiconductor device can be reduced, the chip area can be reduced and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a structure of a SiC junction FET of Example 1.

FIG. 2 is a schematic sectional view showing the structure of a conventional junction FET.

FIG. 3 is a schematic cross-sectional view showing a structure of a buried-gate junction FET of Example 2.

FIG. 4 is a schematic cross-sectional view illustrating a structure of a planar MOSFET according to a third embodiment.

FIG. 5 is a schematic cross-sectional view illustrating a structure of a trench MOSFET according to a fourth embodiment.

FIG. 6 is a schematic circuit diagram of an inverter device using a diode and an FET to which the present invention is applied.

[Explanation of symbols]

11 ... n (+) substrate, 12 ... n (-) epitaxial layer, 14
... n (+) source region, 23 ... p (+) main FLR, 24 ... p (+)
+) Auxiliary FLR, 25 ... guard ring or gate p
(+) Region, 26: gate p (+) region, 27: buried gate p-type region, 28: guard ring / p-well region, 33:
Drain electrode, 34 ... source electrode, 35 ... gate electrode,
40 ... oxide film, 41 ... n (+) channel stopper, 42
... Field plates, 51,52,53,54,5
5, 56 ... FET according to the present invention, 61, 62, 63, 6
4, 65, 66 ... diodes according to the present invention.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tsutomu Yao 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference) 5F102 FA01 GB04 GC07 GC08 GD04 GJ02 GR07

Claims (3)

[Claims] 1. A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration and a first or second conductivity type formed on a first main surface of the base and lower than the base. A first layer of resistance, a first electrode formed on the surface of the first layer, a second region formed on the second main surface of the base and having a conductivity type different from that of the base, and the second region A semiconductor device having a termination region surrounding the periphery of the second region, wherein the termination region has a second conductivity type. And two or more second band-shaped regions having a relatively high concentration and a concentric shape are formed in the first band-shaped region. 2. A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration, and a first or second conductivity type formed on a first main surface of the base and lower than the base. A first layer of resistance, a first electrode formed on the surface of the first layer, a second region formed on the second main surface of the base and having a conductivity type different from that of the base, and the second region A second electrode which is a control electrode formed on the first region, a third region of the first conductivity type having a high impurity concentration formed on the second main surface of the base, and a third electrode formed on the third region. A semiconductor device comprising a termination region surrounding a periphery of a second region where the third electrode is not formed, wherein the termination region has at least one first band-shaped region having a second conductivity type. And a second band-shaped region having a relatively high concentration and a concentric shape relative to the first band-shaped region. The semiconductor device characterized by but are formed two or more. 3. The semiconductor device according to claim 1, wherein the depth of the first band-shaped region is smaller than that of the second region.