JP2002076370A - Super junction schottky diode - Google Patents

Super junction schottky diode

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Publication number
JP2002076370A
JP2002076370A JP2000268460A JP2000268460A JP2002076370A JP 2002076370 A JP2002076370 A JP 2002076370A JP 2000268460 A JP2000268460 A JP 2000268460A JP 2000268460 A JP2000268460 A JP 2000268460A JP 2002076370 A JP2002076370 A JP 2002076370A
Authority
JP
Japan
Prior art keywords
region
schottky diode
junction
conductive
schottky
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000268460A
Other languages
Japanese (ja)
Other versions
JP4770009B2 (en
Inventor
Katsunori Ueno
勝典 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
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Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2000268460A priority Critical patent/JP4770009B2/en
Publication of JP2002076370A publication Critical patent/JP2002076370A/en
Application granted granted Critical
Publication of JP4770009B2 publication Critical patent/JP4770009B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

Abstract

PROBLEM TO BE SOLVED: To speed up the switching of a Schottky barrier diode having a super junction structure which flows a current in on-state and depletes in off-state. SOLUTION: A high resistance region 11 having a substantially high resistivity is inserted between a p-column 10 forming parallel p-n layers 15 and a Schottky electrode 7. A p-high-resistance region 13 having a high resistance may be inserted between the p-column 10 and the electrode 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、オン状態では電流
を流すとともにオフ状態では空乏化する並列pn層から
なる特殊な構造を備える、高耐圧、大電流容量の超接合
ダイオード、特に超接合ショットキーダイオードに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-breakdown-voltage, large-current-capacity super-junction diode, and more particularly to a super-junction shot having a special structure comprising a parallel pn layer which flows a current in an on state and depletes in an off state. Key diode.

【0002】[0002]

【従来の技術】一般にダイオードの順方向特性は、図6
に示した特性図のようになっている。この図の横軸は順
方向電圧、縦軸は電流である。一定の立ち上がり電圧
(ビルトイン電圧)までは電流が流れず、それ以上バイ
アスされると電流が流れはじめる。一定の電流に達した
ときの電圧をオン電圧、また電圧−電流カーブの傾きを
オン抵抗と称する。
2. Description of the Related Art Generally, the forward characteristics of a diode are shown in FIG.
The characteristic diagram shown in FIG. The horizontal axis in this figure is the forward voltage, and the vertical axis is the current. The current does not flow until a certain rising voltage (built-in voltage), and the current starts to flow when biased further. The voltage at which a certain current is reached is called the on-voltage, and the slope of the voltage-current curve is called the on-resistance.

【0003】図5(a)〜(c)は各種電力用ダイオー
ドの構造を示す断面図である。図5(a)はいわゆるp
nダイオードであり、(b)はショットキーダイオー
ド、(c)はその融合型のダイオードである。それぞれ
の特徴は次のようなものである。図5(a)のpnダイ
オードは、pアノード層2からnドリフト層3へ少数キ
ャリアを注入して、nドリフト層3の電気伝導度を著し
く低下させることができるために、オン抵抗が低くな
り、高耐圧のダイオードでも大電流を流すことができ
る。その反面、ターンオフ時には、nドリフト層3から
注入された少数キャリアを排除しなければならず、スイ
ッチング速度が遅く、そのときの発生損失が大きくなっ
てしまうという欠点を有している。
FIGS. 5A to 5C are sectional views showing the structures of various power diodes. FIG. 5 (a) shows the so-called p
(b) is a Schottky diode, and (c) is a diode of the fusion type. Each feature is as follows. In the pn diode of FIG. 5A, minority carriers can be injected from the p anode layer 2 into the n drift layer 3 to significantly reduce the electric conductivity of the n drift layer 3, so that the on-resistance is reduced. In addition, a large current can flow even with a high breakdown voltage diode. On the other hand, at the time of turn-off, the minority carriers injected from the n-drift layer 3 must be removed, which has a disadvantage that the switching speed is slow and the loss generated at that time becomes large.

【0004】図5(b)のショットキーダイオードで
は、pnダイオードに比較してショットキー電極7とn
ドリフト層3の間のバリアハイトを制御することが可能
で、そのためにビルトイン電圧が低く設定可能である。
このため、低耐圧のダイオードではpnダイオードより
も低いオン電圧が実現できる。また、pnダイオードの
ような少数キャリアの蓄積効果が無いので、スイッチン
グ速度が早く、スイッチング時の発生損失が著しく小さ
いという特長がある。
In the Schottky diode of FIG. 5B, the Schottky electrodes 7 and n
The barrier height between the drift layers 3 can be controlled, so that the built-in voltage can be set low.
For this reason, a low breakdown voltage diode can realize a lower on-state voltage than a pn diode. Further, since there is no effect of accumulating minority carriers as in the case of a pn diode, there is a feature that the switching speed is high and the loss generated during switching is extremely small.

【0005】その反面、逆電圧が印加されると、ショッ
トキー電極7と半導体のバリアハイトが低下して、逆方
向のリーク電流が増加すること、および伝導度変調が無
いため、高耐圧のダイオードでは大電流を流したときの
オン抵抗が大きくなってしまうという欠点がある。オン
抵抗RonAと耐圧VB とは次式のような関係にある。
On the other hand, when a reverse voltage is applied, the barrier height of the Schottky electrode 7 and the semiconductor decreases, the leakage current in the reverse direction increases, and there is no conductivity modulation. There is a disadvantage that the ON resistance when a large current flows is increased. The on-resistance R on A and the breakdown voltage V B have the following relationship.

【0006】[0006]

【数1】 ここで、μは電子移動度、εは半導体の誘電率、Ec
最大電界強度である。
(Equation 1) Here, μ is the electron mobility, ε is the dielectric constant of the semiconductor, and E c is the maximum electric field strength.

【0007】このように耐圧が上昇すると急激にオン抵
抗が上昇する。なお、図5(b)では、ガードリング6
を備えている。これは、p型の領域ではあるが図5
(a)のpn接合とは異なり、ショットキー電極7の周
辺部にのみ形成して、ショットキー電極7の周辺に電界
が集中するのを防止するためのものである。
As described above, when the breakdown voltage increases, the on-resistance rapidly increases. In FIG. 5B, the guard ring 6 is used.
It has. Although this is a p-type region, FIG.
Unlike the pn junction of (a), the pn junction is formed only at the periphery of the Schottky electrode 7 to prevent the electric field from concentrating around the Schottky electrode 7.

【0008】pnダイオードとショットキーダイオード
との両者の欠点を補うように提案された構造が図5
(c)の融合型ダイオードである。図5(b)のショッ
トキー電極の内側に少数キャリア注入用の注入用p領域
8が設けられた構造となっている。用途に合わせて注入
用p領域8の寸法を設計することによって、最適なオン
抵抗とスイッチング損失のバランスを実現することがで
きる。
FIG. 5 shows a structure proposed to compensate for the disadvantages of both the pn diode and the Schottky diode.
(C) is a fused diode. The structure is such that an injection p region 8 for minority carrier injection is provided inside the Schottky electrode of FIG. 5B. By designing the dimensions of the implantation p region 8 according to the application, an optimal balance between the on-resistance and the switching loss can be realized.

【0009】一方近年、新しい接合構造によって、高耐
圧半導体素子の低オン抵抗化にブレークスルーをもたら
しうることが見いだされた[EP0053854、US
P5216275、USP5438215および特開平
9−266311号公報、Deboy, G. 他:Technical Di
gest of IEDM'98,(1998 年),683 〜685 頁参照]。この
構造は、ドリフト層を、不純物濃度を高めたn型の領域
とp型の領域を交互に配置した並列pn層で構成し、オ
フ状態の時は空乏化して耐圧を負担するようにしたもの
である。なお、そのような並列pn層からなるドリフト
層を備える半導体素子を超接合半導体素子と称すること
とした。
On the other hand, in recent years, it has been found that a new junction structure can cause a breakthrough in lowering the on-resistance of a high breakdown voltage semiconductor device [EP0053854, US
P5216275, US Pat. No. 5,438,215 and JP-A-9-266311, Deboy, G. et al .: Technical Di
gest of IEDM '98, (1998), pp. 683 to 685]. In this structure, the drift layer is constituted by a parallel pn layer in which an n-type region and a p-type region with an increased impurity concentration are alternately arranged, and is depleted when off to bear a breakdown voltage. It is. Note that a semiconductor element including such a drift layer composed of a parallel pn layer is referred to as a super junction semiconductor element.

【0010】本発明の出願者も特開2000−4082
2号公報において、そのような半導体素子の簡単な製造
方法を提案している。この構造では、オン抵抗RonAと
耐圧VB との関係は次式のようになる[Fujihira, T :
Japnese J. of Appl. Phys. 36巻,(1997 年)6254 〜62
62頁参照] 。
The applicant of the present invention also discloses Japanese Patent Application Laid-Open No. 2000-4082.
Japanese Patent Application Laid-open No. 2 (1994) proposes a simple method for manufacturing such a semiconductor device. In this structure, the relationship between the on-resistance R on A and the breakdown voltage V B is as follows [Fujihira, T:
Japanese J. of Appl. Phys. 36, (1997) 6254-62
See page 62].

【0011】[0011]

【数2】 ここで、dは超接合の幅である。(Equation 2) Here, d is the width of the super junction.

【0012】すなわち、先の(1)式ではオン抵抗が耐
圧の二乗に比例していたのに対し、超接合半導体素子で
は、耐圧の一乗に比例するだけであり、耐圧が高くなっ
てもオン抵抗はそれほど増大しないことを示している。
上記Fujihiraの報文によれば、たとえば1000V 耐圧
のデバイスの場合には、d=5μm 、この時の不純物濃
度とエピタキシャル層の厚さをそれぞれ5×1015c
m-3、60μm とすると、オン抵抗は従来の約1/10
にまで下がる。
That is, in the above equation (1), the on-resistance is proportional to the square of the withstand voltage. On the other hand, in the super-junction semiconductor element, the on-resistance is only proportional to the square of the withstand voltage. This shows that the resistance does not increase so much.
According to Fujihira's report, for example, in the case of a device with a withstand voltage of 1000 V, d = 5 μm, and the impurity concentration and the thickness of the epitaxial layer at this time are each 5 × 10 15 c
Assuming m −3 and 60 μm, the on-resistance is about 1/10
Down to.

【0013】一般のショットキーダイオードでは特に電
極の終端部へと集中する電流によって破壊することが多
いが、超接合構造を利用したショットキーダイオードと
することにより、各コラムに沿って電流が流れることか
ら局部的な電流集中が避けられるという効果もある。
Although a general Schottky diode often breaks down due to a current concentrated particularly on the terminal portion of the electrode, a Schottky diode using a super junction structure causes a current to flow along each column. Therefore, there is also an effect that local current concentration can be avoided.

【0014】[0014]

【発明が解決しようとする課題】スイッチング損失の低
減と、またスイッチング時に発生する大きなノイズの低
減の強い要望に対し、少数キャリアを注入するpnダイ
オードでは損失が大きく、かつノイズの発生が大きいと
いう問題がある。本来、スイッチング損失を低減してい
こうとすると、図5(b)のショットキーダイオードが
最も好ましい。
In response to a strong demand for reduction of switching loss and reduction of large noise generated at the time of switching, a problem is that a pn diode injecting minority carriers has large loss and large noise. There is. Originally, to reduce the switching loss, the Schottky diode of FIG. 5B is most preferable.

【0015】図7は、特開2000−40822号公報
に開示されたものと同種の超接合型のショットキーダイ
オードの一例である。4は低抵抗のn+ カソード層、1
5はnドリフト領域9とp仕切り領域10とからなる並
列pn層である。表面層には、n- 高抵抗層11がのこ
され、一部p仕切り領域10が露出していて、n- 高抵
抗層11とショットキーバリアを形成するショットキー
電極7が設けられている。n+ カソード層4の裏面には
カソード電極5が設けられている。
FIG. 7 shows an example of a super-junction type Schottky diode similar to that disclosed in Japanese Patent Application Laid-Open No. 2000-40822. 4 is a low resistance n + cathode layer, 1
5 is a parallel pn layer composed of an n drift region 9 and a p partition region 10. On the surface layer, an n high resistance layer 11 is provided, a part of the p partition region 10 is exposed, and a Schottky electrode 7 that forms a Schottky barrier with the n high resistance layer 11 is provided. . A cathode electrode 5 is provided on the back surface of the n + cathode layer 4.

【0016】しかしながら、式(1)で示したように、
本質的にはショットキーダイオードであるから、pnダ
イオードのような少数キャリアの注入は無く、大電流領
域で急激にオン抵抗が増大してしまうことは避けられな
い。但し部分的には、順バイアス時にpn接合が順バイ
アスされ、少数キャリアの注入が起きて、少数キャリア
の注入が起き、スイッチング速度を長くする。
However, as shown in equation (1),
Since it is essentially a Schottky diode, there is no injection of minority carriers as in a pn diode, and it is inevitable that the on-resistance rapidly increases in a large current region. However, the pn junction is partially biased at the time of forward bias, minority carrier injection occurs, and minority carrier injection occurs, thereby increasing the switching speed.

【0017】以上の問題に鑑み本発明の目的は、オン抵
抗が低く、pn接合が順バイアスされず、高速スイッチ
ングが可能な超接合型のショットキーダイオードを提供
することにある。
In view of the above problems, an object of the present invention is to provide a super-junction type Schottky diode which has a low on-resistance, does not have a forward biased pn junction, and can perform high-speed switching.

【0018】[0018]

【課題を解決するための手段】上記課題の解決のため本
発明は、第一と第二の主面を有する第一電導型半導体層
と、一方の主面に設けられたショットキーバリア電極
と、他方の主面にオーミック接触したカソード電極と、
第一と第二の主面間に、第一電導型ドリフト領域と第二
電導型仕切り領域とを交互に配置した並列pn層とを備
える超接合ショットキーダイオードにおいて、前記ショ
ットキー電極と第二電導型仕切り領域との間に第一電導
型ドリフト領域より高比抵抗の第一電導型高抵抗領域を
有するものとする。
In order to solve the above problems, the present invention provides a first conductive semiconductor layer having first and second main surfaces, a Schottky barrier electrode provided on one of the main surfaces, and A cathode electrode in ohmic contact with the other main surface,
A super-junction Schottky diode including a parallel pn layer in which first conductive type drift regions and second conductive type partition regions are alternately arranged between first and second main surfaces, wherein the Schottky electrode and the second It is assumed that a first conductive high resistance region having a higher specific resistance than the first conductive drift region is provided between the conductive region and the conductive partition region.

【0019】第一電導型高抵抗領域の存在によりpn接
合が順バイアスされることがないので、少数キャリアの
注入がなく、高速スイッチングが可能である。特に、第
一電導型高抵抗領域の不純物濃度は1×1013〜1×1
15cm-3の範囲にあるものとする。第一電導型高抵抗領
域の不純物濃度が低すぎると、抵抗分が増す。逆に高す
ぎると、逆バイアス時の漏れ電流が増す。また第一電導
型高抵抗領域の不純物濃度はショットキーバリアの高さ
にも影響するので、適正な濃度でなければならない。
Since the pn junction is not forward-biased due to the presence of the first conductive high resistance region, minority carriers are not injected and high-speed switching is possible. In particular, the impurity concentration of the first conductive high resistance region is 1 × 10 13 to 1 × 1.
It should be in the range of 0 15 cm -3 . If the impurity concentration of the first conductive high-resistance region is too low, the resistance increases. Conversely, if it is too high, the leakage current at the time of reverse bias increases. Further, the impurity concentration of the first conductivity type high resistance region also affects the height of the Schottky barrier, so that it must be an appropriate concentration.

【0020】ショットキー電極と第二電導型仕切り領域
とが、第二導電型仕切り領域より高比抵抗の第二導電型
高抵抗領域によって少なくとも一部で電気的に接続して
いる超接合ショットキーダイオードにおいても同様であ
る。その場合は、第二電導型高抵抗領域の不純物量が1
×1012〜1×1014cm-2の範囲にあるもるのとする。
A super junction Schottky in which the Schottky electrode and the second conductive type partition region are at least partially electrically connected by the second conductive type high resistance region having a higher specific resistance than the second conductive type partition region. The same applies to diodes. In this case, the impurity amount of the second conductive type high resistance region is 1
It is assumed that it is in the range of × 10 12 to 1 × 10 14 cm -2 .

【0021】第二電導型仕切り領域と接続された第二導
電型高抵抗領域の存在により、第二導電型仕切り領域に
ショットキー電極の電位が有効に伝達される。但し、第
二電導型高抵抗領域の不純物濃度が低すぎると抵抗分が
増し、第二電導型仕切り領域の電位制御が不十分とな
る。逆に高すぎると、順バイアス時に少数キャリアの注
入を促進し、スイッチング速度を長くする。
The presence of the second conductive type high resistance region connected to the second conductive type partition region allows the potential of the Schottky electrode to be effectively transmitted to the second conductive type partition region. However, if the impurity concentration of the second conductive high resistance region is too low, the resistance increases, and the potential control of the second conductive partition region becomes insufficient. On the other hand, if it is too high, the injection of minority carriers is promoted during forward bias, and the switching speed is increased.

【0022】さらに、第二導電型仕切り領域が電気的に
互いに接続しているとよい。そのような超接合ショット
キーダイオードでは、ショットキー電極の電位が有効に
伝達され、第二導電型仕切り領域の電位が均一になる。
更に、半導体が炭化珪素であるものとすれば、シリコン
半導体素子の範囲を越えた高耐圧、高温用のショットキ
ーダイオードとすることができる。
Further, it is preferable that the second conductivity type partition regions are electrically connected to each other. In such a super junction Schottky diode, the potential of the Schottky electrode is effectively transmitted, and the potential of the second conductivity type partition region becomes uniform.
Further, if the semiconductor is silicon carbide, a Schottky diode having a high breakdown voltage and a high temperature exceeding the range of the silicon semiconductor element can be obtained.

【0023】[0023]

【発明の実施の形態】[実施例1]図1は、本発明を適
用した超接合ショットキーダイオードの第一の例の断面
図である。4は低抵抗のn+ カソード層、15はnドリ
フト領域9とp仕切り領域10とからなる並列pn層で
ある。並列pn層15の上にはn- 高抵抗層11があ
り、その表面にショットキーバリアを形成するショット
キー電極7が設けられている。n+ カソード層4の裏面
にはカソード電極5が設けられている。この例では並列
pn層15とn+ カソード層との間にもn- 高抵抗層1
6があるが、これを設けない場合もある。ショットキー
電極7は例えばチタン(Ti)である。
FIG. 1 is a sectional view of a first embodiment of a super junction Schottky diode to which the present invention is applied. 4 is a low resistance n + cathode layer, and 15 is a parallel pn layer comprising an n drift region 9 and a p partition region 10. The n high resistance layer 11 is provided on the parallel pn layer 15, and a Schottky electrode 7 for forming a Schottky barrier is provided on the surface thereof. A cathode electrode 5 is provided on the back surface of the n + cathode layer 4. In this example, the n high resistance layer 1 is also provided between the parallel pn layer 15 and the n + cathode layer.
There are cases in which there is no such number. The Schottky electrode 7 is, for example, titanium (Ti).

【0024】図2(a)は、図1の超接合ショットキー
ダイオードの並列pn層のパターンを上から見た透視平
面図である。この例では、p仕切り領域10が柱状なの
でpコラムと称する。上から見るとセル状となってい
る。たとえば1000V 耐圧のデバイスの場合には、p
コラム10の幅d=5μm 、この時の不純物濃度と並列
pn層12の厚さは、それぞれ5×1015cm-3、60μ
m とする。nドリフト領域9の幅が同じときは面積が3
倍になるので、不純物濃度を1/3とすれば良い。ショ
ットキー金属7と接触するn- 高抵抗層11は、基板内
の並列pn層15を形成するnドリフト領域9よりも低
濃度の方が望ましい。これは表面近傍で電界を平坦にし
て、電界集中によるリーク電流の発生を防止するためで
ある。具体的には1×1013〜1×1015cm-3程度とす
る。厚さは0.5〜10μm とする。
FIG. 2A is a perspective plan view of the pattern of the parallel pn layer of the super junction Schottky diode of FIG. 1 as viewed from above. In this example, since the p-partition region 10 is columnar, it is called a p-column. Seen from above, it is cellular. For example, for a device with a withstand voltage of 1000 V, p
The width d of the column 10 is 5 μm. At this time, the impurity concentration and the thickness of the parallel pn layer 12 are 5 × 10 15 cm −3 and 60 μm, respectively.
m. When the width of the n drift region 9 is the same, the area is 3
Therefore, the impurity concentration may be reduced to 1/3. It is preferable that the n high resistance layer 11 in contact with the Schottky metal 7 has a lower concentration than the n drift region 9 forming the parallel pn layer 15 in the substrate. This is to flatten the electric field in the vicinity of the surface to prevent generation of a leak current due to electric field concentration. Specifically, it is about 1 × 10 13 to 1 × 10 15 cm −3 . The thickness is 0.5 to 10 μm.

【0025】他の例としては、図2(b)に示したよう
な千鳥格子状、図2(c)に示したようなストライプ状
も考えることができる。これらの場合はnドリフト領域
9とp仕切り領域10の不純物濃度を等しくする。図8
の従来の超接合ショットキーダイオードでは、pコラム
10がショットキー電極7に短絡されていたが、本実施
例の超接合ショットキーダイオードでは、これを短絡し
ない。すなわちpコラム10とショットキー電極1との
間に、n-高抵抗層11が残されている点が違ってい
る。
As other examples, a houndstooth check pattern as shown in FIG. 2B and a stripe pattern as shown in FIG. 2C can be considered. In these cases, the impurity concentrations of the n drift region 9 and the p partition region 10 are made equal. FIG.
In the conventional super-junction Schottky diode described above, the p column 10 is short-circuited to the Schottky electrode 7, but in the super-junction Schottky diode of the present embodiment, this is not short-circuited. That is, the difference is that n high resistance layer 11 is left between p column 10 and Schottky electrode 1.

【0026】このようにしてテバイスを構成すると、順
バイアスにおいては、超接合構造特有の非常に低いオン
抵抗を実現できるとともに、従来の超接合ショットキー
ダイオードのようなp領域からの少数キャリアの注入を
伴わない。そのため図 の従来の超接合ショットキーダ
イオードに比し、逆回復時間が1/10以下になり、高
速スイッチングを実現できる。
When the device is configured in this manner, in the forward bias, a very low on-resistance unique to the super junction structure can be realized, and the injection of minority carriers from the p region such as the conventional super junction Schottky diode can be realized. Is not accompanied. Therefore, the reverse recovery time is 1/10 or less as compared with the conventional super junction Schottky diode shown in the figure, and high-speed switching can be realized.

【0027】図3は、本発明の超接合ショットキーダイ
オードに逆バイアスを印加した時の空空乏層の広がりを
示した図である。逆バイアスを印加すると、空乏層12
がショットキー電極7からn- 高抵抗層11へ広がって
行き、pコラム10に到達するとその電位は並列pn層
15全体へと広がり、図3のような空乏層の広がりとな
る。このことによってpコラム10がショットキー電極
7に接触していなくても十分な耐圧を維持することがで
きる。表面から超接合構造のpコラム10までの深さは
耐圧と密接な関係にあり、耐圧毎に設計を必要とする
が、0.5〜5μm 程度である。
FIG. 3 is a diagram showing the spread of the depletion layer when a reverse bias is applied to the super junction Schottky diode of the present invention. When a reverse bias is applied, the depletion layer 12
Spreads from the Schottky electrode 7 to the n high resistance layer 11 and reaches the p column 10, the potential spreads to the entire parallel pn layer 15, and the depletion layer spreads as shown in FIG. Thus, sufficient breakdown voltage can be maintained even when p column 10 is not in contact with Schottky electrode 7. The depth from the surface to the p-column 10 of the super-junction structure has a close relationship with the withstand voltage and requires a design for each withstand voltage, but is about 0.5 to 5 μm.

【0028】なお、ショットキー電極7の周辺部分には
従来のダイオードと同様のガードリング6を設けたが、
フィールドプレートなど従来使用されている他の耐圧構
造とすることもできる。さらに、図1では、ショットキ
ー電極7の下方の電流が流れる活性部分にのみ並列pn
層15を設けているが、周辺の耐圧構造部分まで延長し
ても構わない。ショットキー電極としては他に、通常使
用されているAl、Mo、Niなどが使用可能である。
A guard ring 6 similar to that of a conventional diode is provided around the Schottky electrode 7.
Other pressure-resistant structures conventionally used, such as a field plate, can also be used. Further, in FIG. 1, parallel pn is provided only in the active portion where the current below Schottky electrode 7 flows.
Although the layer 15 is provided, it may be extended to the peripheral withstand voltage structure. As the Schottky electrode, other commonly used Al, Mo, Ni, etc. can be used.

【0029】[実施例2]図4は、本発明を実施した第
二の実施例の断面図である。図1の実施例1との違い
は、pコラム10とショットキー電極1との間に部分的
に高抵抗のp高抵抗領域13が付加されて、基板内のp
コラム10の一部と接続されている点である。
[Embodiment 2] FIG. 4 is a sectional view of a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that a p-high resistance region 13 having a high resistance is partially added between the p column 10 and the Schottky electrode 1 so that the p
This is a point connected to a part of the column 10.

【0030】このp高抵抗領域13はpコラム10の電
位を均等にする効果をもつので、ある程度高不純物濃度
の方が良いが、逆に不純物濃度が高過ぎると少数キャリ
アの注入を引き起こすので、余り高濃度にすることも出
来ない。従ってp高抵抗領域13の不純物総量は1×1
12〜1×1014cm-3程度とするのがよい。p高抵抗領
域13はまた、pn接合で発生したアバランシェ電流を
逃がす効果もあり、接合に耐量が必要な場合に有効であ
る。
Since the p-high resistance region 13 has an effect of equalizing the potential of the p column 10, it is better to have a high impurity concentration to some extent. Conversely, if the impurity concentration is too high, minority carriers are injected. It is not possible to make the concentration too high. Therefore, the total amount of impurities in the p high resistance region 13 is 1 × 1
It is preferable to be about 0 12 to 1 × 10 14 cm −3 . The p-high resistance region 13 also has an effect of releasing an avalanche current generated at the pn junction, and is effective when the junction requires a large amount of resistance.

【0031】更に、pコラム10の間で電圧の印加や電
流分担を均一にするために、部分的にpコラム10をつ
なぐためのp接続領域14を設けても良い。 [実施例3]以上の実施例は、半導体材料としてシリコ
ンの場合を述べた。しかしながら、近年炭化珪素でパワ
ー素子を形成すると、著しく特性が良好になることが指
摘されている。
Further, in order to make voltage application and current sharing uniform among the p columns 10, a p connection region 14 for partially connecting the p columns 10 may be provided. [Embodiment 3] In the above embodiments, the case where silicon is used as the semiconductor material has been described. However, in recent years, it has been pointed out that when a power element is formed of silicon carbide, characteristics are significantly improved.

【0032】本発明においても炭化珪素に適用すること
によって、シリコンよりも高性能のデバイスを実現可能
である。特に、炭化珪素に応用した場合には、pコラ
ム、およびnドリフト領域の濃度が高く設定できるため
に、より高温で使用可能となる。また,炭化珪素の結晶
成長では制御できる不純物濃度が1×1015cm-3程度で
あり、この濃度では、耐圧が5kV程度となってしまう。
しかし、超接合構造を使用することで、pコラムおよび
nドリフト領域の濃度を一桁以上あげることが可能とな
ることから、高耐圧でありながらオン抵抗が低く、スイ
ッチング速度の速いショットキーダイオードとすること
ができる。
By applying the present invention to silicon carbide, a device having higher performance than silicon can be realized. In particular, when applied to silicon carbide, since the concentration of the p column and the n drift region can be set high, it can be used at a higher temperature. Further, in the crystal growth of silicon carbide, the impurity concentration that can be controlled is about 1 × 10 15 cm −3 , and with this concentration, the breakdown voltage is about 5 kV.
However, by using a super junction structure, the concentration of the p column and the n drift region can be increased by one digit or more. can do.

【0033】[0033]

【発明の効果】以上説明したように本発明によれば、シ
ョットキー電極と第二電導型仕切り領域との間に第一電
導型ドリフト領域より実質的に高比抵抗の第一電導型高
抵抗領域を設けることによって、スイッチング速度の早
い超接合ショットキーダイオードとすることができた。
勿論超接合半導体素子であるから、通常のショットキー
ダイオードに比べオン抵抗が格段に低い。従って、オン
損失、スイッチング損失ともに低いショットキーダイオ
ードが実現できたことになる。
As described above, according to the present invention, the first conductive type high resistance having substantially higher specific resistance than the first conductive type drift region between the Schottky electrode and the second conductive type partition region. By providing the region, a super-junction Schottky diode with a high switching speed could be obtained.
Of course, since it is a super-junction semiconductor element, the on-resistance is much lower than that of a normal Schottky diode. Therefore, a Schottky diode having low on-loss and switching loss can be realized.

【0034】さらに、第二電導型仕切り領域と接続され
る第二電導型高抵抗領域や、第二電導型仕切り領域を結
ぶ接続領域を設けることによって、第二電導型仕切り領
域の電位が安定化され、局部的な電流集中による破壊が
回避でき、信頼性の高いショットキーダイオードが実現
できた。
Further, by providing a second conductive type high resistance region connected to the second conductive type partition region and a connection region connecting the second conductive type partition region, the potential of the second conductive type partition region is stabilized. As a result, destruction due to local current concentration can be avoided, and a highly reliable Schottky diode can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明実施例1の超接合ショットキーダイオー
ドの断面図
FIG. 1 is a cross-sectional view of a super junction Schottky diode according to a first embodiment of the present invention.

【図2】(a)は実施例1の超接合ショットキーダイオ
ードの並列pn層部分の水平断面図、(b)、(c)は
別の超接合ショットキーダイオードの並列pn層部分の
水平断面図
FIG. 2A is a horizontal sectional view of a parallel pn layer portion of a super junction Schottky diode of Example 1, and FIGS. 2B and 2C are horizontal sectional views of a parallel pn layer portion of another super junction Schottky diode. Figure

【図3】本発明実施例1の超接合ショットキーダイオー
ドの逆電圧印加時の空乏層を示す断面図
FIG. 3 is a sectional view showing a depletion layer when a reverse voltage is applied to the super junction Schottky diode according to the first embodiment of the present invention.

【図4】本発明実施例2の超接合ショットキーダイオー
ドの断面図
FIG. 4 is a sectional view of a super junction Schottky diode according to a second embodiment of the present invention.

【図5】(a)はpnダイオードの断面図、(b)はシ
ョットキーダイオードの断面図、(c)は融合型ダイオ
ードの断面図
5A is a sectional view of a pn diode, FIG. 5B is a sectional view of a Schottky diode, and FIG. 5C is a sectional view of a fusion diode.

【図6】ダイオードの順方向電流−電圧特性図FIG. 6 is a forward current-voltage characteristic diagram of a diode.

【図7】従来の超接合ショットキーダイオードの断面図FIG. 7 is a cross-sectional view of a conventional super junction Schottky diode.

【符号の説明】[Explanation of symbols]

1 アノード電極 2 pアノード領域 3 nドリフト層 4 n+ カソード領域 5 カソード電極 6 ガードリング 7 ショットキー電極 8 注入用p領域 9 nドリフト領域 10 pドリフト領域またはpコラム 11 n- 高抵抗領域 12 空乏層 13 p高抵抗領域 14 p接続領域 15 並列pn層 16 n- 高抵抗領域1 anode 2 p anode region 3 n drift layer 4 n + cathode region 5 the cathode electrode 6 guard ring 7 Schottky electrode 8 implanted for the p region 9 n drift region 10 p drift region or p columns 11 n - high resistance region 12 depleted layer 13 p high resistance region 14 p connection region 15 parallel pn layer 16 n - high resistance region

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】第一と第二の主面を有する第一電導型半導
体層と、一方の主面に設けられたショットキー電極と、
他方の主面にオーミック接触したカソード電極と、第一
と第二の主面間に、第一電導型ドリフト領域と第二電導
型仕切り領域とを交互に配置した並列pn層とを備える
超接合ショットキーダイオードにおいて、前記ショット
キー電極と第二電導型仕切り領域との間に第一電導型ド
リフト領域より実質的に高比抵抗の第一電導型高抵抗領
域を有することを特徴とする超接合ショットキーダイオ
ード
A first conductive semiconductor layer having first and second main surfaces; a Schottky electrode provided on one of the main surfaces;
Super junction comprising a cathode electrode in ohmic contact with the other main surface, and a parallel pn layer between the first and second main surfaces, in which first conductive type drift regions and second conductive type partition regions are alternately arranged. In the Schottky diode, a superconductive junction having a first conductive high resistance region having a resistivity substantially higher than that of the first conductive drift region between the Schottky electrode and the second conductive partition region. Schottky diode
【請求項2】第一電導型高抵抗領域の不純物濃度が1×
1013〜1×1015cm-3の範囲にあることを特徴とする
請求項1に記載の超接合ショットキーダイオード。
2. The method according to claim 1, wherein the impurity concentration of the first conductive high resistance region is 1 ×.
2. The super-junction Schottky diode according to claim 1, wherein the Schottky diode is in a range of 10 < 13 > to 1 * 10 < 15 > cm < -3 >.
【請求項3】第一と第二の主面を有する第一電導型半導
体層と、一方の主面に設けられたショットキー電極と、
他方の主面にオーミック接触したカソード電極と、第一
と第二の主面間に、第一電導型ドリフト領域と第二電導
型仕切り領域とを交互に配置した並列pn層とを備える
超接合ショットキーダイオードにおいて、前記ショット
キー電極と第二電導型仕切り領域とが、第二導電型仕切
り領域より実質的に高比抵抗の第二導電型高抵抗領域に
よって少なくとも一部で電気的に接続していることを特
徴とする超接合ショットキーダイオード。
A first conductive semiconductor layer having first and second main surfaces; a Schottky electrode provided on one of the main surfaces;
Super junction comprising a cathode electrode in ohmic contact with the other main surface, and a parallel pn layer between the first and second main surfaces, in which first conductive type drift regions and second conductive type partition regions are alternately arranged. In the Schottky diode, the Schottky electrode and the second conductive type partition region are electrically connected at least in part by a second conductive type high resistance region having substantially higher specific resistance than the second conductive type partition region. A super junction Schottky diode, characterized in that:
【請求項4】第二電導型高抵抗領域の不純物量が1×1
12〜1×1014cm -2の範囲にあることを特徴とする請
求項3に記載の超接合ショットキーダイオード。
4. The method according to claim 1, wherein the amount of impurities in the second conductive high resistance region is 1 × 1.
012~ 1 × 1014cm -2The contract is characterized by being in the range of
The super-junction Schottky diode according to claim 3.
【請求項5】第二導電型仕切り領域を互いに電気的に接
続する接続領域を有することを特徴とする請求項1ない
し5のいずれかに記載の超接合ショットキーダイオー
ド。
5. The super-junction Schottky diode according to claim 1, further comprising a connection region for electrically connecting the second conductivity type partition regions to each other.
【請求項6】半導体が炭化珪素であることを特徴とする
請求項1ないし5のいずれかに記載の超接合ショットキ
ーダイオード。
6. The super-junction Schottky diode according to claim 1, wherein the semiconductor is silicon carbide.
JP2000268460A 2000-09-05 2000-09-05 Superjunction Schottky diode Expired - Fee Related JP4770009B2 (en)

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Country Link
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008014894A1 (en) 2007-04-03 2008-10-09 Denso Corp., Kariya-shi Schottky barrier diode semiconductor device and method of making the same
US7928470B2 (en) 2005-11-25 2011-04-19 Denso Corporation Semiconductor device having super junction MOS transistor and method for manufacturing the same
WO2012090861A1 (en) * 2010-12-28 2012-07-05 三菱電機株式会社 Semiconductor device
JP2012142590A (en) * 2005-12-27 2012-07-26 Qspeed Semiconductor Inc Ultrafast recovery diode
CN104393055A (en) * 2014-11-10 2015-03-04 电子科技大学 Grooved diode with floating island structure
US9728654B2 (en) 2013-06-05 2017-08-08 Rohm Co., Ltd. Semiconductor device and method of manufacturing same
US20170256657A1 (en) * 2016-03-01 2017-09-07 Toyoda Gosei Co., Ltd. Mps diode
WO2019073776A1 (en) * 2017-10-11 2019-04-18 株式会社デンソー Silicon carbide semiconductor device equipped with schottky barrier diode and production method therefor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320774A (en) * 1976-08-09 1978-02-25 Philips Nv Semiconductor device
JP2000040822A (en) * 1998-07-24 2000-02-08 Fuji Electric Co Ltd Superjunction semiconductor element and its manufacture
JP2000208527A (en) * 1999-01-11 2000-07-28 Fuji Electric Co Ltd Manufacture of super-joint semiconductor element and the super-joint semiconductor element
JP2000294805A (en) * 1999-04-09 2000-10-20 Matsushita Electronics Industry Corp Schottky barrier diode and its manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320774A (en) * 1976-08-09 1978-02-25 Philips Nv Semiconductor device
JP2000040822A (en) * 1998-07-24 2000-02-08 Fuji Electric Co Ltd Superjunction semiconductor element and its manufacture
JP2000208527A (en) * 1999-01-11 2000-07-28 Fuji Electric Co Ltd Manufacture of super-joint semiconductor element and the super-joint semiconductor element
JP2000294805A (en) * 1999-04-09 2000-10-20 Matsushita Electronics Industry Corp Schottky barrier diode and its manufacture

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DE102008014894A1 (en) 2007-04-03 2008-10-09 Denso Corp., Kariya-shi Schottky barrier diode semiconductor device and method of making the same
DE112011104631B4 (en) 2010-12-28 2020-06-04 Mitsubishi Electric Corp. Semiconductor device
WO2012090861A1 (en) * 2010-12-28 2012-07-05 三菱電機株式会社 Semiconductor device
CN103443925A (en) * 2010-12-28 2013-12-11 三菱电机株式会社 Semiconductor device
JP5474218B2 (en) * 2010-12-28 2014-04-16 三菱電機株式会社 Semiconductor device
US8963276B2 (en) 2010-12-28 2015-02-24 Mitsubishi Electric Corporation Semiconductor device including a cell array having first cells and second cells interspersed around the arrangement of the first cells
US9728654B2 (en) 2013-06-05 2017-08-08 Rohm Co., Ltd. Semiconductor device and method of manufacturing same
CN104393055A (en) * 2014-11-10 2015-03-04 电子科技大学 Grooved diode with floating island structure
US10026851B2 (en) * 2016-03-01 2018-07-17 Toyoda Gosei Co., Ltd. MPS diode
US20170256657A1 (en) * 2016-03-01 2017-09-07 Toyoda Gosei Co., Ltd. Mps diode
WO2019073776A1 (en) * 2017-10-11 2019-04-18 株式会社デンソー Silicon carbide semiconductor device equipped with schottky barrier diode and production method therefor
JP2019071394A (en) * 2017-10-11 2019-05-09 株式会社デンソー Silicon carbide semiconductor device with schottky barrier diode and manufacturing method of the same
JP7098906B2 (en) 2017-10-11 2022-07-12 株式会社デンソー Silicon carbide semiconductor device equipped with Schottky barrier diode and its manufacturing method

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