JP2009016618A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has high withstand voltage and can be manufactured at low cost, and a manufacturing method thereof. <P>SOLUTION: The semiconductor device 100 has a structure in which a trench insulting gate transistor 30 is formed on the inside of a semiconductor substrate 20, a LOCOS oxide film 40 is formed on the outside semiconductor substrate 20 so as to be separated from an outermost trench insulating gate TG1, a second conductivity-type semiconductor region 50 is formed from the lower part of the outermost trench insulating gate TG1 to the lower part of the LOCOS oxide film 40, the second conductivity-type semiconductor region 50 consists of a first concentration region 51 for covering a corner portion TG1c from the lower part of the outermost trench insulating gate TG1 and a second concentration region 52 for covering the lower part of the LOCOS oxide film 40, the second concentration region 52 has an impurity concentration set lower than the impurity concentration of the first concentration region 51, and the second concentration region 52 has a diffusion depth set shallower than the diffusion depth of the first concentration region 51. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of a semiconductor substrate, and a method for manufacturing the same.

  Japanese Laid-Open Patent Publication No. 6-45612 (Patent Document 1) discloses a semiconductor device in which a vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of a semiconductor substrate.

  13A and 13B are semiconductor devices disclosed in Patent Document 1, and are schematic cross-sectional views of the semiconductor devices 91 and 92, respectively.

In semiconductor devices 91 and 92 shown in FIGS. 13A and 13B, a trench MOS gate structure IGBT (vertical trench insulated gate transistor) is formed as an assembly of cells on the inner portion of the semiconductor substrate 1. This is a semiconductor device. As shown in the figure, P + An N epitaxial layer 2 is formed on the surface of the substrate 1, and an N− epitaxial layer 3 is formed on the N epitaxial layer 2. On the N-epitaxial layer 3, a plurality of P well regions 4 and a plurality of P well regions 4 and a plurality of trench isolation layers (trench insulating gates) 10 made of gate polysilicon 7 and oxide films 7 formed around the gate polysilicon 7 are formed. P well regions 41 and 42 are formed. These trench isolation layers 10 are regularly formed at predetermined intervals, and the formation depths are also set to the same level. N + emitter regions 5 are formed on the surfaces of the P well regions 4 and 41 and 42, respectively. An emitter electrode 8 is formed on the entire surface of the P well regions 4 and 41 including the N + emitter region 5 and the trench isolation layer 10, and a collector electrode 9 is formed on the back surface of the P + substrate 1.

In the semiconductor device 91 of FIG. 13A, the formation depth of the outermost P well region 41 formed adjacent to the outermost trench isolation layer 10A is the same as the formation depth of the trench isolation layer 10. Thus, the depth is set deeper than the formation depth of the P well region 4 which is a P well region other than the outermost P well region 41. In the semiconductor device 92 of FIG. 13B, the outermost P well region 42 is formed with a predetermined depth so as to cover the outermost trench isolation layer 10A. In addition, the P well region 42 is formed at a predetermined depth in the region from the outermost trench isolation layer 10A to the outside direction (the region side where the trench isolation layer 10 is not formed). The trench isolation layer 10 is formed deeper than the formation depth. In the semiconductor devices 91 and 92 shown in FIGS. 13A and 13B, the outermost P well regions 41 and 42 are formed deeper than the other P well regions 4, thereby forming the outermost trench isolation layer 10 </ b> A. The electric field concentration in the region near the bottom edge can be relaxed and the breakdown voltage can be improved.
JP-A-6-45612

  Patent Document 1 shows that in the semiconductor devices 91 and 92 of FIGS. 13A and 13B, the electric field concentration in the region near the bottom edge of the outermost trench isolation layer 10A can be relaxed, thereby improving the breakdown voltage. Has been. However, Patent Document 1 does not consider other portions that affect the breakdown voltage (for example, the end portion of the substrate 1 at the right end of the figure). Further, in order to form the outermost P-well regions 41 and 42 deeper than the other P-well regions 4, these need to be formed in a separate process, which causes an increase in cost.

  Accordingly, the present invention provides a semiconductor device in which a vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of a semiconductor substrate, and a method for manufacturing the semiconductor device, which has a high breakdown voltage and is inexpensively manufactured. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

  According to the first aspect of the present invention, a vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of the first conductivity type semiconductor substrate, and a LOCOS oxide film surrounds the assembly of cells. Separated from the outer peripheral trench insulating gate, formed on the first conductive type semiconductor substrate outside the outermost peripheral trench insulating gate, and a second conductive type semiconductor region is formed from the lower portion of the outermost peripheral trench insulating gate from the LOCOS oxidation gate. A first concentration region formed on a surface layer portion of the first conductivity type semiconductor substrate over a lower portion of the film, wherein the second conductivity type semiconductor region covers a corner portion from a lower portion of the outermost trench insulating gate; And a second concentration region covering a lower portion of the LOCOS oxide film, wherein the impurity concentration of the second concentration region is set lower than the impurity concentration of the first concentration region, and the second concentration Diffusion depth of pass has been characterized by comprising set shallower than the diffusion depth of the first doped region.

  In the semiconductor device, a second conductivity type semiconductor region is formed from the lower part of the outermost trench insulating gate to the lower part of the LOCOS oxide film, and the first concentration region of the second conductivity type semiconductor region causes the The corners are covered from the lower part of the outermost trench insulating gate. Therefore, in the semiconductor device, the electric field concentration in the vicinity of the corner of the outermost peripheral trench insulating gate is alleviated, thereby improving the breakdown voltage. The second concentration region of the second conductivity type semiconductor region covering the lower portion of the LOCOS oxide film disposed separately from the outermost trench insulating gate is the first concentration covering the corner of the outermost trench insulating gate. The impurity concentration is set lower than that in the region. For this reason, the depletion layer is easily spread around the second concentration region as compared with the first concentration region. By utilizing this, in the semiconductor device, the breakdown voltage of the outer part of the outermost peripheral trench insulating gate can be set higher than that of the inner part (cell forming part).

  In the semiconductor device, the diffusion depth of the second concentration region is shallower than the diffusion depth of the first concentration region, and the impurity concentration of the second concentration region is compared with the impurity concentration of the first concentration region. Is set low. Since the structure including the first concentration region and the second concentration region having different impurity concentrations and diffusion depths can be formed in one step by a manufacturing method described later, the semiconductor device is made an inexpensive semiconductor device. Can do.

  As described above, the semiconductor device is a semiconductor device in which a vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of a semiconductor substrate, and has a high breakdown voltage and is inexpensive. It is a semiconductor device that can be manufactured.

  In the semiconductor device, as described in claim 2, the impurity concentration of the second concentration region is suitably set corresponding to the first conductivity type semiconductor substrate, and the first concentration region is formed below the LOCOS oxide film. It is preferable that a so-called RESURF (Reduced Surface Electric Field) structure is constituted by the one-conductivity-type semiconductor substrate and the second concentration region. As a result, when the reverse voltage is applied, the first conductive semiconductor substrate and the second concentration region below the LOCOS oxide film are completely depleted within a predetermined range, whereby the breakdown voltage of the semiconductor device can be further increased.

  In the semiconductor device, as described in claim 3, a shortest distance from a corner portion of the outermost peripheral trench insulating gate to a boundary surface between the first concentration region and the second concentration region is equal to that of the first concentration region. It is preferable that the depth is set larger than the diffusion depth.

  According to this, the second concentration region in the second conductivity type semiconductor region is sufficiently separated from the corner portion of the outermost peripheral trench insulating gate, and the corner portion is sufficiently covered with the first concentration region having a high impurity concentration. Become. For this reason, in the state which excluded the influence of the 2nd concentration area | region with low impurity concentration, the relaxation effect of the electric field concentration in the corner | angular part vicinity of the outermost periphery trench insulated gate by the 1st concentration area | region mentioned above can be exhibited.

  A fourth aspect of the present invention relates to a method for manufacturing the semiconductor device.

  According to a fourth aspect of the present invention, a vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of the first conductivity type semiconductor substrate, and a LOCOS oxide film surrounds the assembly of cells. Separated from the outer peripheral trench insulating gate, formed on the first conductive type semiconductor substrate outside the outermost peripheral trench insulating gate, and a second conductive type semiconductor region is formed from the lower portion of the outermost peripheral trench insulating gate from the LOCOS oxidation gate. A first concentration region formed on a surface layer portion of the first conductivity type semiconductor substrate over a lower portion of the film, wherein the second conductivity type semiconductor region covers a corner portion from a lower portion of the outermost trench insulating gate; And a second concentration region covering a lower portion of the LOCOS oxide film, wherein the impurity concentration of the second concentration region is set lower than the impurity concentration of the first concentration region, and the second concentration A method for manufacturing a semiconductor device, wherein a diffusion depth of a region is set to be shallower than a diffusion depth of the first concentration region, wherein the second conductivity type semiconductor region is formed in the first conductivity type semiconductor substrate. , An ion implantation step of ion-implanting a second conductivity type impurity; a LOCOS oxide film formation step for forming the LOCOS oxide film after the ion implantation step; and a second conductivity after the ion implantation after the LOCOS oxide film formation step. And a thermal diffusion step of forming a second conductivity type semiconductor region composed of the first concentration region and the second concentration region by thermally diffusing the type impurities.

  In the semiconductor device manufacturing method, ions are implanted into a region where the second conductivity type semiconductor region is to be formed, then a LOCOS oxide film is formed, and then the ion implanted second conductivity type impurities are thermally diffused. After the ion implantation, the ion implantation layer of the second conductivity type impurity is formed near the extremely shallow surface of the first conductivity type semiconductor substrate from the region where the outermost trench insulating gate is to be formed to the region where the LOCOS oxide film is to be formed. Is formed. The ion implantation layer formed near the surface of the first conductivity type semiconductor substrate is divided into two regions having different concentration distributions after the next LOCOS oxide film formation. That is, the second conductivity type impurity is taken into the LOCOS oxide film from the ion implantation layer when the LOCOS oxide film is formed. For this reason, in the lower region of the LOCOS oxide film, the second conductivity type impurity is reduced to form an ion implantation region having a low concentration, and in the region where the outermost trench insulating gate is not formed, the second conductivity type impurity is formed. There is no change in the amount of type impurities, and the state during ion implantation is maintained, so that an ion implantation region having a high concentration is obtained. As a result, in the next thermal diffusion step, a first concentration region having a high impurity concentration and a deep diffusion depth is formed in the region where the outermost trench insulating gate is to be formed, and the impurity concentration is low below the LOCOS oxide film. Thus, the second concentration region having a shallow diffusion depth is formed.

  In the formation of the second conductivity type semiconductor region described above, the first concentration region and the second concentration region are formed in one step even though the impurity concentration and the diffusion depth of the first concentration region and the second concentration region are different. It is possible. Therefore, the semiconductor device can be manufactured at a lower cost than when the first concentration region and the second concentration region having different impurity concentrations and diffusion depths are formed in separate steps.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 as an example of the semiconductor device of the present invention. FIG. 2 is a diagram showing a dimensional relationship of main parts of the semiconductor device 100 of FIG.

  In the semiconductor device 100 shown in FIG. 1, a vertical trench insulated gate transistor 30 includes an N-type N (N−) layer 21 and a second N-type (N +) layer 22 as an aggregate of cells. It is formed in the inner part of the conductive semiconductor substrate 20. The trench insulated gate transistor 30 has a trench insulated gate TG made of a sidewall oxide film 31 and polycrystalline silicon 32, and is a vertical MOS transistor in which carriers flow in the vertical direction of the N-conductivity type semiconductor substrate 20. . The second N conductivity type (N +) layer 22 on the back surface side of the N conductivity type semiconductor substrate 20 functions as a drain region of the trench insulated gate transistor 30, and the first N conductivity type (N−) layer 21 serves as a carrier drift region. Function. Note that the reference numeral 33 represents a source region of the trench insulated gate transistor 30, and the reference numeral 34 represents a channel formation region. The portion 35 at the end of the N conductivity type semiconductor substrate 20 is an N conductivity type (N +) region formed simultaneously with the source region 33 on the main surface side, and the second N conductivity type (N +) layer 22 on the back surface side. Connected. Reference numeral 23 denotes an interlayer insulating film, and reference numeral 24 denotes an aluminum (Al) electrode layer.

  In the semiconductor device 100 of FIG. 1, the LOCOS oxide film 40 is separated from the outermost trench insulating gate TG1 surrounding the aggregate of cells of the trench insulated gate transistor 30, and the N conductivity outside the outermost trench insulating gate TG1. It is formed on the type semiconductor substrate 20. Further, the P conductivity type semiconductor region 50 is formed in the surface layer portion of the N conductivity type semiconductor substrate 20 from the lower part of the outermost peripheral trench insulating gate TG1 to the lower part of the LOCOS oxide film 40. The P conductivity type semiconductor region 50 includes a first concentration (P) region 51 covering the corner portion TG1c from the lower part of the outermost peripheral trench insulating gate TG1, and a second concentration (P−) region 52 covering the lower part of the LOCOS oxide film 40. Consists of.

  As shown in FIG. 2, the diffusion depth d <b> 2 of the second concentration region 52 in the P conductivity type semiconductor region 50 is set to be shallower than the diffusion depth of the first concentration region 51. Further, the impurity concentration (P−) of the second concentration region 52 is set to be lower than the impurity concentration (P) of the first concentration region 51.

  In the semiconductor device 100 of FIG. 1, a P-conductivity type semiconductor region 50 is formed from a lower part of the outermost peripheral trench insulating gate TG1 to a lower part of the LOCOS oxide film 40, and the impurity concentration in the P-conductivity type semiconductor region 50 The corner portion TG1c is covered from the lower part of the outermost peripheral trench insulating gate TG1 by the first concentration region 51 having a high (P). Therefore, in the semiconductor device 100, similarly to the semiconductor device 92 shown in FIG. 13B, the electric field concentration in the vicinity of the corner portion TG1c of the outermost peripheral trench insulating gate TG1 is alleviated, whereby the breakdown voltage can be improved. .

  3 to 5 are diagrams showing simulation results performed to verify the effect when the corner portion TG1c is covered from the lower portion of the outermost peripheral trench insulating gate TG1 by the first concentration region 51 described above. FIG. 3 is a diagram showing an impurity concentration distribution in an enlarged cross section around the corner portion TG1c. FIG. 4 is a diagram showing the electric field strength distribution, and FIG. 5 is a diagram showing the current density distribution during breakdown (breakdown). 3A to 5A are the same as the semiconductor device 91 shown in FIG. 13A, and the tip of the first concentration (P) region 51s is formed at the corner portion TG1c of the outermost peripheral trench insulating gate TG1. This is for a certain semiconductor device 100s. 3B to 5B are the same as the semiconductor device 92 shown in FIG. 13B, and the semiconductor in which the tip of the first concentration (P) region 51d wraps around to the lower part of the outermost trench insulating gate TG1. For the device 100d.

  As shown in FIG. 4A, in the semiconductor device 100s, not only the equal electric field strength lines in the first concentration region 51s but also the equal electric field strength lines in the first N conductivity type layer 21 are formed in the outermost trench insulating gate TG1. Converging at the corner TG1c, the electric field concentration at the corner TG1c is large. Accordingly, as shown in FIG. 5A, the maximum current density portion at the time of breakdown is also formed below the corner portion TG1c, but the breakdown voltage is as small as 256.7V, and the current at the trench corner portion TG1c at the time of breakdown. In order to concentrate, the maximum current density is a small value.

  On the other hand, as shown in FIG. 4B, in the semiconductor device 100d, a part of the equal electric field strength line in the first concentration region 51d converges to the corner portion TG1c of the outermost peripheral trench insulating gate TG1, Electric field concentration at the corner portion TG1c is small. Accordingly, as shown in FIG. 5B, the maximum current density portion at the time of breakdown is formed below the bottom of the outermost peripheral trench insulating gate TG1 different from the corner portion TG1c, and the breakdown voltage is as large as 287.8V, yielding. Sometimes the current is distributed and the maximum current density can be increased.

  As described above, in the semiconductor device 100d shown in FIGS. 3B to 5B, the corner portion TG1c is covered with the first concentration region 51d from the lower part of the outermost trench insulating gate TG1, so that the outermost trench insulation is performed. Electric field concentration in the vicinity of the corner portion TG1c of the gate TG1 is alleviated. Thereby, in the semiconductor device 100d shown in FIGS. 3B to 5B, the breakdown voltage can be improved as compared with the semiconductor device 100s shown in FIGS. 3A to 5A.

  Further, in the semiconductor device 100 of FIG. 1, the second concentration (P−) region 52 of the P conductivity type semiconductor region 50 covering the lower portion of the LOCOS oxide film 40 disposed separately from the outermost trench insulating gate TG1 is The impurity concentration is set lower than that of the first concentration (P) region 51 that covers the corner portion TG1c of the outermost peripheral trench insulating gate TG1. For this reason, the depletion layer is easily spread around the second concentration region as compared with the first concentration region. By utilizing this, in the semiconductor device 100, the breakdown voltage of the outer portion of the outermost peripheral trench insulating gate TG1 can be set higher than that of the inner portion (cell forming portion).

  In the semiconductor device 100 of FIG. 1, particularly, the impurity concentration of the second concentration region 52 is set appropriately low corresponding to the N conductivity type semiconductor substrate 20 (first N conductivity type layer 21), and below the LOCOS oxide film 40. The N conductivity type semiconductor substrate 20 (first N conductivity type layer 21) and the second concentration region 52 preferably constitute a so-called RESURF (Reduced Surface electric field) structure. Thus, the N-conductivity-type semiconductor substrate 20 (first N-conductivity-type layer 21) and the second concentration region 52 below the LOCOS oxide film 40 are completely depleted within a predetermined range when a reverse voltage is applied. The breakdown voltage of 100 can be further increased.

  In the semiconductor device 100, the shortest distance w from the corner portion TG1c of the outermost peripheral trench insulating gate TG1 in FIG. 2 to the boundary surface indicated by the dotted line between the first concentration region 51 and the second concentration region 52 is the first concentration region 51. The diffusion depth is preferably set to be greater than the diffusion depth d1. According to this, the second concentration region 52 in the P-conductivity type semiconductor region 50 is sufficiently separated from the corner portion TG1c of the outermost peripheral trench insulating gate TG1, and the corner portion TG1c is more sufficient than the first concentration region 51 having a high impurity concentration. It will be covered with. For this reason, the effect of reducing the electric field concentration in the vicinity of the corner portion TG1c of the outermost peripheral trench insulating gate TG1 by the first concentration region 51 can be exhibited in a state where the influence of the second concentration region 52 having a low impurity concentration is eliminated. it can.

  Further, in the semiconductor device 100, as shown in FIG. 2, the impurity concentration (P−) of the second concentration region 52 is set lower than the impurity concentration (P) of the first concentration region 51, and the second concentration region 52. Is set to be shallower than the diffusion depth d 1 of the first concentration region 51. The structure including the first concentration region 51 and the second concentration region 52 having different impurity concentrations and diffusion depths can be formed in one step by the manufacturing method described below. Therefore, the semiconductor device 100 can be an inexpensive semiconductor device.

  Next, a method for manufacturing the semiconductor device 100 of FIG. 1 will be described.

  6 to 9 are cross-sectional views for each process relating to the method for manufacturing the semiconductor device 100.

First, as shown in FIG. 6A, an N-conductivity type semiconductor substrate 20 composed of a first N-conductivity type (N−) layer 21 and a second N-conductivity type (N +) layer 22 is prepared. Next, the surface of the semiconductor substrate 20 is oxidized to form a silicon oxide (SiO ₂ ) film 61. Next, a silicon nitride (SiN) film 62 is deposited on the silicon oxide film 61.

  Next, in order to form the LOCOS oxide film 40 of FIG. 1, as shown in FIG. 6B, a first resist mask M1 having a predetermined opening K1 is formed, and the silicon oxide film 61 is used as a stopper. The silicon nitride film 62 is etched through the part K1. As a result, an opening K1 is formed in the silicon nitride film 62 in advance.

  Next, after removing the first resist mask M1, a second resist mask M2 having a predetermined opening K2 is formed as shown in FIG. 6C in order to form the P-conductivity type semiconductor region 50 of FIG. Form.

  Next, in the ion implantation step shown in FIG. 6D, a P-conductivity type impurity such as boron (B) is ion-implanted through the opening K2 of the second resist mask M2. Thus, a P conductivity type impurity ion implantation layer 50a is formed in a region where the P conductivity type semiconductor region 50 of FIG. 1 is to be formed in the N conductivity type semiconductor substrate 20 (first N conductivity type layer 21). The P conductivity type impurity ion implantation layer 50a extends from the region where the outermost peripheral trench insulating gate TG1 shown in FIG. 1 is formed to the region where the LOCOS oxide film 40 is to be formed (first N conductivity type). It is formed near the very shallow surface of layer 21).

  Next, after removing the second resist mask M2, in the LOCOS oxide film forming step shown in FIG. 7A, heat treatment is performed under conditions of, for example, 1050 ° C. for 30 minutes, and the opening K1 of the silicon nitride (SiN) film 62 is obtained. The LOCOS oxide film 40 is formed by oxidizing the exposed semiconductor substrate 20 (first N conductivity type layer 21).

  Accordingly, the ion implantation layer 52a formed near the surface of the N conductivity type semiconductor substrate 20 (first N conductivity type layer 21) in the ion implantation step of FIG. 7A is divided into two regions 51a and 52a having different concentration distributions. That is, when the LOCOS oxide film 40 shown in FIG. 7A is formed, P conductivity type impurities are taken into the LOCOS oxide film 40 from the ion implantation layer 50a shown in FIG. Therefore, in the lower region of the LOCOS oxide film 40, the amount of P-conductivity type impurities is reduced to form a low concentration ion implantation region 52a. There is no change in the amount, and the state at the time of ion implantation is maintained, and the ion implantation region 51a having a high concentration is obtained.

  Next, in the thermal diffusion step shown in FIG. 7B, for example, P conductivity type impurities implanted by heat treatment under conditions of 1170 ° C. for 240 minutes are respectively transferred from the ion implantation regions 51a and 52a in FIG. 7A. Heat diffuse. At this time, the first concentration region 51 having a high impurity concentration and a deep diffusion depth shown in FIG. 1 is formed from the ion implantation region 51 a having a high concentration of the P conductivity type impurity, and the P conductivity type impurity under the LOCOS oxide film 40 is formed. From the ion implantation region 52a having a low concentration, the second concentration region 52 of FIG. 1 having a low impurity concentration and a shallow diffusion depth is formed. As a result, the P-conductivity type semiconductor region 50 composed of the first concentration region 51 and the second concentration region 52 shown in FIG. 1 is formed.

  Next, as shown in FIG. 7C, the silicon nitride film 62 is removed, and preparation of the N-conductivity type semiconductor substrate 20 before forming the trench insulated gate transistor is completed.

  Next, as shown in FIG. 8A, a silicon oxide film 23 serving as a mask for forming the interlayer insulating film (lower layer) 23 and the next trenches T and T1 in FIG. 1 is formed. Next, a resist mask (not shown) having a predetermined opening is formed on the silicon oxide film 23, and the silicon oxide film 23, the silicon oxide film 61, and the N-conductivity type semiconductor substrate 20 (first N) are formed through the opening. The conductive layer 21) is continuously etched to form trenches T and T1 shown in FIG. 8B at predetermined positions. Next, as shown in FIG. 8C, after the side wall oxide film 31 is formed in the trenches T and T1 by thermal oxidation, polycrystalline silicon 32 is deposited and the trench T is embedded and patterned. Thereby, trench insulating gate TG and outermost peripheral trench insulating gate TG1 made of sidewall oxide film 31 and polycrystalline silicon 32 in FIG. 1 are formed. Next, as shown in FIG. 8D, a thermal oxide film 63 is formed on the surface of the polycrystalline silicon 32. Next, in order to remove the silicon oxide film 23 used as a mask for forming the trenches T and T1, a resist mask M3 having a predetermined opening is formed.

  Next, as shown in FIG. 9A, etching is performed through the resist mask M3 of FIG. 8D, and the LOCOS oxide film 40, the silicon oxide film 23, and a part of the thermal oxide film 63 are left, and N The oxide film formed on the surface of the conductive semiconductor substrate 20 (first N conductive type layer 21) is removed. Next, as shown in FIG. 9B, ion implantation is performed to sequentially form the channel formation region 34 and the source region 33 of FIG. 1 and the N conductivity type (N +) region 35 on the main surface side. Next, as shown in FIG. 9C, the interlayer insulating film (upper layer) 23 of FIG. 1 is formed, and an opening for electrode connection is provided. Next, as shown in FIG. 9D, the aluminum (Al) electrode layer 24 of FIG. 1 is formed and processed into a predetermined pattern.

  Thereby, the semiconductor device 100 shown in FIG. 1 is completed.

  The manufacturing process of the semiconductor device 100 shown in FIGS. 6 to 9 includes the LOCOS oxide film forming step shown in FIG. 7A after the ion implantation step shown in FIG. A feature is that the thermal diffusion step shown in FIG. 7B is performed after the film formation step. That is, in the method of manufacturing the semiconductor device 100, after the ion implantation process shown in FIG. 6D, ions are implanted into the region where the P-conductivity type semiconductor region 50 is to be formed, and then the LOCOS oxidation shown in FIG. The LOCOS oxide film 40 is formed in the film formation process, and then the P-conductivity type impurities ion-implanted in the thermal diffusion process shown in FIG. 7B are thermally diffused. After the ion implantation of FIG. 6D, the N conductive type semiconductor substrate 20 (first N conductive type layer 21) extends from the region where the outermost periphery trench insulating gate TG1 is to be formed to the region where the LOCOS oxide film 40 is to be formed. Near the extremely shallow surface, an ion-implanted layer 50a of P conductivity type impurities is formed. The ion implantation layer 50a formed near the surface of the N conductivity type semiconductor substrate 20 (first N conductivity type layer 21) has a different concentration distribution after the formation of the LOCOS oxide film 40 shown in FIG. It will be divided into two regions 51a and 52a. Therefore, the first concentration region 51 having a high impurity concentration and a deep diffusion depth is formed in the region where the outermost trench insulating gate TG1 is to be formed by the thermal diffusion step shown in FIG. 7B, and the LOCOS oxide film is formed. In the lower portion of 40, a second concentration region 52 having a low impurity concentration and a shallow diffusion depth is formed.

  The P-conductivity-type semiconductor region 50 is formed by combining the first concentration region 51 and the second concentration region 52 in spite of the difference in impurity concentration and diffusion depth between the first concentration region 51 and the second concentration region 52. It can be formed in a process. Therefore, compared with the case where the first concentration region 51 and the second concentration region 52 having different impurity concentrations and diffusion depths are formed in separate processes, the manufacturing method described above makes the semiconductor device 100 of FIG. 1 inexpensive. Can be manufactured.

  As described above, according to the manufacturing process of the semiconductor device 100 shown in FIGS. 6 to 9, the corner portion TG1c of the outermost peripheral trench insulating gate TG1 is formed in the first concentration region 51 having a high impurity concentration formed in one process. The second concentration region 52 having a low impurity concentration can be used for covering the RESURF structure.

  On the other hand, in the conventional semiconductor device, the concentration distribution of the P-conductivity type semiconductor region formed outside the outermost trench insulating gate is constant. For this reason, the manufacturing process of the conventional semiconductor device is different from the process sequence shown in FIGS. 6A to 7B. Usually, after the ion implantation process, for example, heat treatment is performed under a long heat treatment condition at 1170 ° C. for 480 minutes. A diffusion process is performed, and then a LOCOS oxide film formation process is performed.

FIG. 10 shows the result of examining the relationship between the trench insulating gate depth and the breakdown voltage, using the ion implantation dose as a parameter for the semiconductor device prototyped according to the above-described conventional process sequence and heat treatment conditions. The data indicated by rhombuses in the figure all have an impurity concentration of 9.6 × 10 ¹⁴ cm ⁻³ and a diffusion depth of 26 μm, and the data indicated by squares are all The impurity concentration of the P conductivity type semiconductor region is 9.4 × 10 ¹⁴ cm ⁻³ and the diffusion depth is 25 μm. The data indicated by the diamonds and the data indicated by the squares are substantially the same impurity concentration and diffusion depth data, and the impurity concentration of the P-conductivity type semiconductor region is a value that can satisfy the RESURF condition. The diffusion depth is shallower than the trench insulating gate depth.

As shown in FIG. 10, the semiconductor device manufactured in the conventional process sequence has a low breakdown voltage of about 220 V, although there are variations in 3 × 10 ¹² dose data with a low dose. As shown in FIGS. 3A to 5A, the impurity concentration of the P-conductivity type semiconductor region is low and the diffusion depth is shallower than that of the outermost trench insulating gate. This is because the portion is not covered with the P-conductivity type semiconductor region, and electric field concentration occurs at the corner portion, and the breakdown voltage is determined here.

On the other hand, FIG. 11 shows the result of investigating the relationship between the trench insulating gate depth and the breakdown voltage, using the heat treatment conditions after the LOCOS formation as parameters for the semiconductor device 100 prototyped by the manufacturing steps shown in FIGS. The data indicated by rhombuses in the figure all have the impurity concentration of the second concentration region 52 of 9.6 × 10 ¹⁴ cm ⁻³ and the diffusion depth of 26 μm. The impurity concentration of the second concentration region 52 is 9.4 × 10 ¹⁴ cm ⁻³ and the diffusion depth is 25 μm. For comparison, data when heat treatment was not performed after LOCOS formation is shown by white circles. Also in this case, the data indicated by diamonds and the data indicated by squares are data of substantially the same impurity concentration and diffusion depth, and the impurity concentration of the second concentration region 52 is a value that can satisfy the RESURF condition. However, the diffusion depth is shallower than the trench insulating gate depth.

  As shown in FIG. 11, the semiconductor device 100 manufactured in the process sequence shown in FIGS. 6A to 7B excludes data indicated by white circles that were not subjected to heat treatment after LOCOS formation. Thus, there was no variation, and most of them had a high breakdown voltage near 280V. As shown in FIGS. 3B to 5B, the RESURF structure is constituted by the second concentration region 52 and the N-conductivity type semiconductor substrate 20 (first N-conductivity type layer 21), as well as impurities. This is because the first concentration region 51 having a high concentration and a large diffusion depth covers the corner portion TG1c of the outermost peripheral trench insulating gate TG1, and the electric field concentration at the corner portion is alleviated.

FIG. 12 is a graph showing the distribution of P-conductivity type impurities in a sample heat-treated under each condition after ion-implanting P-conductivity type impurities under the conditions of 120 kV and 1.1 × 10 ¹³ dose by SIMS (Secondary Ionization Mass Spectrometer). It is the result evaluated by the dashed-dotted lines A and B.

  As shown in FIG. 12, in the sample (b) in which the thermal diffusion process was performed before LOCOS formation, the impurity concentration ratio between the first diffusion region 51 and the second diffusion region 52 was as small as about 1.5 times. On the other hand, for the samples (c) and (d) in which the thermal diffusion process was performed after the LOCOS formation and the samples in (a) where the thermal diffusion process was not performed, the impurity concentration ratio between the first diffusion region 51 and the second diffusion region 52 Is 3-4 times larger. Accordingly, the samples (c) and (d) that were subjected to the thermal diffusion process after the LOCOS formation and the samples (a) that were not subjected to the thermal diffusion process (the thermal diffusion process was performed before the LOCOS formation). The breakdown voltage is improved as compared with the sample of (b).

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention include a semiconductor device in which a vertical trench insulated gate transistor is formed as an assembly of cells in an inner portion of a semiconductor substrate, and a manufacturing method thereof. Thus, the semiconductor device has a high breakdown voltage and can be manufactured at low cost, and a manufacturing method thereof.

1 is a schematic cross-sectional view of a semiconductor device 100 as an example of the semiconductor device of the present invention. FIG. 2 is a diagram illustrating a dimensional relationship of main parts in the semiconductor device 100 of FIG. 1. (A), (b) is a figure which shows the simulation result of semiconductor device 100s, 100d, respectively, and is a figure which showed impurity concentration distribution in the expanded cross section around corner | angular part TG1c. (A), (b) is a figure which shows the simulation result of semiconductor device 100s, 100d, respectively, and is a figure which showed electric field strength distribution. (A), (b) is a figure which shows the simulation result of semiconductor device 100s, 100d, respectively, and is the figure which showed the current density distribution at the time of a breakdown (breakdown). FIGS. 5A to 5D are cross-sectional views for each process related to the method for manufacturing the semiconductor device 100. FIGS. FIGS. 5A to 5C are cross-sectional views for each process related to the method for manufacturing the semiconductor device 100. FIGS. FIGS. 5A to 5D are cross-sectional views for each process related to the method for manufacturing the semiconductor device 100. FIGS. FIGS. 5A to 5D are cross-sectional views for each process related to the method for manufacturing the semiconductor device 100. FIGS. It is the result of investigating the relationship between the trench insulating gate depth and the breakdown voltage, using the dose amount of ion implantation as a parameter for a semiconductor device prototyped according to the conventional process sequence and heat treatment conditions. 6 is a result of investigating the relationship between the trench insulating gate depth and the breakdown voltage using the heat treatment conditions after LOCOS formation as a parameter for the semiconductor device 100 prototyped by the manufacturing process shown in FIGS. It is the result of having evaluated the distribution of the P conductivity type impurity of the sample heat-processed on each condition after ion-implanting a P conductivity type impurity with the dashed-dotted lines A and B of a figure by SIMS. (A), (b) is a semiconductor device indicated by patent documents 1, and is a typical sectional view of semiconductor devices 91 and 92, respectively.

Explanation of symbols

91, 92, 100, 100s, 100d Semiconductor device 30 Trench insulated gate transistor 20 N conductivity type semiconductor substrate 21 1st N conductivity type (N−) layer 22 2nd N conductivity type (N +) layer TG Trench insulation gate TG1 Outermost trench isolation Gate TG1c Corner 40 LOCOS oxide film 50 P conductivity type semiconductor region 51, 51s, 51d First concentration (P) region 52 Second concentration (P−) region

Claims (4)

A vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of the first conductivity type semiconductor substrate,
LOCOS oxide film
Separated from the outermost trench insulating gate surrounding the cell assembly, the outermost trench insulating gate is formed on the first conductivity type semiconductor substrate outside the outermost trench insulating gate,
A second conductivity type semiconductor region is formed in a surface layer portion of the first conductivity type semiconductor substrate from a lower portion of the outermost peripheral trench insulating gate to a lower portion of the LOCOS oxide film;
The second conductivity type semiconductor region includes a first concentration region covering a corner portion from a lower portion of the outermost peripheral trench insulating gate and a second concentration region covering a lower portion of the LOCOS oxide film;
The impurity concentration of the second concentration region is set lower than the impurity concentration of the first concentration region;
A semiconductor device, wherein a diffusion depth of the second concentration region is set to be shallower than a diffusion depth of the first concentration region. By the first conductivity type semiconductor substrate and the second concentration region,
The semiconductor device according to claim 1, comprising a RESURF structure.   The shortest distance from a corner of the outermost peripheral trench insulating gate to a boundary surface between the first concentration region and the second concentration region is set larger than a diffusion depth of the first concentration region. 3. The semiconductor device according to 1 or 2. A vertical trench insulated gate transistor is formed as an assembly of cells on an inner portion of the first conductivity type semiconductor substrate,
LOCOS oxide film
Separated from the outermost trench insulating gate surrounding the cell assembly, the outermost trench insulating gate is formed on the first conductivity type semiconductor substrate outside the outermost trench insulating gate,
A second conductivity type semiconductor region is formed in a surface layer portion of the first conductivity type semiconductor substrate from a lower portion of the outermost peripheral trench insulating gate to a lower portion of the LOCOS oxide film;
The second conductivity type semiconductor region includes a first concentration region covering a corner portion from a lower portion of the outermost peripheral trench insulating gate and a second concentration region covering a lower portion of the LOCOS oxide film;
The impurity concentration of the second concentration region is set lower than the impurity concentration of the first concentration region;
A method for manufacturing a semiconductor device, wherein a diffusion depth of the second concentration region is set to be shallower than a diffusion depth of the first concentration region,
An ion implantation step of ion-implanting a second conductivity type impurity into a region where the second conductivity type semiconductor region is to be formed in the first conductivity type semiconductor substrate;
A LOCOS oxide film forming step of forming the LOCOS oxide film after the ion implantation step;
After the LOCOS oxide film formation step, a thermal diffusion step of thermally diffusing the ion-implanted second conductivity type impurity to form a second conductivity type semiconductor region composed of the first concentration region and the second concentration region is performed. A method for manufacturing a semiconductor device, comprising:

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