JPS61137368A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61137368A JPS61137368A JP25915584A JP25915584A JPS61137368A JP S61137368 A JPS61137368 A JP S61137368A JP 25915584 A JP25915584 A JP 25915584A JP 25915584 A JP25915584 A JP 25915584A JP S61137368 A JPS61137368 A JP S61137368A
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- region
- substrate
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- Prior art date
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- Pending
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- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000015556 catabolic process Effects 0.000 claims description 24
- 230000002093 peripheral effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 abstract 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置における窩耐圧化技術に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a technique for increasing voltage resistance in a semiconductor device.
パワーＭＯ５ＦＥＴは、例えば１９８１年１１月２３日
日経マグロウヒル社発行日経エレクトロニクス誌１３０
項〜１４１項に示されるように種々の構造が開発されて
いるが、第４図に示すように半導体基板１の表面に形成
された複数のＭＯＳセルを構成する半導体Ｐｎ接合の耐
圧を向上するためにこれらセルを囲み半導体基板周辺に
そって半導体Ｐｎ接合からなるフィールド・リミット・
リング（ＦＬＲ）１１を設けたものがある。The power MO5FET is described, for example, in Nikkei Electronics Magazine 130, published by Nikkei McGraw-Hill on November 23, 1981.
Various structures have been developed as shown in Sections 1 to 141, and as shown in FIG. For this purpose, a field limit circuit consisting of semiconductor Pn junctions is placed around these cells and along the periphery of the semiconductor substrate.
Some are equipped with a ring (FLR) 11.
このＦＬＲ構造は、本来フローティングなＰｎ接合から
延びる空乏層により、ＭＯ３素子を構成する主接合の電
界を緩和し、それによって主接合の耐圧の向上を図るよ
うになっているが、ＦＬＲ自身の耐圧が小さいとＦＬＲ
側で耐圧が決定されることになる。したがってＭＯ３素
子（ＩＣ）を設計する段階では、ＭＯ８素子の耐圧をＦ
ＬＲが主接合のいずれかの耐圧により決定する。This FLR structure uses a depletion layer extending from the originally floating Pn junction to alleviate the electric field of the main junction that constitutes the MO3 element, thereby improving the breakdown voltage of the main junction.However, the breakdown voltage of the FLR itself is is small, FLR
The withstand pressure will be determined by the side. Therefore, at the stage of designing the MO3 element (IC), the withstand voltage of the MO8 element should be set to F.
LR is determined by the breakdown voltage of one of the main junctions.
ＦＬＲ側で耐圧を決定した場合１表面の可動イオンの影
響を受けやすく、信頼性試験で耐圧低下現象が発生する
。したがって、主接合で素子の耐圧を決定することにな
るが、このためにはＦＬＲの十分な耐圧マージンが必要
となる。When the breakdown voltage is determined on the FLR side, it is susceptible to the influence of mobile ions on the first surface, and a breakdown voltage drop phenomenon occurs during reliability tests. Therefore, the breakdown voltage of the element is determined by the main junction, and for this purpose, a sufficient breakdown voltage margin of the FLR is required.
本発明の目的とするところは、ＦＬＲ構造を有する半導
体装置において、高い耐圧のＦＬＲ構造をうることによ
り、半導体装置の素子の耐圧を向上することにある。An object of the present invention is to improve the breakdown voltage of elements of a semiconductor device by providing a high breakdown voltage FLR structure in a semiconductor device having an FLR structure.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基体の主表面に半導体素子が形成され
、この半導体素子を取り囲み、基体周辺部表面に基体表
面と導電型の異なる半導体領域からなるフィールド・リ
ミット・リングが形成された半導体装置において上記フ
ィールド・リミット・リングに接してその外側の接合勾
配をゆるやかにするような低濃度の耐圧層を形成するこ
とにより、フィールド・リミット・リングの耐圧を高め
、それにより素子の耐圧を向上するものである。That is, in a semiconductor device in which a semiconductor element is formed on the main surface of a semiconductor substrate, a field limit ring is formed on the peripheral surface of the substrate, surrounding the semiconductor element, and consisting of a semiconductor region having a conductivity type different from that of the substrate surface.・By forming a low-concentration breakdown voltage layer that is in contact with the limit ring and softens the junction gradient on the outside, the breakdown voltage of the field limit ring is increased, thereby improving the breakdown voltage of the device. .
〔実施例〕
第１図は本発明の一実施例を示すもので、縦形Ｄ Ｓ
Ａ （Ｄｉｆｆｕｓｉｏｎ ５ｅｌｆ Ａｌｉｇｎｍｅ
ｎｔ）構造のパワーＭＯ８ＦＥＴの要部断面図である。[Embodiment] Fig. 1 shows an embodiment of the present invention.
A (Diffusion 5elf Alignme
nt) is a cross-sectional view of a main part of a power MO8FET having a structure.
同図において、１はドレインとなるｎ−型シリコン基板
（チップ本体）、２はドレイ電極（Ｄ）形成のためのｎ
″型層、３は絶縁膜（Ｓｉ０２膜）、４はポリシリコン
ゲート、５はチャネル部となるＰ型層、６はソースとな
るｎ４型層でＰ型層５゜ｎ０型層６は上記ポリシリコン
ゲート４をマスクとして不純物をイオン打込み、拡散す
ることによりセルファライン（自己整合物）にゲート長
を決定するものである。これらＰ型層、ｎ”型層６及び
ゲート４とでＭＯＳＦＥＴの一つのセルを構成する。In the figure, 1 is an n-type silicon substrate (chip body) that will become a drain, and 2 is an n-type silicon substrate for forming a drain electrode (D).
3 is an insulating film (Si02 film), 4 is a polysilicon gate, 5 is a P-type layer that becomes a channel part, 6 is an n4-type layer that becomes a source, and P-type layer 5゜n0-type layer 6 is the polysilicon layer. Using the silicon gate 4 as a mask, impurity ions are implanted and diffused to determine the gate length in a self-aligned material.These P-type layer, n''-type layer 6, and gate 4 form a MOSFET. Configure one cell.
７はフィールド絶縁膜で、この上にたとえばゲート用ボ
ンディングバットとなるアルミニウム膜８を形成し、前
記ポリシリコンゲート４とを接続している。９はアルミ
ニウム膜からなるソース電極で前記Ｐ型層５の一部及び
ｎ“型層６にコンタクトさせである。１０はアルミニウ
ム膜よりなるフィールドプレートでチップｌの周縁にそ
って形成される。Reference numeral 7 denotes a field insulating film, on which an aluminum film 8 serving as a gate bonding bat, for example, is formed, and is connected to the polysilicon gate 4. Reference numeral 9 denotes a source electrode made of an aluminum film, which is in contact with a part of the P-type layer 5 and the n'' type layer 6. Reference numeral 10 denotes a field plate made of an aluminum film, which is formed along the periphery of the chip l.
１１はＰ型層からなるフィールド・リミット・リング（
ＦＬ’Ｒ部）で複数のＭＯＳセルを取り餌むように基板
（チップ）１の周辺部に形成されるにのＰ型層１１は各
セルを構成するＰ型層５と同じ拡散工程で形成される。11 is a field limit ring (
The P-type layer 11 formed on the periphery of the substrate (chip) 1 to capture a plurality of MOS cells in the FL'R section) is formed in the same diffusion process as the P-type layer 5 constituting each cell. .
１２はＰ−型高耐圧層で低濃度ボロンイオン打込みによ
り上記ＦＬＲに接し、その外側の接合勾配をゆるやかに
するような低濃度で接合深さが浅い層（０，５〜１．０
μｍ）として形成される。Reference numeral 12 denotes a P-type high breakdown voltage layer which is in contact with the above FLR by implanting low concentration boron ions, and a layer with a low concentration and shallow junction depth (0.5 to 1.0
μm).
（第２図）
すなわち、このＰ−型高耐圧層は濃度、横幅あるいは接
合深さｘｊは下記の条件にしたがって決定される。(FIG. 2) That is, the concentration, width, or junction depth xj of this P-type high breakdown voltage layer is determined according to the following conditions.
（１）Ｐ−型高耐圧層１２の電界はＰ−型層が空乏層化
することにより、Ｐ型のＦＬＲ部１１の電界より小さく
押える。(1) The electric field of the P-type high voltage layer 12 is suppressed to be smaller than the electric field of the P-type FLR section 11 because the P-type layer becomes a depletion layer.
（２）Ｐ−型高耐圧層１２の空乏層化（ピンチオフ）が
速やかに行われるために、ｎ−型基板１の濃度に比べＰ
−型層１２を低濃度とするが、ＦＬＲｌｔｔの面積の増
大を押えるように接合深さｘｊの最適値化設計が必要と
なる。(2) Since the P-type high breakdown voltage layer 12 is quickly depleted (pinch-off), the concentration of P
- Although the mold layer 12 has a low concentration, it is necessary to design the junction depth xj to an optimum value so as to suppress an increase in the area of FLRltt.
以上実施例で述べた本発明によれば下記のように効果が
得られる。According to the present invention described in the embodiments above, the following effects can be obtained.
従来のＦＬＲを有する半導体装置においては、たとえば
第５図に示すように、素子電極へのノ（イアス印加によ
って接合（主接合）とＦＬＲの接合よりの空乏層の延び
（あるいは電気力線の延び）が互いに相殺することでバ
ランスするが、ＦＬＲのみの場合、外側では空乏層が横
方向へ延びにくく、基板表面で電流集中し、耐圧が決定
される。In a conventional semiconductor device having an FLR, for example, as shown in FIG. ) are balanced by canceling each other out, but in the case of only an FLR, the depletion layer is difficult to extend laterally on the outside, current concentrates on the substrate surface, and the withstand voltage is determined.
これに対してＦＬＲＩ ｌに接して高耐圧層１２を設け
た本発明では、第３図に示すように空乏層が高耐圧層に
そって外側へ延びて、電流集中を緩和し、耐圧性が向上
する。On the other hand, in the present invention, in which the high breakdown voltage layer 12 is provided in contact with the FLRI 1, the depletion layer extends outward along the high breakdown voltage layer to alleviate current concentration and improve the breakdown voltage. improves.
第６図及び第７図は印加電圧の変化に伴う主接合ＣＢ）
とＦＬＲの接合（Ａ）における電界の変化を曲線図であ
られしたものである。Figures 6 and 7 show the main junction CB as the applied voltage changes)
This is a curve diagram showing the change in electric field at the junction (A) of FLR and FLR.
従来のＦＬＲを有する半導体装置では第６図に示すよう
に、所定の印加電圧（ピンチオフ電圧）Ｖｐで主接合側
の電界（Ｂ）にＦＬＲ側の電界（Ａ）が追いつくことに
なるのに対し、本発明では、第７図に示すように、高耐
圧層を設けることでＦＬＲ側（Ａ′）の電界上昇の傾き
が小さくなっていることにより、前記電圧Ｖｐにおいて
も電界に余裕があり、より高い■ｐ′でピンチオフされ
る。In a conventional semiconductor device having an FLR, as shown in FIG. 6, the electric field (A) on the FLR side catches up with the electric field (B) on the main junction side at a predetermined applied voltage (pinch-off voltage) Vp. In the present invention, as shown in FIG. 7, the slope of the rise in the electric field on the FLR side (A') is reduced by providing the high breakdown voltage layer, so there is a margin in the electric field even at the voltage Vp, It is pinched off at higher ■p'.
第８図は主接合（素子側）とＦＬＲとの間の間隔ｄに対
する耐圧変動の方向を、従来構造の場合（１）と２本発
明構造の場合（ＴＩ）とを対して示すものである。FIG. 8 shows the direction of breakdown voltage variation with respect to the distance d between the main junction (element side) and the FLR for the conventional structure (1) and the structure of the present invention (TI). .
同図によれば、本発明の構造では、ＦＬＲと主接合間の
距離ｄと耐圧の関係は、ＦＬＲのみの従来構造の場合よ
り高耐圧に設計できることを示している。高温逆バイア
ス試験による耐圧変動は。According to the figure, in the structure of the present invention, the relationship between the distance d between the FLR and the main junction and the breakdown voltage shows that the structure can be designed to have a higher breakdown voltage than the conventional structure including only the FLR. What is the breakdown voltage variation due to high temperature reverse bias test?
同図矢印の方向に進み、本発明構造（ＩＩ）では、ＦＬ
Ｒの耐圧にマージンがあるため耐圧低下まで進まない。Proceeding in the direction of the arrow in the figure, in the structure (II) of the present invention, FL
Since there is a margin in the withstand voltage of R, the process does not proceed to the point where the withstand voltage drops.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが１本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々に変更
できることはいうまでもなし１ 。Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. 1.
たとえば、ＦＬＲと同時に基板表面上に第１図で示すよ
うにアルミニウム膜からなるフィールドプレート（Ｆ、
Ｐ）１０を併用することができる。For example, a field plate (F,
P) 10 can be used in combination.
本発明は、ＦＬＲ構造を利用した半導体装置（ＭＯＳ
Ｔ Ｃ，Ｂ ｉ −Ｉ Ｃ，Ｂ−ＭＯＳ Ｉ Ｃ）に適
用することができる。The present invention is a semiconductor device (MOS) using an FLR structure.
It can be applied to T C, B i -IC, B-MOS I C).
本発明は、特にＦＬＲを有する高耐圧（３００Ｖ以上）
のパワーＭＯ３ＦＥＴ、パワートランジスタに応用して
有効である。The present invention is particularly suitable for high voltage withstand voltage (300V or more) having FLR.
It is effective when applied to power MO3FETs and power transistors.
第１図は本発明の一実施例を示すパワーＭＯ５ｒｃの要
部断面図である。
第２図は第１図における二部拡大断面図、第３図は本発
明の詳細な説明するための断面図である。
第４図はＦＬＲ構造を有する半導体装置の例を模型図で
示す正面断面斜面図である。
第５図は第４図におけるＦＬＲの動作原理を示す断面図
である。
第６図乃至第８図は本発明の詳細な説明するための曲線
図である。
ｌ・・・ｎ−型シリコン基板、２・・・ｎ″型層３・・
・絶縁ゲート、４・・・ゲート、５・・・Ｐ型層（チャ
ネル部）６・−・ｎ０型Ｎ（ドレイン）、７・・フィー
ルド絶縁膜、８，９・・・アルミニウム電極、１０・・
・フィールドプレート、１１・・Ｐ型層（ＦＬＲ）、１
２・・・高耐圧Ｐ−型層。
第 ３ 図
第 ４ 図
第 ６ 図
第 ７ 図
Ｑ ２７［１％！ Ｌ ＶＰ
ＣＶ）第 ８ 図
（ｆｌ？ｒ死ず珀訊）
闇不伶を−FIG. 1 is a sectional view of a main part of a power MO5rc showing an embodiment of the present invention. FIG. 2 is an enlarged sectional view of two parts in FIG. 1, and FIG. 3 is a sectional view for explaining the present invention in detail. FIG. 4 is a front cross-sectional oblique view schematically showing an example of a semiconductor device having an FLR structure. FIG. 5 is a sectional view showing the operating principle of the FLR in FIG. 4. 6 to 8 are curve diagrams for explaining the present invention in detail. l...n-type silicon substrate, 2...n'' type layer 3...
・Insulated gate, 4... Gate, 5... P type layer (channel part) 6... n0 type N (drain), 7... Field insulating film, 8, 9... Aluminum electrode, 10...・
・Field plate, 11...P-type layer (FLR), 1
2...High voltage P-type layer. Figure 3 Figure 4 Figure 6 Figure 7 Q 27 [1%! L VP
CV) Figure 8 (fl?r deathless question) Darkness -
Claims (1)
の半導体素子を取り囲み、基体周辺部表面に基体表面と
導電型の異なる半導体領域からなるフィールドリミット
リングが形成された半導体装置であって、上記導電形の
異なる半導体領域に接してその外側の接合勾配をゆるや
かにするような低濃度の耐圧層が形成されていることを
特徴とする半導体装置。 ２、上記半導体素子は縦形のＭＯＳＦＥＴである特許請
求の範囲第１項に記載の半導体装置。[Claims] 1. A semiconductor element is formed on one main surface of a semiconductor substrate, and a field limit ring is formed on the peripheral surface of the substrate, surrounding the semiconductor element, and consisting of a semiconductor region having a conductivity type different from that of the substrate surface. 1. A semiconductor device, characterized in that a low concentration breakdown voltage layer is formed in contact with the semiconductor regions having different conductivity types to soften the junction gradient on the outside thereof. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a vertical MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25915584A JPS61137368A (en) | 1984-12-10 | 1984-12-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25915584A JPS61137368A (en) | 1984-12-10 | 1984-12-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61137368A true JPS61137368A (en) | 1986-06-25 |
Family
ID=17330103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25915584A Pending JPS61137368A (en) | 1984-12-10 | 1984-12-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61137368A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63194366A (en) * | 1987-02-09 | 1988-08-11 | Toshiba Corp | High breakdown-voltage planar type semiconductor element |
| EP0568692A1 (en) * | 1991-11-25 | 1993-11-10 | Harris Corp | Power fet with shielded channels. |
| EP0624943A1 (en) * | 1993-05-10 | 1994-11-17 | STMicroelectronics S.A. | Serial current limiting device |
| US5430324A (en) * | 1992-07-23 | 1995-07-04 | Siliconix, Incorporated | High voltage transistor having edge termination utilizing trench technology |
| US5543645A (en) * | 1992-11-24 | 1996-08-06 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| FR2768858A1 (en) * | 1997-09-22 | 1999-03-26 | Sgs Thomson Microelectronics | Grid contact pad structure |
| JP2006516815A (en) * | 2003-01-15 | 2006-07-06 | クリー インコーポレイテッド | Edge termination structure for silicon carbide semiconductor device and manufacturing method thereof |
| JP2009016618A (en) * | 2007-07-05 | 2009-01-22 | Denso Corp | Semiconductor device and manufacturing method thereof |
| US9515135B2 (en) | 2003-01-15 | 2016-12-06 | Cree, Inc. | Edge termination structures for silicon carbide devices |
| WO2018207712A1 (en) * | 2017-05-08 | 2018-11-15 | ローム株式会社 | Semiconductor device |
-
1984
- 1984-12-10 JP JP25915584A patent/JPS61137368A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63194366A (en) * | 1987-02-09 | 1988-08-11 | Toshiba Corp | High breakdown-voltage planar type semiconductor element |
| EP0568692A1 (en) * | 1991-11-25 | 1993-11-10 | Harris Corp | Power fet with shielded channels. |
| US5605852A (en) * | 1992-07-23 | 1997-02-25 | Siliconix Incorporated | Method for fabricating high voltage transistor having trenched termination |
| US5430324A (en) * | 1992-07-23 | 1995-07-04 | Siliconix, Incorporated | High voltage transistor having edge termination utilizing trench technology |
| US5780895A (en) * | 1992-10-24 | 1998-07-14 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| US5543645A (en) * | 1992-11-24 | 1996-08-06 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| US5563436A (en) * | 1992-11-24 | 1996-10-08 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| US5956582A (en) * | 1993-05-10 | 1999-09-21 | Sgs-Thomson Microelectronics S.A. | Current limiting circuit with continuous metallization |
| FR2705173A1 (en) * | 1993-05-10 | 1994-11-18 | Sgs Thomson Microelectronics | Serial current limiter component. |
| EP0624943A1 (en) * | 1993-05-10 | 1994-11-17 | STMicroelectronics S.A. | Serial current limiting device |
| FR2768858A1 (en) * | 1997-09-22 | 1999-03-26 | Sgs Thomson Microelectronics | Grid contact pad structure |
| JP2006516815A (en) * | 2003-01-15 | 2006-07-06 | クリー インコーポレイテッド | Edge termination structure for silicon carbide semiconductor device and manufacturing method thereof |
| JP2011243999A (en) * | 2003-01-15 | 2011-12-01 | Cree Inc | Edge termination structure for silicon carbide semiconductor devices and methods of fabricating same |
| US8124480B2 (en) | 2003-01-15 | 2012-02-28 | Cree, Inc. | Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations |
| JP2012084910A (en) * | 2003-01-15 | 2012-04-26 | Cree Inc | Edge termination structure for silicon carbide semiconductor device and method for fabricating the same |
| US9515135B2 (en) | 2003-01-15 | 2016-12-06 | Cree, Inc. | Edge termination structures for silicon carbide devices |
| JP2009016618A (en) * | 2007-07-05 | 2009-01-22 | Denso Corp | Semiconductor device and manufacturing method thereof |
| WO2018207712A1 (en) * | 2017-05-08 | 2018-11-15 | ローム株式会社 | Semiconductor device |
| JPWO2018207712A1 (en) * | 2017-05-08 | 2020-03-26 | ローム株式会社 | Semiconductor device |
| US11101345B2 (en) | 2017-05-08 | 2021-08-24 | Rohm Co., Ltd. | Semiconductor device |
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