JPS63263767A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a low concentrated drain structure of high breakdown strength which is remarkably improved in performance by a method wherein impurity of a low concentrated diffusion layer is so distributed as to be maxi mum inside a substrate in value and a diffusion layer region of the same conduc tivity type as the substrate, which is higher than the substrate in concentration, is provided inside the substrate under a low and a high concentrated diffusion layer. CONSTITUTION:Phosphorous is injected at 100 keV through a gate electrode serving as a mask and thereafter heat treatment is performed for the formation of a low concentrated diffusion layer 4. The low concentrated diffusion layer 4 is about 1X10<13>cm<-3> at its maximum in concentration, about 0.25mum in depth and bounded by a puch-through-stopper region. Thereafter, arsenic is injected, for example, to 5X10<15> cm<-2> at 80 keV, and a high concentration diffused layer 6 is formed. The depth of the diffused layer is about 0.2 mum. Thereafter, an interlaminar insulating film 2 is spread and a contact hole is provided, then the process is completed after an aluminum wiring is built. Thereby, a device can be realized which is high in breakdown strength and alleviated in a short channel effect at the same time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and is particularly suitable for increasing the reliability of a fine MIS type field effect transistor, and has excellent hot carrier resistance and short channel effect resistance. The present invention relates to a MIS type field effect transistor.

[Conventional technology]

In conventional MIS type field effect transistors, as the gate length becomes shorter, the electric field near the drain during operation becomes extremely large, resulting in a significant decrease in reliability due to increased short channel effects and characteristic deterioration due to hot carrier injection. This has become a big problem.

Various structures have been considered to prevent this and improve reliability, especially withstand voltage, but one of the most promising structures at the Imicron level is the one described in U.S. Pat. A lightly doped drain (Lightly) is offset and has a lightly doped diffusion layer between
An example is a doped drain (LDD) structure. Furthermore, as a structure for alleviating the short channel effect, I, E, D, M, Technical Digest (1982), paragraphs 718 to 719 (
I E D M Technical Digest (
1982) PP 718-719), there is one in which a punch-through stopper region (P pocket) is provided around a low concentration diffusion layer of an LDD structure, and this is shown in FIG.

[Problem that the invention seeks to solve]

When using the above-mentioned conventional technology to construct a finer element in the submicron region, there are problems that 1) the degree of improvement in breakdown voltage is insufficient, and 2) the short channel effect becomes severe.

In the conventional LDD structure, when the gate length is shortened to the submicron region, the short channel effect becomes severe.
Reliability is also uncertain depending on the amount of withstand voltage improvement in this structure. In addition, although the channel stopper region material shown in FIG. 2 can certainly suppress the short channel effect, since the channel stopper region is located all around the low concentration region, the internal electric field becomes strong and no improvement in breakdown voltage can be expected.

The purpose of the present invention is to achieve the above 1) even in the submicron region.
, 2) The objective is to provide a structure that can solve the problems at the same time.

[Means for solving problems]

The above purpose is to make the impurity distribution of the low concentration diffusion layer reach its maximum value inside the substrate, as shown in Figure 1, and to make the impurity distribution of the same conductivity type as the substrate inside the substrate under the low concentration and high concentration diffusion layers. Higher concentration diffusion layer region (punch-through stopper region)
This is achieved by providing

[Effect]

The hot carrier effect in minute MOS transistors has become more prominent as the power supply voltage remains constant while the device dimensions have been scaling year by year.Currently, the withstand voltage determined by the hot carrier effect is This is the most severe condition as it is lower than the breakdown voltage near the drain. FIG. 4 shows the dependence of hot carrier breakdown voltage on gate length in various structures. Hot carrier withstand voltage is defined as a drain voltage whose transfer conductance fluctuates by 10% in 10 years. In the conventional single drain structure 12, the voltage is less than 5V at 1 μm and cannot be used at a power supply voltage of 5V.On the other hand, in the conventional LDOF11B structure 10 with a high withstand voltage structure, the voltage is less than 7V and 5V at 1 μm. There is.

However, even in this LDD structure 10, for example, the gate length is 0.
When the thickness becomes 5 μm, the withstand voltage is insufficient. When the low concentration drain region of the conventional LDD structure is formed deep inside the substrate, the generation part of hot carriers moves to the inside of the substrate, and the amount of injection into the gate decreases. However, the hot carrier breakdown voltage 9 is improved compared to the conventional LDDifR structure 10, and it can be used as a 5Vffi source even at the 0.5 μm level.

Furthermore, when the depth of the lightly doped drain region is increased in this manner, the short channel effect generally becomes severe, and the threshold voltage is greatly reduced at a short gate length. This situation is shown in Figure 3. If the depth of the lightly doped drain region is simply increased, the threshold voltage will drop significantly as shown in Figure 8, and the gate length will be 0.5.
Therefore, if a punch-through stopper region is formed inside the lower substrate of the lightly doped drain region as in the structure of the present invention, the short channel effect is alleviated as shown in 7. Therefore, the structure of the present invention satisfies the requirements of high breakdown voltage and mitigation of the short channel effect at the same time.

Here, it is better to form the channel stopper region only under the drain and source regions. this is.

This is to prevent the substrate effect constant of the MOS transistor from increasing. Further, in terms of process, it is only necessary to add one impurity introduction step to the conventional LDD structure without increasing the number of masks, and it can be easily formed.

〔Example〕

Example 1 The outline of the manufacturing process will be described below as a first example of the present invention with reference to FIG.

First, as shown in FIG. 5(a), after selectively forming an element isolation region on a p-type 10Ω-■ silicon substrate 1, a gate oxide film 2 is formed.
After forming a polycrystalline silicon film doped with phosphorus at a high concentration, a silicide film, or a composite film 3 of these to a thickness of about 400 nm, these are selectively left by photoetching to form a gate electrode 3. form. Then, using this gate electrode 3 as a mask, boron is implanted at 100 keV and approximately (1 to 10) x 1018 as-'' to form a punch-through stopper region 5 with a self-alignment line.At this time, in order to prevent boron from passing through the gate electrode, Depending on the material of the gate electrode, an insulating film, for example, a 5iOz film may be coated upon formation of the electrode to form a two-layer gate electrode.

Next, as shown in (b), using the gate electrode 3 as a mask, phosphorus is applied at a voltage of, for example, 100KsV (1~1.0X1018CI11-"
A low concentration diffusion layer 4 is formed by implantation and subsequent heat treatment. The peak concentration of the low concentration diffusion layer is approximately I x 10
"cs-8, the depth of the diffusion layer was approximately 0.25 μm at the boundary with the punch-through stopper region.

Next, after devoting the oxide film to a thickness of 300 to 400 nm, side spacers 2 were formed at the step portion of the gate electrode as shown in (C) by reactive ion etching (RIE). At this time, the width of the side spacer was approximately 0.3 to 0.4 μm. Thereafter, arsenic is e.g. 80KeV, 5
-" A high concentration diffusion layer was formed by implantation and heat treatment. The depth of the diffusion layer at this time was approximately 0.2 μm. After this, an interlayer insulating film was coated, and a contact hole was formed.
Complete by forming aluminum wiring.

As described above, the process of the structure of the present invention is similar to that of the conventional L D
D Only one ion implantation step is added to the structure process.

Embodiment 2 Next, another embodiment of the present invention will be described using FIGS. 6.7 and 8.9.

In the structure shown in FIG. 6, the depth of the low concentration diffusion NJ4 is made shallow, and the punch-through stopper region 5 is also formed shallow. As a result, the short channel effect can be further suppressed. However, since the high concentration diffusion layer 6 and the punch-through stopper region are in direct contact with each other, the junction capacitance increases somewhat.

Further, in the structure shown in FIG. 7, after forming the low concentration diffusion layer 4', another low concentration diffusion layer 11 of the same conductivity type is formed. The low concentration diffusion layer 11 is formed by forming the low concentration diffusion layer of the LDD structure deep within the substrate, thereby reducing the substrate surface concentration and suppressing an increase in the hot carrier deterioration mode specific to the LDD structure. This low concentration diffusion layer 11
For example, arsenic is 50~l O0KeV10"~10"Q
l'''! Can be formed by ion implantation.

Furthermore, the structure shown in FIG. 8 further limits the shape of the punch-through stopper region 5 in the structure of the present invention. Basically, if the bunt-through stopper region 5 is provided only at the end of the low concentration diffusion layer 4 as shown in FIG. 8, the above-mentioned effect can be obtained.

With this structure, the increase in extra junction capacitance can be minimized.

The structure shown in FIG. 9 has the punch-through stopper region 5 formed deep within the wafer over the entire surface, and is most effective in suppressing the short channel effect.

However, since a punch-through stopper is also formed in the region below the gate electrode, it is preferable that the punch-through stopper be formed as deep as possible from the semiconductor substrate surface to prevent an increase in the substrate effect constant, etc. ,
The punch-through stopper region 5 of this embodiment contains 20% boron.
A desired punch-through stopper can be formed by ion implantation with high energy of 0Key or higher.

〔Effect of the invention〕

According to the present invention, the performance of the conventional high-voltage LDD structure can be greatly improved, and future ULSI
(Ultra Large 5cale Inte
It is very effective as a basic device for glation.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a structure showing the first embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional structure, FIG. 3 is a diagram showing the gate length dependence of threshold voltage, and FIG. FIG. 5 is a diagram showing the dependence of carrier breakdown voltage on gate length, FIG. 5 is a diagram showing the process flow of the first embodiment of the present invention, and FIGS. 6 to 9 are diagrams showing structures of other embodiments of the present invention. FIG. 1... Semiconductor substrate, 2... Insulating film, 3... Game]
- Electrode, 4...Low concentration diffusion layer, 5...Diffusion layer for punch-through stopper, 6...High concentration diffusion layer, 7, 8...
・Threshold voltage, 9.1o...Hot carrier withstand voltage, 11
...Low concentration diffusion layer. : ] j : ノ Figure 2y 5 / Zusu person Lust / Mu) Drop g Takano 哓Gomoshikino 3rd country grass 4 concavity 6th figure 7 figure 2 calyx q figure

Claims (1)

[Claims] 1. In a MIS field effect transistor formed on a first conductivity type semiconductor substrate, at least one of the source and the drain is: i) in contact with the substrate surface and not directly under the gate conductor; ii) a second semiconductor region of a second conductivity type with a low concentration that is in contact with the substrate surface and the first semiconductor region and reaches directly below the gate conductor; iii) A semiconductor device comprising: a third semiconductor region of a first conductivity type that is in contact with at least one of the first and second semiconductor regions and is present only inside the substrate and has a higher concentration than the substrate. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a location giving a maximum value of impurity concentration distribution in the second semiconductor region is inside the substrate. 3. In the semiconductor device according to claim 2,
A semiconductor device characterized in that a second semiconductor region surrounds a first semiconductor region.