JPS63263767A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63263767A
JPS63263767A JP9739587A JP9739587A JPS63263767A JP S63263767 A JPS63263767 A JP S63263767A JP 9739587 A JP9739587 A JP 9739587A JP 9739587 A JP9739587 A JP 9739587A JP S63263767 A JPS63263767 A JP S63263767A
Authority
JP
Japan
Prior art keywords
substrate
diffusion layer
region
concentration
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9739587A
Other languages
Japanese (ja)
Inventor
Akihiro Shimizu
昭博 清水
Yoshio Sakai
芳男 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP9739587A priority Critical patent/JPS63263767A/en
Publication of JPS63263767A publication Critical patent/JPS63263767A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize a low concentrated drain structure of high breakdown strength which is remarkably improved in performance by a method wherein impurity of a low concentrated diffusion layer is so distributed as to be maxi mum inside a substrate in value and a diffusion layer region of the same conduc tivity type as the substrate, which is higher than the substrate in concentration, is provided inside the substrate under a low and a high concentrated diffusion layer. CONSTITUTION:Phosphorous is injected at 100 keV through a gate electrode serving as a mask and thereafter heat treatment is performed for the formation of a low concentrated diffusion layer 4. The low concentrated diffusion layer 4 is about 1X10<13>cm<-3> at its maximum in concentration, about 0.25mum in depth and bounded by a puch-through-stopper region. Thereafter, arsenic is injected, for example, to 5X10<15> cm<-2> at 80 keV, and a high concentration diffused layer 6 is formed. The depth of the diffused layer is about 0.2 mum. Thereafter, an interlaminar insulating film 2 is spread and a contact hole is provided, then the process is completed after an aluminum wiring is built. Thereby, a device can be realized which is high in breakdown strength and alleviated in a short channel effect at the same time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に係り、特に微細なMIS型電界
効果トランジスタの高信頼度化に好適で、耐ホツトキャ
リア、耐短チヤネル効果のすぐれたMIS型電界効果ト
ランジスタに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and is particularly suitable for increasing the reliability of a fine MIS type field effect transistor, and has excellent hot carrier resistance and short channel effect resistance. The present invention relates to a MIS type field effect transistor.

〔従来の技術〕[Conventional technology]

従来のMIS型電界効果トランジスタは、ゲート長が短
くなるに従い、動作時のドレイン近傍の電界が非常に大
きくなり、短チヤネル効果の増大、ホットキャリア注入
による特性劣化等の信頼性の低下が非常に大きな問題と
なっている。
In conventional MIS type field effect transistors, as the gate length becomes shorter, the electric field near the drain during operation becomes extremely large, resulting in a significant decrease in reliability due to increased short channel effects and characteristic deterioration due to hot carrier injection. This has become a big problem.

これを防ぎ、信頼性、特に耐圧を向上させる構造として
は種々のものが考えられているが、イミクロンレベルで
有力なものに米国特許4356623号に記載のように
、高濃度拡散層をゲートよりオフセットさせ、その間に
低濃度拡散層を設けた低濃度ドレイン(Lightly
 Doped Drain、略してLDD)構造があげ
られる。また、さらに、短チヤネル効果を緩和する構造
としては、アイ、イー、ディー、エム、テクニカル、ダ
イジェスト(1982年)第718項から第719項(
I E D M TechnicalDigest (
1982) P P 718−719 )に記載の様に
、LDD構造の低濃度拡散層の周囲にパンチスルースト
ッパー領域(Pポケット)を設けたものがあり、これを
第2図に示す。
Various structures have been considered to prevent this and improve reliability, especially withstand voltage, but one of the most promising structures at the Imicron level is the one described in U.S. Pat. A lightly doped drain (Lightly) is offset and has a lightly doped diffusion layer between
An example is a doped drain (LDD) structure. Furthermore, as a structure for alleviating the short channel effect, I, E, D, M, Technical Digest (1982), paragraphs 718 to 719 (
I E D M Technical Digest (
1982) PP 718-719), there is one in which a punch-through stopper region (P pocket) is provided around a low concentration diffusion layer of an LDD structure, and this is shown in FIG.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術でさらに微細なサブミクロン領域の素子を
構成すると、1)耐圧の向上度が足りない、2)短チヤ
ネル効果が厳しくなるという問題があった。
When using the above-mentioned conventional technology to construct a finer element in the submicron region, there are problems that 1) the degree of improvement in breakdown voltage is insufficient, and 2) the short channel effect becomes severe.

従来技術であるLDD構造では、ゲート長をサブミクロ
ン領域まで短くすると、短チヤネル効果が激しくなり、
本構造での耐圧向上量では信頼性も不定する。また、第
2図に示したチャネルストッパ領域材では確かに短チヤ
ネル効果は抑えられるが、低濃度領域の周囲全体にチャ
ネルストッパ領域があるため、内部電界が強くなり耐圧
の向上はあまり望めない。
In the conventional LDD structure, when the gate length is shortened to the submicron region, the short channel effect becomes severe.
Reliability is also uncertain depending on the amount of withstand voltage improvement in this structure. In addition, although the channel stopper region material shown in FIG. 2 can certainly suppress the short channel effect, since the channel stopper region is located all around the low concentration region, the internal electric field becomes strong and no improvement in breakdown voltage can be expected.

本発明の目的は、サブミクロン領域においても上記1)
、2)の問題を同時に解決しうる構造を提供することに
ある。
The purpose of the present invention is to achieve the above 1) even in the submicron region.
, 2) The objective is to provide a structure that can solve the problems at the same time.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、第1図に示す様に低濃度拡散層の不純物分
布を基板内部に最大値がくるようにし、かつ、低濃度及
び高濃度拡散層下の基板内部に基板と同一導電型で基板
より高濃度の拡散層領域(パンチスルーストッパ領域)
を設けることにより達成される。
The above purpose is to make the impurity distribution of the low concentration diffusion layer reach its maximum value inside the substrate, as shown in Figure 1, and to make the impurity distribution of the same conductivity type as the substrate inside the substrate under the low concentration and high concentration diffusion layers. Higher concentration diffusion layer region (punch-through stopper region)
This is achieved by providing

〔作用〕[Effect]

微細なMOSトランジスタにおけるホットキャリア効果
は、デバイス寸法が年々スケーリングされてきているの
に対して電源電圧が一定のままであることにより顕著と
なってきたもので、現在、ホットキャリア効果により定
まる耐圧はドレイン近傍での降伏耐圧よりも低く最も厳
しい条件となっている。第4図に各種構造におけるホッ
トキャリア耐圧のゲート長依存性を示す。ホットキャリ
ア耐圧とは伝達コンダクタンスは10年で10%変動す
るドレイン電圧で定義している。従来のシングルドレイ
ン構造12では、1μmで5vを下回っており、5vの
電源電圧ではとても使用できない、これに対し、高耐圧
構造の従来L D o f11B造10では、1μmで
7vと5vを上回っている。
The hot carrier effect in minute MOS transistors has become more prominent as the power supply voltage remains constant while the device dimensions have been scaling year by year.Currently, the withstand voltage determined by the hot carrier effect is This is the most severe condition as it is lower than the breakdown voltage near the drain. FIG. 4 shows the dependence of hot carrier breakdown voltage on gate length in various structures. Hot carrier withstand voltage is defined as a drain voltage whose transfer conductance fluctuates by 10% in 10 years. In the conventional single drain structure 12, the voltage is less than 5V at 1 μm and cannot be used at a power supply voltage of 5V.On the other hand, in the conventional LDOF11B structure 10 with a high withstand voltage structure, the voltage is less than 7V and 5V at 1 μm. There is.

しかし、このLDD構造10でも例えばゲート長が0.
5μmになると耐圧が不足している。従来LDD構造の
低濃度ドレイン領域を基板内部に深く形成すると、ホッ
トキャリアの発生部が基板内部に移りゲートへの注入量
が減少する。しかるに、ホットキャリア耐圧9は、従来
LDDifR造10よのも向上し、0.5μm レベル
でも5Vffi源で使用可能となる。
However, even in this LDD structure 10, for example, the gate length is 0.
When the thickness becomes 5 μm, the withstand voltage is insufficient. When the low concentration drain region of the conventional LDD structure is formed deep inside the substrate, the generation part of hot carriers moves to the inside of the substrate, and the amount of injection into the gate decreases. However, the hot carrier breakdown voltage 9 is improved compared to the conventional LDDifR structure 10, and it can be used as a 5Vffi source even at the 0.5 μm level.

また、このように低濃度ドレイン領域の深さを大きくす
ると一般に短チヤネル効果が激しくなり、閾値電圧がゲ
ート長の短い所で大きく低下してしまう。この様子を第
3図に示す、低濃度ドレイン領域の深さを単に大きくす
ると8のように閾値電圧の低下が大きくゲート長0.5
μmではとても使用できない、そこで、本発明の構造の
如く、低濃度ドレイン領域の下部基板内部にパンチスル
ーストッパ領域を形成すると7の様に短チヤネル効果が
緩和される。故に、本発明の構造は、高耐圧化と短チヤ
ネル効果の緩和を同時な満たしている。
Furthermore, when the depth of the lightly doped drain region is increased in this manner, the short channel effect generally becomes severe, and the threshold voltage is greatly reduced at a short gate length. This situation is shown in Figure 3. If the depth of the lightly doped drain region is simply increased, the threshold voltage will drop significantly as shown in Figure 8, and the gate length will be 0.5.
Therefore, if a punch-through stopper region is formed inside the lower substrate of the lightly doped drain region as in the structure of the present invention, the short channel effect is alleviated as shown in 7. Therefore, the structure of the present invention satisfies the requirements of high breakdown voltage and mitigation of the short channel effect at the same time.

ここでチャネルストッパ領域は、ドレイン、ソース領域
の下部にのみ形成した方が良い。これは。
Here, it is better to form the channel stopper region only under the drain and source regions. this is.

MOSトランジスタの基板効果定数を大きくさせないた
めである。また、プロセス的には従来LDD構造にマス
クの増加なしに不純物導入工程を1回加えるだけでよく
、容易に形成可能である。
This is to prevent the substrate effect constant of the MOS transistor from increasing. Further, in terms of process, it is only necessary to add one impurity introduction step to the conventional LDD structure without increasing the number of masks, and it can be easily formed.

〔実施例〕〔Example〕

実施例1 以下に本発明の第1の実施例として製造工程の概略を第
5図を用いて説明する。
Example 1 The outline of the manufacturing process will be described below as a first example of the present invention with reference to FIG.

まず、第5図(a)の如くp型10Ω−■シリコン基板
1上に選択的に素子分離領域を形成後、ゲート酸化膜2
を5〜50nm程度形成し、その上に高濃度にリンをド
ープした多結晶シリコン膜やシリサイド膜或いはそれら
の複合膜3を400nm程度被膜後、これらをフォトエ
ツチングにより選択的に残し、ゲート電極3を形成する
。その後、このゲート電極3をマスクにボロンを例えば
100keV、(1〜10) X 1018as−”程
度打込み、セルファラインでパンチスルーストッパ領域
5を形成する。この時、ボロンがゲート電極を通り抜け
ないために、ゲート電極の材料によっては、電極形成時
に絶縁膜、例えば5iOz膜を被膜しゲート電極を2層
膜とすればよい。
First, as shown in FIG. 5(a), after selectively forming an element isolation region on a p-type 10Ω-■ silicon substrate 1, a gate oxide film 2 is formed.
After forming a polycrystalline silicon film doped with phosphorus at a high concentration, a silicide film, or a composite film 3 of these to a thickness of about 400 nm, these are selectively left by photoetching to form a gate electrode 3. form. Then, using this gate electrode 3 as a mask, boron is implanted at 100 keV and approximately (1 to 10) x 1018 as-'' to form a punch-through stopper region 5 with a self-alignment line.At this time, in order to prevent boron from passing through the gate electrode, Depending on the material of the gate electrode, an insulating film, for example, a 5iOz film may be coated upon formation of the electrode to form a two-layer gate electrode.

次に、(b)の如くゲート電極3をマスクにリンを例え
ば100KsV、(1〜1.0X1018CI11−”
打込み、その後の熱処理により低濃度拡散層4を形成す
る。低濃度拡散層のピーク濃度はおよそI X 10 
”cs−8、拡散層深さは上記パンチスルーストッパ領
域との境界であり約0.25μmとなった。
Next, as shown in (b), using the gate electrode 3 as a mask, phosphorus is applied at a voltage of, for example, 100KsV (1~1.0X1018CI11-"
A low concentration diffusion layer 4 is formed by implantation and subsequent heat treatment. The peak concentration of the low concentration diffusion layer is approximately I x 10
"cs-8, the depth of the diffusion layer was approximately 0.25 μm at the boundary with the punch-through stopper region.

次に、酸化膜を300〜400nmデボ後、反応性イオ
ンエツチング(RI E)により(C)の如くゲート電
極段差部にサイドスペーサ2を形成した。この時、サイ
ドスペーサの幅は約0.3〜0.4μmとなった。その
後、ヒ素を例えば80KeV、5 X 1011San
−”打込み、熱処理により高濃度拡散層を形成した。こ
の時の拡散層深さは、およそ0.2μmであった。この
後は、層間絶縁膜を被膜し、コンタクトホール形成後、
アルミニウム配線を形成して完成する。
Next, after devoting the oxide film to a thickness of 300 to 400 nm, side spacers 2 were formed at the step portion of the gate electrode as shown in (C) by reactive ion etching (RIE). At this time, the width of the side spacer was approximately 0.3 to 0.4 μm. Thereafter, arsenic is e.g. 80KeV, 5
-" A high concentration diffusion layer was formed by implantation and heat treatment. The depth of the diffusion layer at this time was approximately 0.2 μm. After this, an interlayer insulating film was coated, and a contact hole was formed.
Complete by forming aluminum wiring.

以上の様に、本発明構造のプロセスは、従来のL D 
D 構造プロセスに、イオン打込み工程が1つ加わった
だけである。
As described above, the process of the structure of the present invention is similar to that of the conventional L D
D Only one ion implantation step is added to the structure process.

実施例2 次に、本発明の他の実施例を第6.7,8.9図を用い
て説明する。
Embodiment 2 Next, another embodiment of the present invention will be described using FIGS. 6.7 and 8.9.

第6図に示した構造は、低濃度拡散NJ4の深さを浅く
シ、かつ、パンチスルーストッパー領域5をも浅く形成
したものである。これにより、短チヤネル効果は一層抑
えられることになる。しかし、高濃度拡散層6とパンチ
スルーストッパ領域が直に接している為、接合容量が多
少増大することになる。
In the structure shown in FIG. 6, the depth of the low concentration diffusion NJ4 is made shallow, and the punch-through stopper region 5 is also formed shallow. As a result, the short channel effect can be further suppressed. However, since the high concentration diffusion layer 6 and the punch-through stopper region are in direct contact with each other, the junction capacitance increases somewhat.

また、第7図に示した構造は、低濃度拡散層4を形成し
た′後に、さらに同導電型で別の低濃度拡散層11を形
成した。低濃度拡散層11は、LDD構造の低濃度拡散
層を基板内深く形成したことにより、基板表面濃度が低
下し、LDD構造固有のホットキャリア劣化モードの増
大することを抑えたものである。この低濃度拡散層11
は例えばヒ素を50〜l O0KeV10”〜10”Q
l’″!イオン打込みすることにより形成することがで
きる。
Further, in the structure shown in FIG. 7, after forming the low concentration diffusion layer 4', another low concentration diffusion layer 11 of the same conductivity type is formed. The low concentration diffusion layer 11 is formed by forming the low concentration diffusion layer of the LDD structure deep within the substrate, thereby reducing the substrate surface concentration and suppressing an increase in the hot carrier deterioration mode specific to the LDD structure. This low concentration diffusion layer 11
For example, arsenic is 50~l O0KeV10"~10"Q
l'''! Can be formed by ion implantation.

さらに、第8図に示した構造は本発明の構造におけるパ
ンチスルーストッパ領域5の形状をさらに限定したもの
である。バントスルーストッパ領域5としては、基本的
には第8図のように低濃度拡散層4端にのみあれば前述
の効果が得られる。
Furthermore, the structure shown in FIG. 8 further limits the shape of the punch-through stopper region 5 in the structure of the present invention. Basically, if the bunt-through stopper region 5 is provided only at the end of the low concentration diffusion layer 4 as shown in FIG. 8, the above-mentioned effect can be obtained.

本構造では、余分な接合容量の増大を極力小さくするこ
とができる。
With this structure, the increase in extra junction capacitance can be minimized.

第9図に示した構造はパンチスルーストッパ領域5をウ
ェハ内深部に全面に形成したものであり、短チャンネル
効果を抑制する効果は最も大きい。
The structure shown in FIG. 9 has the punch-through stopper region 5 formed deep within the wafer over the entire surface, and is most effective in suppressing the short channel effect.

但し、ゲート電極下の領域にもパンチスルーストッパが
形成されているため、基板効果定数などの増加を防ぐよ
うに、パンチスルーストッパはできるだけ半導体基板表
面から深く形成されているのが好ましい、そのために、
本実施例のパンチスルーストッパ領域5はボロンを20
0Key以上の高いエネルギーでイオン打込みすること
により所望のパンチスルーストッパが形成できる。
However, since a punch-through stopper is also formed in the region below the gate electrode, it is preferable that the punch-through stopper be formed as deep as possible from the semiconductor substrate surface to prevent an increase in the substrate effect constant, etc. ,
The punch-through stopper region 5 of this embodiment contains 20% boron.
A desired punch-through stopper can be formed by ion implantation with high energy of 0Key or higher.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、従来の高耐圧構造のLDD構造の性能
を大きく向上させることができ、将来のU L S I
  (Ultra Large 5cale Inte
glation)の基本デバイスとして非常に有効であ
る。
According to the present invention, the performance of the conventional high-voltage LDD structure can be greatly improved, and future ULSI
(Ultra Large 5cale Inte
It is very effective as a basic device for glation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示す構造の断面図、第
2図は従来構造の断面図、第3図は閾値電圧のゲート長
依存性を示した図、第4図はホットキャリア耐圧のゲー
ト長依存性を示した図、第5図は本発明の第1の実施例
のプロセスフローを示す図、第6図乃至第9図は本発明
の他の実施例を示す構造の断面図である。 1・・・半導体基板、2・・・絶縁膜、3・・・ゲー]
−電極、4・・・低濃度拡散層、5・・・パンチスルー
ストッパ用拡散層、6・・・高濃度拡散層、7,8・・
・閾値電圧、9.1o・・・ホットキャリア耐圧、11
・・・低濃度拡散層。 :]j: ノ 図 平2y 5  /ず〉す人ル−ストー/ム)雫 g 高濃屓込敷乃 第 3国 茅4凹 第 6図 第7図 第2図 萼 q 図
FIG. 1 is a cross-sectional view of a structure showing the first embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional structure, FIG. 3 is a diagram showing the gate length dependence of threshold voltage, and FIG. FIG. 5 is a diagram showing the dependence of carrier breakdown voltage on gate length, FIG. 5 is a diagram showing the process flow of the first embodiment of the present invention, and FIGS. 6 to 9 are diagrams showing structures of other embodiments of the present invention. FIG. 1... Semiconductor substrate, 2... Insulating film, 3... Game]
- Electrode, 4...Low concentration diffusion layer, 5...Diffusion layer for punch-through stopper, 6...High concentration diffusion layer, 7, 8...
・Threshold voltage, 9.1o...Hot carrier withstand voltage, 11
...Low concentration diffusion layer. : ] j : ノ Figure 2y 5 / Zusu person Lust / Mu) Drop g Takano 哓Gomoshikino 3rd country grass 4 concavity 6th figure 7 figure 2 calyx q figure

Claims (1)

【特許請求の範囲】 1、第1導電型半導体基板上に形成されたMIS型電界
効果トランジスタにおいて、該ソース、ドレインの少な
くとも一方が、 i)基板表面に接し、ゲート導体直下にはない高濃度で
第2導電型の第1半導体領域、 ii)基板表面及び第1半導体領域に接し、ゲート導体
直下まで達する低濃度で第2導電型の第2半導体領域。 iii)第1及び第2半導体領域の少なくとも一方に接
し、基板内部にのみ存在する基板より高濃度の第1導電
型の第3半導体領域、 から成ることを特徴とする半導体装置。 2、特許請求の範囲第1項記載の半導体装置において、
第2半導体領域の不純物濃度分布の最大値を与える所が
基板内部にあることを特徴とする半導体装置。 3、特許請求の範囲第2項記載の半導体装置において、
第2半導体領域が第1半導体領域を囲んでいることを特
徴とする半導体装置。
[Claims] 1. In a MIS field effect transistor formed on a first conductivity type semiconductor substrate, at least one of the source and the drain is: i) in contact with the substrate surface and not directly under the gate conductor; ii) a second semiconductor region of a second conductivity type with a low concentration that is in contact with the substrate surface and the first semiconductor region and reaches directly below the gate conductor; iii) A semiconductor device comprising: a third semiconductor region of a first conductivity type that is in contact with at least one of the first and second semiconductor regions and is present only inside the substrate and has a higher concentration than the substrate. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a location giving a maximum value of impurity concentration distribution in the second semiconductor region is inside the substrate. 3. In the semiconductor device according to claim 2,
A semiconductor device characterized in that a second semiconductor region surrounds a first semiconductor region.
JP9739587A 1987-04-22 1987-04-22 Semiconductor device Pending JPS63263767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9739587A JPS63263767A (en) 1987-04-22 1987-04-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9739587A JPS63263767A (en) 1987-04-22 1987-04-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63263767A true JPS63263767A (en) 1988-10-31

Family

ID=14191327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9739587A Pending JPS63263767A (en) 1987-04-22 1987-04-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63263767A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453461A (en) * 1987-05-19 1989-03-01 Seiko Epson Corp Semiconductor device and manufacture thereof
JPH0191466A (en) * 1987-10-02 1989-04-11 Fujitsu Ltd Semiconductor device
JPH0254537A (en) * 1988-08-18 1990-02-23 Seiko Epson Corp Semiconductor device and manufacture thereof
JPH0653232A (en) * 1992-08-03 1994-02-25 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH06252374A (en) * 1992-12-28 1994-09-09 Sharp Corp Solid-state image pickup device
JP2010087149A (en) * 2008-09-30 2010-04-15 Nec Electronics Corp Semiconductor device and method of manufacturing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453461A (en) * 1987-05-19 1989-03-01 Seiko Epson Corp Semiconductor device and manufacture thereof
JPH0191466A (en) * 1987-10-02 1989-04-11 Fujitsu Ltd Semiconductor device
JPH0254537A (en) * 1988-08-18 1990-02-23 Seiko Epson Corp Semiconductor device and manufacture thereof
JPH0653232A (en) * 1992-08-03 1994-02-25 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH06252374A (en) * 1992-12-28 1994-09-09 Sharp Corp Solid-state image pickup device
JP2010087149A (en) * 2008-09-30 2010-04-15 Nec Electronics Corp Semiconductor device and method of manufacturing same

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