JPH0191466A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0191466A JPH0191466A JP24924987A JP24924987A JPH0191466A JP H0191466 A JPH0191466 A JP H0191466A JP 24924987 A JP24924987 A JP 24924987A JP 24924987 A JP24924987 A JP 24924987A JP H0191466 A JPH0191466 A JP H0191466A
- Authority
- JP
- Japan
- Prior art keywords
- source
- drain region
- layer
- semiconductor substrate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005669 field effect Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
Abstract
Description
【発明の詳細な説明】
〔概要〕
短チャ゛ネル電界効果トランジスタを有する半導体装置
の構造に関し。DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to the structure of a semiconductor device having a short channel field effect transistor.
短チヤネルＦＥＴ０高耐圧、高速性を実現する構造を得
ることを目的とし。The aim is to obtain a short channel FET0 structure that achieves high withstand voltage and high speed.
半導体基板上に形成されたゲート電極と、該ゲート電極
の両側において該半導体基板内に形成されたソースドレ
イン領域と、該半導体基板内において少なくとも該ゲー
ト電極の下部に該ソースドレイン領域および該半導体基
板表面より離れて形成され、かつ該半導体基板と同一導
電型で該半導体基板より濃度の高い不純物導入層とを有
するように構成する。前記半導体基板がＳｉ基板からな
る場合は、前記不純物導入層はソースドレイン領域より
０．１μｍ以上離れて形成され、かつ不純物導入層とソ
ースドレイン領域間の不純物濃度が１０１）０ｌ８″以
下であるように構成する。a gate electrode formed on a semiconductor substrate; a source drain region formed in the semiconductor substrate on both sides of the gate electrode; and a source drain region and the semiconductor substrate at least below the gate electrode in the semiconductor substrate. It is configured to have an impurity-introduced layer that is formed at a distance from the surface, has the same conductivity type as the semiconductor substrate, and has a higher concentration than the semiconductor substrate. When the semiconductor substrate is made of a Si substrate, the impurity-introduced layer is formed at least 0.1 μm apart from the source/drain region, and the impurity concentration between the impurity-introduced layer and the source/drain region is 101)0l8″ or less. Configure.
本発明は短チヤネル電界効果トランジスタ（ＦＥＴ）を
有する半導体装置の構造に関する。The present invention relates to the structure of a semiconductor device having a short channel field effect transistor (FET).
ｒｃの高速化、高官変化の要望より、短チャネルＰＥＴ
の開発が各所で活発に行われている。Short channel PET due to higher speed of RC and demands of changes in high-ranking officials
Development is being actively carried out in various places.
しかしながら、 ＦＥＴ、例えばＭＯＳ ＦＥＴを微細
化するため、ゲート（チャネル）長を短くしてゆくと。However, in order to miniaturize FETs, such as MOS FETs, the gate (channel) length is shortened.
ソース／ドレイン間が空乏層で連絡し、パンチスルー電
流が流れるようになるため、この対策が必要となる。This measure is necessary because the source/drain is connected through a depletion layer and a punch-through current flows.
第３図は従来例によるパンチスルーを防止したＦＢＴの
断面図である。FIG. 3 is a sectional view of a conventional FBT that prevents punch-through.
図において、１はＳｉ基板、２はゲート電極、３はゲー
ト絶縁層、４，５はソースドレイン領域。In the figure, 1 is a Si substrate, 2 is a gate electrode, 3 is a gate insulating layer, and 4 and 5 are source/drain regions.
ＩＡは高濃度不純物導入層である。IA is a layer into which high concentration impurities are introduced.
ゲート長が１μｍ程度の短チャネルＦＥＴにおいては、
ドレイン領域より延びてきた空乏層により等電位面の鞍
部が基板内部に形成されるため、パンチスルー電流はゲ
ート下のチャネル形成部の基板表面から０．２μｍ程度
深い部分を流れることが確認されている。In a short channel FET with a gate length of about 1 μm,
Because a saddle of an equipotential surface is formed inside the substrate by the depletion layer extending from the drain region, it has been confirmed that the punch-through current flows approximately 0.2 μm deep from the substrate surface in the channel formation area under the gate. There is.
このパンチスルー電流を防止するため、基板と同じ導電
型の高温度不純物導入層１八をチャネル形成部の下に形
成する構造が知られている。In order to prevent this punch-through current, a structure is known in which a high-temperature impurity-introduced layer 18 of the same conductivity type as the substrate is formed under the channel forming portion.
この高濃度層により、空乏層の拡がりは阻止され、従っ
てバンチスルー電流は阻止される。This highly doped layer prevents the depletion layer from expanding and therefore bunch-through current.
この場合１例えば、ソースドレイン領域の濃度を〜１０
２０ｃｍ−３．基板濃度を〜１０ ” ｃｍ−’として
、高濃度不純物導入層ＩＡの濃度は〜１０１８ｃｍ”’
にする。In this case 1, for example, the concentration of the source/drain region is ~10
20cm-3. Assuming that the substrate concentration is ~10"cm-', the concentration of the high-concentration impurity-introduced layer IA is ~1018 cm"'
Make it.
しかし、従来例の構造では高濃度不純物導入層ＩＡがソ
ースドレイン領域４．５と接するために次の欠点をもつ
。However, the conventional structure has the following drawbacks because the heavily doped layer IA is in contact with the source/drain region 4.5.
■ ソースドレイン領域と基板間で形成するｐｎ接合の
耐圧が低下・し、高いソースドレイン耐圧と高い接合耐
圧を同時に得ることはできなかった。(2) The breakdown voltage of the pn junction formed between the source/drain region and the substrate decreased, and it was not possible to obtain a high source/drain breakdown voltage and a high junction breakdown voltage at the same time.
■ 接合容量が増加し、デバイスの高速性を阻害する。■ Junction capacitance increases, impeding device speed.
従って９本発明は短チャネルＦＥＴの高耐圧、高速性を
実現する構造を得ることを目的とする。Therefore, the object of the present invention is to obtain a structure that realizes high breakdown voltage and high speed performance of a short channel FET.
上記問題点の解決は、半導体基板上に形成されたゲート
電極と、該ゲート電極の両側において該半導体基板内に
形成されたソースドレイン領域と。A solution to the above problem is a gate electrode formed on a semiconductor substrate, and source/drain regions formed in the semiconductor substrate on both sides of the gate electrode.
該半導体基板内において少なくとも該ゲート電極の下部
に該ソースドレイン領域および該半導体基板表面より離
れて形成され、かつ該半導体基板と同一導電型で該半導
体基板より濃度の高い不純物導入層とを有する半導体装
置によって達成される。A semiconductor comprising, in the semiconductor substrate, at least below the gate electrode, the source/drain region and an impurity-introduced layer that is formed at a distance from the surface of the semiconductor substrate and has the same conductivity type as the semiconductor substrate and has a higher concentration than the semiconductor substrate. achieved by the device.
前記半導体基板がＳｉ基板からなる場合は、前記不純物
導入層はソースドレイン領域より０．１μｍ以上離れて
形成され、かつ不純物導入層とソースドレイン領域間の
不純物濃度が１０１８ｃｍ−’以下であればよい。When the semiconductor substrate is made of a Si substrate, the impurity-introduced layer may be formed at a distance of 0.1 μm or more from the source/drain region, and the impurity concentration between the impurity-introduced layer and the source/drain region is 10 cm -' or less. .
この数値限定は、オフセソｌ−（ＬＤＤ）構造のソース
ドレイン領域の低濃度部が１０″８ｃｍ−”程度である
ので、不純物４人層とソースドレイン領域間はこれより
低濃度であることが必要であり、かつ濃度が１０ ＋
ｓ ｃ ｍ −３の場合は接合に１０ Ｖの逆バイアス
をかけたときの空乏層の拡がりは約０．１μｍであるこ
とより行った。This numerical limitation is because the low concentration part of the source/drain region of the offset L-(LDD) structure is about 10"8cm-", so the concentration between the 4-layer impurity layer and the source/drain region must be lower than this. and the concentration is 10 +
In the case of s cm -3, this was done based on the fact that the depletion layer spreads by about 0.1 μm when a reverse bias of 10 V is applied to the junction.
本発明はパンチスルー防止用の高濃度不純物導入層をソ
ースドレイン領域より離して形成することにより、従来
両者を接して形成した場合に発生した接合耐圧の低下と
接合容量の増加を防止したものである。The present invention prevents a decrease in junction breakdown voltage and an increase in junction capacitance that conventionally occur when the two are formed in contact by forming a high-concentration impurity-introduced layer for punch-through prevention away from the source and drain regions. be.
第１図は本発明の一実施例によるパンチスルーを防止し
たＦＥＴの断面図である。FIG. 1 is a sectional view of an FET that prevents punch-through according to an embodiment of the present invention.
図において、１はＳｉ基板、２はゲート電極、３はゲー
ト絶縁層、４．５はソースドレイン領域。In the figure, 1 is a Si substrate, 2 is a gate electrode, 3 is a gate insulating layer, and 4.5 is a source/drain region.
ＩＢは高濃度不純物導入層である。IB is a layer into which high concentration impurities are introduced.
従来例と異なる点は、ソースドレイン領域４゜５を浅く
形成し、高濃度不純物導入７１）Ｂをソースドレイン領
域４，５より０．１μｍ以上離して形成した点である。The difference from the conventional example is that the source/drain regions 4.degree.
この場合にも従来例と同様に１例えば、ソースドレイン
領域の濃度を〜１０１８ｃｍ−’＋基板濃度を〜１０Ｉ
５０「３として、高濃度不純物導入層ＩＢの濃度は〜ｌ
Ｏ”ｃｍ−”にする。In this case, as in the conventional example, for example, the concentration of the source/drain region is ~1018cm-'+the substrate concentration is ~10I
50"3, the concentration of the high concentration impurity introduced layer IB is ~l
Set it to O"cm-".
ソースドレイン領域と高濃度不純物導入層１８間の濃度
は〜１０１）０ｌ８”以下である。The concentration between the source/drain region and the high concentration impurity introduced layer 18 is ~101)0l8'' or less.
具体的に不純物導入層とソースドレイン領域を離して形
成する構造を得るための実施例を説明する。Specifically, an example will be described for obtaining a structure in which an impurity-introduced layer and a source/drain region are formed apart from each other.
■ ソースドレイン領域を浅く形成する。■ Form source/drain regions shallowly.
（ａｌ 低加速イオン注入
例えば、 Ａｓ＋をエネルギ３５ ＫｅＶ （従来は〜
８０ＫｅＶ） ＋ ドーズ量ＩＥ１５ ｃｏｄ−”で
注入する。(al Low acceleration ion implantation For example, As+ is implanted at an energy of 35 KeV (conventionally ~
80KeV) + implanted at a dose of IE15 cod-".
ｆｂｌ 注入不純物の活性化温度を下げるフラッジラ
ンプを用いたＰＴＡ（Ｒａｐｉｄ ＴｈｅｒｍａｌＡｎ
ｎｅａｌ）等の熱処理により、９５０℃以下の温度で短
時間に活性化を行い、不純物の拡散を最小限に抑える。PTA (Rapid Thermal An) using a flood lamp to lower the activation temperature of implanted impurities
neal) etc., activation is performed in a short time at a temperature of 950° C. or less, and diffusion of impurities is minimized.
■ 高濃度不純物導入層の不純物分布の拡がりを防止す
る
（ａｌ 高加速イオン注入
例えば Ｂ゛をエネルギ１５０ ＫｅＶ 、 ドーズ
量ＩＥ１３ ｃｍ−”、 レンジＲｐ ＝０．４２μ
ｍで注入する。■ Preventing the spread of the impurity distribution in the high-concentration impurity-introduced layer (Al High-acceleration ion implantation, for example, B' energy 150 KeV, dose IE 13 cm-'', range Rp = 0.42μ
Inject at m.
（ｂ） 拡散係数の小さい不純物を注入する。(b) Implanting impurities with a small diffusion coefficient.
例えば、 Ｇａ”等を用い、後工程の熱処理で拡がらな
いようにする。For example, use Ga'' or the like to prevent it from spreading during the heat treatment in the post-process.
拡散係数は、９００℃で８は２ｘｌＯ−” （μｍ／ｈ
）””であるが、 Ｇａは１ｘｌＯ−２（μｍ／ｈ）”
”と小さい。The diffusion coefficient is 2xlO-” (μm/h) at 900°C.
)"", but Ga is 1xlO-2 (μm/h)"
” and small.
（Ｃ） 注入不純物の活性化温度を下げる従来１００
０℃程度の熱処理を、 ＰＴＡ等を用いて９００℃程度
の温度で短時間に活性化を行い、不純物の拡散を最小限
に抑える。(C) Conventional method 100 to lower the activation temperature of implanted impurities
Heat treatment at about 0°C is activated in a short time at a temperature of about 900°C using PTA, etc. to minimize the diffusion of impurities.
■ ソースドレイン領域のかさ上げ
他の実施例を示す第２図のように、ゲートの両側に選択
エピタキシャル層６を成長した後、ソースドレイン形成
用のイオン注入を行う。(2) Raising the height of the source/drain region As shown in FIG. 2 showing another embodiment, after selective epitaxial layers 6 are grown on both sides of the gate, ion implantation for forming the source/drain is performed.
以上の方法を用いて、ソースドレイン領域と高濃度不純
物導入領域との間に、濃度が１０ ’ ８ｃｍ” ’以
下の領域を０．１μｍ以上の幅に形成する。Using the above method, a region having a concentration of 10'8 cm'' or less and a width of 0.1 μm or more is formed between the source/drain region and the high concentration impurity doped region.
このような構造では、空乏層が０．１μｍ以内しか拡が
らず、１０Ｖ以上の耐圧が実現できる。In such a structure, the depletion layer expands only within 0.1 μm, and a breakdown voltage of 10 V or more can be achieved.
以上詳細に説明したように本発明によれば、パンチスル
ー電流を防止することにより、ソースドレイン間耐圧を
上げ、同時にドレイン近傍でのアバランシェインパクト
イオン化が起こり難くなり。As described above in detail, according to the present invention, by preventing punch-through current, the withstand voltage between the source and drain is increased, and at the same time, avalanche impact ionization near the drain becomes less likely to occur.
ホットキャリアの発生を防止できる。Generation of hot carriers can be prevented.
従って、短チャネルの高速微細ＦＥＴを有する半導体装
置が得られる。Therefore, a semiconductor device having a short channel high speed fine FET can be obtained.
第１図は本発明の一実施例によるパンチスルーを防止し
たＦＥＴの断面図。
第２図は他の実施例を説明する断面図。
第３図は従来例によるパンチスルーを防止したＦＥＴの
断面図である。
図において。
１はＳｉ基板。
１Ｂは高濃度不純物導入層。
２はゲート電極。
３はゲート絶縁層。
４．５はソースドレイン領域FIG. 1 is a sectional view of an FET that prevents punch-through according to an embodiment of the present invention. FIG. 2 is a sectional view illustrating another embodiment. FIG. 3 is a sectional view of a conventional FET that prevents punch-through. In fig. 1 is a Si substrate. 1B is a layer into which high concentration impurities are introduced. 2 is the gate electrode. 3 is a gate insulating layer. 4.5 is the source drain region
Claims (2)
ト電極の両側において該半導体基板内に形成されたソー
スドレイン領域と、 該半導体基板内において少なくとも該ゲート電極の下部
に該ソースドレイン領域および該半導体基板表面より離
れて形成され、かつ該半導体基板と同一導電型で該半導
体基板より濃度の高い不純物導入層 とを有することを特徴とする半導体装置。(1) A gate electrode formed on a semiconductor substrate, a source drain region formed in the semiconductor substrate on both sides of the gate electrode, and a source drain region and a source drain region formed in the semiconductor substrate at least below the gate electrode. A semiconductor device comprising: an impurity-introduced layer formed at a distance from a surface of the semiconductor substrate, having the same conductivity type as the semiconductor substrate and having a higher concentration than the semiconductor substrate.
導入層がソースドレイン領域より０．１μｍ以上離れて
形成され、かつ前記不純物導入層とソースドレイン領域
間の不純物濃度が１０＾１＾８ｃｍ＾−＾３以下である
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。(2) The semiconductor substrate is made of a Si substrate, the impurity doped layer is formed at a distance of 0.1 μm or more from the source/drain region, and the impurity concentration between the impurity doped layer and the source/drain region is 10^1^8 cm^ 2. The semiconductor device according to claim 1, wherein: -^3 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62249249A JP2668893B2 (en) | 1987-10-02 | 1987-10-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62249249A JP2668893B2 (en) | 1987-10-02 | 1987-10-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0191466A true JPH0191466A (en) | 1989-04-11 |
| JP2668893B2 JP2668893B2 (en) | 1997-10-27 |
Family
ID=17190147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62249249A Expired - Lifetime JP2668893B2 (en) | 1987-10-02 | 1987-10-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2668893B2 (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5518072A (en) * | 1978-07-26 | 1980-02-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos semiconductor device |
| JPS56169360A (en) * | 1980-05-29 | 1981-12-26 | Sharp Corp | Semiconductor device |
| JPS5831576A (en) * | 1981-08-20 | 1983-02-24 | Matsushita Electric Ind Co Ltd | Mos type field effect transistor |
| JPS58107667A (en) * | 1981-12-21 | 1983-06-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Semiconductor integrated circuit device |
| JPS58115863A (en) * | 1981-12-28 | 1983-07-09 | Matsushita Electric Ind Co Ltd | Insulating gate type field-effect semiconductor device and manufacture thereof |
| JPS60206070A (en) * | 1984-03-29 | 1985-10-17 | Toshiba Corp | Semiconductor device |
| JPS61172372A (en) * | 1985-01-28 | 1986-08-04 | Nec Corp | Manufacture of semiconductor device |
| JPS63263767A (en) * | 1987-04-22 | 1988-10-31 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-10-02 JP JP62249249A patent/JP2668893B2/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5518072A (en) * | 1978-07-26 | 1980-02-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos semiconductor device |
| JPS56169360A (en) * | 1980-05-29 | 1981-12-26 | Sharp Corp | Semiconductor device |
| JPS5831576A (en) * | 1981-08-20 | 1983-02-24 | Matsushita Electric Ind Co Ltd | Mos type field effect transistor |
| JPS58107667A (en) * | 1981-12-21 | 1983-06-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Semiconductor integrated circuit device |
| JPS58115863A (en) * | 1981-12-28 | 1983-07-09 | Matsushita Electric Ind Co Ltd | Insulating gate type field-effect semiconductor device and manufacture thereof |
| JPS60206070A (en) * | 1984-03-29 | 1985-10-17 | Toshiba Corp | Semiconductor device |
| JPS61172372A (en) * | 1985-01-28 | 1986-08-04 | Nec Corp | Manufacture of semiconductor device |
| JPS63263767A (en) * | 1987-04-22 | 1988-10-31 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2668893B2 (en) | 1997-10-27 |
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