JP2668893B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2668893B2 JP2668893B2 JP62249249A JP24924987A JP2668893B2 JP 2668893 B2 JP2668893 B2 JP 2668893B2 JP 62249249 A JP62249249 A JP 62249249A JP 24924987 A JP24924987 A JP 24924987A JP 2668893 B2 JP2668893 B2 JP 2668893B2
- Authority
- JP
- Japan
- Prior art keywords
- source
- concentration
- drain region
- impurity
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 239000012535 impurity Substances 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 34
- 230000015556 catabolic process Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241000465531 Annea Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
〔概要〕
短チャネル電界効果トランジスタを有する半導体装置
の構造に関し,
短チャネルFETの高耐圧,高速性を実現する構造を得
ることを目的とし,
半導体基板上に形成されたゲート電極と,該ゲート電
極の両側において該半導体基板内に形成されたソースド
レイン領域と,該半導体基板内において少なくとも該ゲ
ート電極の下部に該ソースドレイン領域および該半導体
基板表面より離れて形成され,かつ該半導体基板と同一
導電型で該半導体基板より濃度の高い不純物導入層とを
有するように構成する。前記半導体基板がSi基板からな
る場合は,前記不純物導入層はソースドレイン領域より
0.1μm以上離れて形成され,かつ不純物導入層とソー
スドレイン領域間の不純物濃度が1018cm-3以下であるよ
うに構成する。
〔産業上の利用分野〕
本発明は短チャネル電界効果トランジスタ(FET)を
有する半導体装置の構造に関する。
ICの高速化,高密度化の要望より,短チャネルFETの
開発が各所で活発に行われている。
しかしながら,FET,例えばMOS FETを微細化するため,
ゲート(チャネル)長を短くしてゆくと,ソース/ドレ
イン間が空乏層で連絡し,パンチスルー電流が流れるよ
うになるため,この対策が必要となる。
〔従来の技術〕
第3図は従来例によるパンチスルーを防止したFETの
断面図である。
図において,1はSi基板,2はゲート電極,3はゲート絶縁
層,4,5はソースドレイン領域,1Aは高濃度不純物導入層
である。
ゲート長が1μm程度の短チャネルFETにおいては,
ドレイン領域より延びてきた空乏層により等電位面の鞍
部が基板内部に形成されるため,パンチスルー電流はゲ
ート下のチャネル形成部の基板表面から0.2μm程度深
い部分を流れることが確認されている。
このパンチスルー電流を防止するため,基板と同じ導
電型の高濃度不純物導入層1Aをチャネル形成部の下に形
成する構造が知られている。
この高濃度層により,空防層の拡がりは阻止され,従
ってパンチスルー電流は阻止される。
この場合,例えば,ソースドレイン領域の濃度を〜10
20cm-3,基板濃度を〜1015cm-3として,高濃度不純物導
入層1Aの濃度は〜1018cm-3にする。
〔発明が解決しようとする問題点〕
しかし,従来例の構造では高濃度不純物導入層1Aがソ
ースドレイン領域4,5と接するために次の欠点をもつ。
ソースドレイン領域と基板間で形成するpn接合の耐
圧が低下し,高いソースドレイン耐圧と高い接合耐圧を
同時に得ることはできなかった。
接合容量が増加し,デバイスの高速性を阻害する。
従って,本発明は短チャネルFETの高耐圧,高速性を
実現する構造を得ることを目的とする。
〔問題点を解決するための手段〕
上記問題点の解決は,半導体基板上に設けられたゲー
ト電極と,該ゲート電極の両側において該半導体基板内
に低濃度不純物領域と高濃度不純物領域とで構成された
ソースドレイン領域と,該半導体基板内において少なく
とも該ゲート電極および該ソースドレイン領域の下部に
該ソースドレイン領域より離れて形成され,かつ該半導
体基板と同一導電型で該半導体基板より濃度の高い不純
物導入層とを有し,
該不純物導入層は,ゲート電極の下方とソースドレイ
ン領域の下方とで同じ深さに形成され,該ソースドレイ
ン領域と該不純物導入層との間の不純物濃度は該不純物
導入層より低く,かつ該ソースドレイン領域と該不純物
導入層との間の距離は,該ソースドレイン領域と該不純
物導入層との間の不純物濃度が該ソースドレイン領域の
低濃度領域の不純物濃度と同じ濃度である場合に対し該
ソースドレイン領域に動作電圧として所定の逆バイアス
を印加したときの空乏層の広がり以上の距離に設定され
ている半導体装置により達成される。
前記半導体基板がSi基板からなる場合は,前記不純物
導入層はソースドレイン領域より0.1μm以上離れて形
成され,かつ不純物導入層とソースドレイン領域間の不
純物濃度が1018cm-3以下であればよい。
この数値限定は,オフセット(LDD)構造のソースド
レイン領域の低濃度部が1018cm-3程度であるので,不純
物導入層とソースドレイン領域間はこれより低濃度であ
ることが必要であり,かつ濃度が1018cm-3の場合は接合
に10Vの逆バイアスをかけたときの空乏層の拡がりは約
0.1μmであることより行った。
〔作用〕
本発明はパンチスルー防止用の高濃度不純物導入層を
ソースドレイン領域より離して形成することにより,従
来両者を接して形成した場合に発生した接合耐圧の低下
と接合容量の増加を防止したものである。
本発明はソースとドレイン間のパンチスルーを防止す
ることは勿論であるが,ソースドレイン領域の下側まで
高濃度不純物層が形成されているため,ホットキャリア
等の好ましくない電荷の発生を防止するとともに,たと
えこのような電荷が発生しても高濃度不純物層により電
荷を吸収し,MOS FET内の電荷を安定させる作用がある。
〔実施例〕
第1図は本発明の一実施例によるパンチスルーを防止
したFETの断面図である。
図において,1はSi基板,2はゲート電極,3はゲート絶縁
層,4,5はソースドレイン領域,1Bは高濃度不純物導入層
である。
従来例と異なる点は,ソースドレイン領域4,5を浅く
形成し,高濃度不純物導入層1Bをソースドレイン領域4,
5より0.1μm以上離して形成した点である。
この場合にも従来例と同様に,例えば,ソースドレイ
ン領域の濃度を〜1020cm-3,基板濃度を〜1015cm-3とし
て,高濃度不純物導入層1Bの濃度は〜1018cm-3にする。
ソースドレイン領域と高濃度不純物導入層1B間の濃度
は1018cm-3以下である。
具体的に不純物導入層とソースドレイン領域を離して
形成する構造を得るための実施例を説明する。
ソースドレイン領域を浅く形成する。
(a) 低加速イオン注入
例えば,As+をエネルギ35KeV(従来は〜80KeV),ドー
ズ量1E15cm-2で注入する。
(b) 注入不純物の活性化温度を下げる
フラッシランプを用いたRTA(Rapid Thermal Annea
l)等の熱処理により,950℃以下の温度で短時間に活性
化を行い,不純物の拡散を最小限に抑える。
高濃度不純物導入層の不純物分布の拡がりを防止す
る
(a) 高加速イオン注入
例えば,B+をエネルギ150KeV,ドーズ量1E13cm-2,レン
ジRp=0.42μmで注入する。
(b) 拡散係数の小さい不純物を注入する。
例えば,Ga+等を用い,後工程の熱処理で拡がらないよ
うにする。
拡散係数は,900℃でBは2×10-2(μm/h)1/2である
が,Gaは1×10-2(μm/h)1/2と小さい。
(c) 注入不純物の活性化温度を下げる
従来1000℃程度の熱処理を,RTA等を用いて900℃程度
の温度で短時間に活性化を行い,不純物の拡散を最小限
に抑える。
ソースドレイン領域のかさ上げ
他の実施例を示す第2図のように,ゲートの両側に選
択エピタキシャル層6を成長した後,ソースドレイン形
成用のイオン注入を行う。
以上の方法を用いて,ソースドレイン領域と高濃度不
純物導入領域との間に,濃度が1018cm-3以下の領域を0.
1μm以上の幅に形成する。
このような構造では,例えば,高濃度不純物導入領域
とソースドレイン間の濃度が1018cm-3のときは,空乏層
が0.1μm以内しか拡がらず,10V以上の耐圧が実現でき
る。
〔発明の効果〕
以上詳細に説明したように本発明によれば,パンチス
ルー電流を防止することにより,ソースドレイン間耐圧
を上げ,同時にドレイン近傍でのアバランシェインパク
トイオン化が起こり難くなり,ホットキャリアの発生を
防止できる。
従って,短チャネルの高速微細FETを有する半導体装
置が得られる。DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a structure of a semiconductor device having a short channel field effect transistor, a structure formed on a semiconductor substrate for the purpose of obtaining a structure that realizes high breakdown voltage and high speed of a short channel FET. A gate electrode, a source / drain region formed in the semiconductor substrate on both sides of the gate electrode, and formed at least below the gate electrode in the semiconductor substrate, apart from the source / drain region and the surface of the semiconductor substrate, Further, the semiconductor substrate has the same conductivity type as that of the semiconductor substrate and an impurity introduction layer having a higher concentration than that of the semiconductor substrate. When the semiconductor substrate is made of a Si substrate, the impurity introduction layer is formed from the source / drain region.
It is formed so as to be separated by 0.1 μm or more, and the impurity concentration between the impurity introduction layer and the source / drain region is 10 18 cm −3 or less. TECHNICAL FIELD The present invention relates to the structure of a semiconductor device having a short channel field effect transistor (FET). Due to the demand for higher speed and higher density of ICs, short channel FETs are being actively developed in various places. However, in order to miniaturize FET, for example, MOS FET,
If the gate (channel) length is shortened, the source / drain communicates with the depletion layer, and a punch-through current flows, so that this measure is required. [Prior Art] FIG. 3 is a cross-sectional view of an FET in which punch-through is prevented according to a conventional example. In the figure, 1 is a Si substrate, 2 is a gate electrode, 3 is a gate insulating layer, 4 and 5 are source / drain regions, and 1A is a high concentration impurity introduction layer. In a short channel FET with a gate length of about 1 μm,
It has been confirmed that the punch-through current flows about 0.2 μm deep from the substrate surface in the channel formation portion under the gate because the saddle portion of the equipotential surface is formed inside the substrate by the depletion layer extending from the drain region. . In order to prevent this punch-through current, a structure is known in which a high-concentration impurity introduction layer 1A of the same conductivity type as that of the substrate is formed below a channel forming portion. Due to this high-concentration layer, the spread of the air-defense layer is blocked, and therefore punch-through current is blocked. In this case, for example, the concentration of the source
The substrate concentration is 20 cm -3 , and the substrate concentration is -10 15 cm -3 , and the concentration of the high-concentration impurity introduction layer 1A is 10 18 cm -3 . [Problems to be Solved by the Invention] However, the structure of the conventional example has the following disadvantages because the high-concentration impurity introduction layer 1A is in contact with the source / drain regions 4 and 5. The breakdown voltage of the pn junction formed between the source / drain region and the substrate was reduced, and it was not possible to obtain a high source / drain breakdown voltage and a high junction breakdown voltage at the same time. The junction capacitance increases and hinders high-speed operation of the device. Therefore, it is an object of the present invention to obtain a structure that realizes high breakdown voltage and high speed of a short channel FET. [Means for Solving the Problems] The above problems can be solved by a gate electrode provided on a semiconductor substrate and low concentration impurity regions and high concentration impurity regions in the semiconductor substrate on both sides of the gate electrode. A source / drain region formed in the semiconductor substrate, at least under the gate electrode and the source / drain region in the semiconductor substrate, separated from the source / drain region, and having the same conductivity type as the semiconductor substrate and a concentration higher than that of the semiconductor substrate. A high impurity introduction layer, wherein the impurity introduction layer is formed at the same depth below the gate electrode and below the source / drain region, and the impurity concentration between the source / drain region and the impurity introduction layer is The distance between the source / drain region and the impurity introduction layer is lower than the impurity introduction layer, and the distance between the source / drain region and the impurity introduction layer is an impurity. When the concentration is the same as the impurity concentration of the low concentration region of the source / drain region, the distance is set to be equal to or larger than the spread of the depletion layer when a predetermined reverse bias is applied as an operating voltage to the source / drain region. It is achieved by a semiconductor device. When the semiconductor substrate is made of a Si substrate, the impurity introduction layer is formed at a distance of 0.1 μm or more from the source / drain region and the impurity concentration between the impurity introduction layer and the source / drain region is 10 18 cm −3 or less. Good. This numerical limitation is that the low-concentration part of the source / drain region of the offset (LDD) structure is about 10 18 cm −3 , and therefore the concentration between the impurity introduction layer and the source / drain region needs to be lower. And when the concentration is 10 18 cm -3 , the depletion layer spreads when the junction is reverse biased at 10 V.
The thickness was 0.1 μm. [Operation] The present invention prevents a decrease in junction breakdown voltage and an increase in junction capacitance, which would otherwise occur when the high-concentration impurity-introduced layer for preventing punch-through is formed separately from the source / drain region. It was done. The present invention not only prevents punch-through between the source and drain, but also prevents generation of unfavorable charges such as hot carriers because the high-concentration impurity layer is formed up to the lower side of the source / drain region. In addition, even if such charge is generated, the charge is absorbed by the high-concentration impurity layer to stabilize the charge in the MOS FET. [Embodiment] FIG. 1 is a sectional view of an FET in which punch through is prevented according to an embodiment of the present invention. In the figure, 1 is a Si substrate, 2 is a gate electrode, 3 is a gate insulating layer, 4 and 5 are source / drain regions, and 1B is a high concentration impurity introduction layer. The difference from the conventional example is that the source / drain regions 4 and 5 are shallowly formed, and the high-concentration impurity introduction layer 1B is formed on the source / drain regions 4 and 4.
This is a point formed at a distance of 0.1 μm or more from 5. As with conventional Again, for example, concentration to 10 20 cm -3 in the source drain regions, the substrate concentration as to 10 15 cm -3, the concentration of the high concentration impurity doped layer. 1B to 10 18 cm - Make 3 The concentration between the source / drain region and the high-concentration impurity introduction layer 1B is 10 18 cm −3 or less. An embodiment for obtaining a structure in which the impurity introduction layer and the source / drain region are separated from each other will be specifically described. The source / drain region is formed shallow. (A) Low-acceleration ion implantation For example, As + is implanted at an energy of 35 KeV (up to 80 KeV in the past) at a dose of 1E15 cm −2 . (B) Lower activation temperature of implanted impurities RTA (Rapid Thermal Annea) using flash lamp
By heat treatment such as l), activation is performed in a short time at a temperature of 950 ° C or less to minimize impurity diffusion. (A) Highly Accelerated Ion Implantation For example, B + is implanted with an energy of 150 KeV, a dose amount of 1E13 cm −2 , and a range R p = 0.42 μm. (B) Inject an impurity having a small diffusion coefficient. For example, use Ga + or the like so that it does not spread in the heat treatment of the subsequent process. The diffusion coefficient of B at 900 ° C is 2 × 10 -2 (μm / h) 1/2 , but Ga is 1 × 10 -2 (μm / h) 1/2 . (C) Lowering the activation temperature of implanted impurities Conventionally, heat treatment at about 1000 ° C is activated at a temperature of about 900 ° C in a short time using RTA or the like to minimize impurity diffusion. As shown in FIG. 2 showing another embodiment, after the selective epitaxial layer 6 is grown on both sides of the gate, ion implantation for forming the source / drain is performed. Using the above method, a region with a concentration of 10 18 cm -3 or less is formed between the source / drain region and the high-concentration impurity introduction region.
It is formed with a width of 1 μm or more. In such a structure, for example, when the concentration between the high-concentration impurity introduction region and the source / drain is 10 18 cm −3 , the depletion layer extends only within 0.1 μm, and a withstand voltage of 10 V or more can be realized. [Effects of the Invention] As described above in detail, according to the present invention, by preventing punch-through current, the breakdown voltage between the source and the drain is increased, and at the same time, avalanche impact ionization near the drain becomes less likely to occur. Occurrence can be prevented. Therefore, a semiconductor device having a short-channel high-speed fine FET can be obtained.
【図面の簡単な説明】
第1図は本発明の一実施例によるパンチスルーを防止し
たFETの断面図,
第2図は他の実施例を説明する断面図,
第3図は従来例によるパンチスルーを防止したFETの断
面図である。
図において,
1はSi基板,
1Bは高濃度不純物導入層,
2はゲート電極,
3はゲート絶縁層,
4,5はソースドレイン領域
である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an FET in which punch-through is prevented according to one embodiment of the present invention, FIG. 2 is a cross-sectional view illustrating another embodiment, and FIG. It is sectional drawing of FET which prevented through. In the figure, 1 is a Si substrate, 1B is a high concentration impurity introduction layer, 2 is a gate electrode, 3 is a gate insulating layer, and 4 and 5 are source / drain regions.
Claims (1)
純物領域と高濃度不純物領域とで構成されたソースドレ
イン領域と, 該半導体基板内において少なくとも該ゲート電極および
該ソースドレイン領域の下部に該ソースドレイン領域よ
り離れて形成され,かつ該半導体基板と同一導電型で該
半導体基板より濃度の濃い不純物導入層 とを有し, 該不純物導入層は,ゲート電極の下方とソースドレイン
領域の下方とで同じ深さに形成され,該ソースドレイン
領域と該不純物導入層との間の不純物濃度は該不純物導
入層より低く,かつ該ソースドレイン領域と該不純物導
入層との間の距離は,該ソースドレイン領域と該不純物
導入層との間の不純物濃度が該ソースドレイン領域の低
濃度領域の不純物濃度と同じ濃度である場合に対し該ソ
ースドレイン領域に動作電圧として所定の逆バイアスを
印加したときの空乏層の広がり以上の距離に設定されて
いることを特徴とする半導体装置。 2.前記半導体基板がSi基板からなり,前記不純物導入
層がソースドレイン領域より0.1μm以上離れて形成さ
れ,かつ前記不純物導入層と該ソースドレイン領域間の
不純物濃度が1018cm-3以下であることを特徴とする特許
請求の範囲第1項記載の半導体装置。(57) [Claims] A gate electrode provided on a semiconductor substrate; a source / drain region including a low-concentration impurity region and a high-concentration impurity region in the semiconductor substrate on both sides of the gate electrode; and at least the gate electrode in the semiconductor substrate And an impurity introduction layer formed below the source / drain region apart from the source / drain region and having the same conductivity type as the semiconductor substrate and having a higher concentration than the semiconductor substrate. And at the same depth below the source / drain region, the impurity concentration between the source / drain region and the impurity introduction layer is lower than the impurity introduction layer, and the source / drain region and the impurity introduction layer The distance between the source and drain regions and the impurity introduction layer is such that the impurity concentration in the low concentration region of the source and drain regions is low. Wherein a set in the spread over the distance of the depletion layer at the time of applying a predetermined reverse bias as an operating voltage to the source drain regions to be the same concentration as. 2. The semiconductor substrate is made of a Si substrate, the impurity introduction layer is formed at a distance of at least 0.1 μm from the source / drain region, and an impurity concentration between the impurity introduction layer and the source / drain region is 10 18 cm −3 or less. 3. The semiconductor device according to claim 1, wherein:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62249249A JP2668893B2 (en) | 1987-10-02 | 1987-10-02 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62249249A JP2668893B2 (en) | 1987-10-02 | 1987-10-02 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0191466A JPH0191466A (en) | 1989-04-11 |
JP2668893B2 true JP2668893B2 (en) | 1997-10-27 |
Family
ID=17190147
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62249249A Expired - Lifetime JP2668893B2 (en) | 1987-10-02 | 1987-10-02 | Semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JP2668893B2 (en) |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5518072A (en) * | 1978-07-26 | 1980-02-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos semiconductor device |
JPS56169360A (en) * | 1980-05-29 | 1981-12-26 | Sharp Corp | Semiconductor device |
JPS5831576A (en) * | 1981-08-20 | 1983-02-24 | Matsushita Electric Ind Co Ltd | Mos type field effect transistor |
US4506436A (en) * | 1981-12-21 | 1985-03-26 | International Business Machines Corporation | Method for increasing the radiation resistance of charge storage semiconductor devices |
JPS58115863A (en) * | 1981-12-28 | 1983-07-09 | Matsushita Electric Ind Co Ltd | Insulating gate type field-effect semiconductor device and manufacture thereof |
JPS60206070A (en) * | 1984-03-29 | 1985-10-17 | Toshiba Corp | Semiconductor device |
JPS61172372A (en) * | 1985-01-28 | 1986-08-04 | Nec Corp | Manufacture of semiconductor device |
JPS63263767A (en) * | 1987-04-22 | 1988-10-31 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-10-02 JP JP62249249A patent/JP2668893B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0191466A (en) | 1989-04-11 |
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