JP2668893B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a structure of a semiconductor device having a short channel field effect transistor, a structure formed on a semiconductor substrate for the purpose of obtaining a structure that realizes high breakdown voltage and high speed of a short channel FET. A gate electrode, a source / drain region formed in the semiconductor substrate on both sides of the gate electrode, and formed at least below the gate electrode in the semiconductor substrate, apart from the source / drain region and the surface of the semiconductor substrate, Further, the semiconductor substrate has the same conductivity type as that of the semiconductor substrate and an impurity introduction layer having a higher concentration than that of the semiconductor substrate. When the semiconductor substrate is made of a Si substrate, the impurity introduction layer is formed from the source / drain region.
It is formed so as to be separated by 0.1 μm or more, and the impurity concentration between the impurity introduction layer and the source / drain region is 10 ¹⁸ cm ⁻³ or less. TECHNICAL FIELD The present invention relates to the structure of a semiconductor device having a short channel field effect transistor (FET). Due to the demand for higher speed and higher density of ICs, short channel FETs are being actively developed in various places. However, in order to miniaturize FET, for example, MOS FET,
If the gate (channel) length is shortened, the source / drain communicates with the depletion layer, and a punch-through current flows, so that this measure is required. [Prior Art] FIG. 3 is a cross-sectional view of an FET in which punch-through is prevented according to a conventional example. In the figure, 1 is a Si substrate, 2 is a gate electrode, 3 is a gate insulating layer, 4 and 5 are source / drain regions, and 1A is a high concentration impurity introduction layer. In a short channel FET with a gate length of about 1 μm,
It has been confirmed that the punch-through current flows about 0.2 μm deep from the substrate surface in the channel formation portion under the gate because the saddle portion of the equipotential surface is formed inside the substrate by the depletion layer extending from the drain region. . In order to prevent this punch-through current, a structure is known in which a high-concentration impurity introduction layer 1A of the same conductivity type as that of the substrate is formed below a channel forming portion. Due to this high-concentration layer, the spread of the air-defense layer is blocked, and therefore punch-through current is blocked. In this case, for example, the concentration of the source
^The substrate concentration is ²⁰ cm ^-3 , and the substrate concentration is -10 ¹⁵ cm ^-3 , and the concentration of the high-concentration impurity introduction layer 1A is 10 ¹⁸ cm ^-3 . [Problems to be Solved by the Invention] However, the structure of the conventional example has the following disadvantages because the high-concentration impurity introduction layer 1A is in contact with the source / drain regions 4 and 5. The breakdown voltage of the pn junction formed between the source / drain region and the substrate was reduced, and it was not possible to obtain a high source / drain breakdown voltage and a high junction breakdown voltage at the same time. The junction capacitance increases and hinders high-speed operation of the device. Therefore, it is an object of the present invention to obtain a structure that realizes high breakdown voltage and high speed of a short channel FET. [Means for Solving the Problems] The above problems can be solved by a gate electrode provided on a semiconductor substrate and low concentration impurity regions and high concentration impurity regions in the semiconductor substrate on both sides of the gate electrode. A source / drain region formed in the semiconductor substrate, at least under the gate electrode and the source / drain region in the semiconductor substrate, separated from the source / drain region, and having the same conductivity type as the semiconductor substrate and a concentration higher than that of the semiconductor substrate. A high impurity introduction layer, wherein the impurity introduction layer is formed at the same depth below the gate electrode and below the source / drain region, and the impurity concentration between the source / drain region and the impurity introduction layer is The distance between the source / drain region and the impurity introduction layer is lower than the impurity introduction layer, and the distance between the source / drain region and the impurity introduction layer is an impurity. When the concentration is the same as the impurity concentration of the low concentration region of the source / drain region, the distance is set to be equal to or larger than the spread of the depletion layer when a predetermined reverse bias is applied as an operating voltage to the source / drain region. It is achieved by a semiconductor device. When the semiconductor substrate is made of a Si substrate, the impurity introduction layer is formed at a distance of 0.1 μm or more from the source / drain region and the impurity concentration between the impurity introduction layer and the source / drain region is 10 ¹⁸ cm ⁻³ or less. Good. This numerical limitation is that the low-concentration part of the source / drain region of the offset (LDD) structure is about 10 ¹⁸ cm ⁻³ , and therefore the concentration between the impurity introduction layer and the source / drain region needs to be lower. And when the concentration is 10 ¹⁸ cm ^-3 , the depletion layer spreads when the junction is reverse biased at 10 V.
The thickness was 0.1 μm. [Operation] The present invention prevents a decrease in junction breakdown voltage and an increase in junction capacitance, which would otherwise occur when the high-concentration impurity-introduced layer for preventing punch-through is formed separately from the source / drain region. It was done. The present invention not only prevents punch-through between the source and drain, but also prevents generation of unfavorable charges such as hot carriers because the high-concentration impurity layer is formed up to the lower side of the source / drain region. In addition, even if such charge is generated, the charge is absorbed by the high-concentration impurity layer to stabilize the charge in the MOS FET. [Embodiment] FIG. 1 is a sectional view of an FET in which punch through is prevented according to an embodiment of the present invention. In the figure, 1 is a Si substrate, 2 is a gate electrode, 3 is a gate insulating layer, 4 and 5 are source / drain regions, and 1B is a high concentration impurity introduction layer. The difference from the conventional example is that the source / drain regions 4 and 5 are shallowly formed, and the high-concentration impurity introduction layer 1B is formed on the source / drain regions 4 and 4.
This is a point formed at a distance of 0.1 μm or more from 5. As with conventional Again, for example, concentration to 10 ²⁰ cm ^-3 in the source drain regions, the substrate concentration as to 10 ¹⁵ cm ^-3, the concentration of the high concentration impurity doped layer. 1B to 10 ¹⁸ cm ^{- Make 3} The concentration between the source / drain region and the high-concentration impurity introduction layer 1B is 10 ¹⁸ cm ⁻³ or less. An embodiment for obtaining a structure in which the impurity introduction layer and the source / drain region are separated from each other will be specifically described. The source / drain region is formed shallow. (A) Low-acceleration ion implantation For example, As ⁺ is implanted at an energy of 35 KeV (up to 80 KeV in the past) at a dose of 1E15 cm ⁻² . (B) Lower activation temperature of implanted impurities RTA (Rapid Thermal Annea) using flash lamp
By heat treatment such as l), activation is performed in a short time at a temperature of 950 ° C or less to minimize impurity diffusion. (A) Highly Accelerated Ion Implantation For example, B ⁺ is implanted with an energy of 150 KeV, a dose amount of 1E13 cm ⁻² , and a range R _p = 0.42 μm. (B) Inject an impurity having a small diffusion coefficient. For example, use Ga ⁺ or the like so that it does not spread in the heat treatment of the subsequent process. The diffusion coefficient of B at 900 ° C is 2 × 10 ^-2 (μm / h) ^1/2 , but Ga is 1 × 10 ^-2 (μm / h) ^1/2 . (C) Lowering the activation temperature of implanted impurities Conventionally, heat treatment at about 1000 ° C is activated at a temperature of about 900 ° C in a short time using RTA or the like to minimize impurity diffusion. As shown in FIG. 2 showing another embodiment, after the selective epitaxial layer 6 is grown on both sides of the gate, ion implantation for forming the source / drain is performed. Using the above method, a region with a concentration of 10 ¹⁸ cm ^-3 or less is formed between the source / drain region and the high-concentration impurity introduction region.
It is formed with a width of 1 μm or more. In such a structure, for example, when the concentration between the high-concentration impurity introduction region and the source / drain is 10 ¹⁸ cm ⁻³ , the depletion layer extends only within 0.1 μm, and a withstand voltage of 10 V or more can be realized. [Effects of the Invention] As described above in detail, according to the present invention, by preventing punch-through current, the breakdown voltage between the source and the drain is increased, and at the same time, avalanche impact ionization near the drain becomes less likely to occur. Occurrence can be prevented. Therefore, a semiconductor device having a short-channel high-speed fine FET can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an FET in which punch-through is prevented according to one embodiment of the present invention, FIG. 2 is a cross-sectional view illustrating another embodiment, and FIG. It is sectional drawing of FET which prevented through. In the figure, 1 is a Si substrate, 1B is a high concentration impurity introduction layer, 2 is a gate electrode, 3 is a gate insulating layer, and 4 and 5 are source / drain regions.

Claims (1)

(57) [Claims] A gate electrode provided on a semiconductor substrate; a source / drain region including a low-concentration impurity region and a high-concentration impurity region in the semiconductor substrate on both sides of the gate electrode; and at least the gate electrode in the semiconductor substrate And an impurity introduction layer formed below the source / drain region apart from the source / drain region and having the same conductivity type as the semiconductor substrate and having a higher concentration than the semiconductor substrate. And at the same depth below the source / drain region, the impurity concentration between the source / drain region and the impurity introduction layer is lower than the impurity introduction layer, and the source / drain region and the impurity introduction layer The distance between the source and drain regions and the impurity introduction layer is such that the impurity concentration in the low concentration region of the source and drain regions is low. Wherein a set in the spread over the distance of the depletion layer at the time of applying a predetermined reverse bias as an operating voltage to the source drain regions to be the same concentration as. 2. The semiconductor substrate is made of a Si substrate, the impurity introduction layer is formed at a distance of at least 0.1 μm from the source / drain region, and an impurity concentration between the impurity introduction layer and the source / drain region is 10 ¹⁸ cm ⁻³ or less. 3. The semiconductor device according to claim 1, wherein: