JPS58115863A - Insulating gate type field-effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain the MOS type field-effect transistor suitable for the formation of a short channeled gate length by a method wherein a high impurity density region of the conductive type reverse to a source and drain region is formed surrounding a part or the entire source or drain region. CONSTITUTION:The titled semiconductor device consists of a one-way conductive type semiconductor substrate 8 of high impurity density, an epitaxial layer 9 of the same conductive type as the substrate 8 in low impurity density which is connected to the semiconductor substrate 8, a source region 11 of the conductive type reverse to the substrate 8 formed in the epitaxial layer, a drain region 12, a high impurity density region 10 having the conductive type reverse to the drain region 12 which was formed surrounding the drain region 12, a gate oxide film 13 and a gate electrode 14. As the substrate of high impurity density is located below the drain region 12, most of the elongation of a depletion layer is absorbed by these regions, the depeletion region of the source region 11 does not come in contact with that of the source region 11. Also, as the semiconductor substrate 8 is located below the epitaxial layer 9, the extension of the depletion layer from the source or the drain region is absorbed there, and subthreshold voltage can be largely improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a novel structure for shortening the channel of an insulated gate field effect semiconductor device.

In recent years, in MO8 type semiconductor devices, MO8 type field effect transistors have been made to have shorter channels in order to improve the performance and degree of integration of LSIs. However, as the channel of MO8 field effect transistors becomes shorter, the edge of the drain depletion layer comes into contact with the edge of the source depletion layer, and the current does not flow through the surface of the semiconductor substrate, but instead flows several thousand times from the surface. It begins to flow at a depth of . This current is a punch-through current. When this current flows, MO8
The type field effect transistor does not exhibit the hexode characteristics as shown in FIG. 1, but instead exhibits the triode characteristics as shown in FIG.

However, in Figures 1 and 2, the horizontal axis represents the drain voltage (V
D), the vertical axis is the drain current (VD) or the parameter is the gate voltage.

Further, FIG. 3 shows how a bunch through current flows deep within a semiconductor substrate. In FIG. 3, 1 is a semiconductor substrate, 2 is a source region, 3 is a drain region, 4 is a gate oxide film, 5 is a gate electrode, the solid line 6 is an equipotential line, and the wavy line 7 is a current flow.

The reason why the MO8 type field effect transistor exhibits triode characteristics instead of pentode characteristics when the channel is shortened is due to the electrostatic induction effect caused by the drain voltage. In other words, since the depletion layer in the drain region is connected to the depletion layer in the source region, the potential peak near the source region is affected not only by the gate voltage but also by the drain voltage.

Since the current flows deep inside the semiconductor substrate, the controllability of the drain current by the Gert voltage deteriorates, and even if the gate voltage is below the threshold voltage, the current is not completely cut off, and the Buschire-Seehold current flows. In this case, the voltage that can be applied as the drain voltage of such an MO8 field effect transistor is limited. This situation is shown in FIG. In FIG. 4, the horizontal axis shows the effective channel length Leff, and the vertical axis shows the maximum drain voltage vDma. Effective channel length. When ff is long, the maximum drain voltage ■Pma! is limited by the avalanche breakdown of the MO8 field transistor (region A).
, when the effective channel length becomes short, the maximum drain voltage is limited by punch-through (region B).

As mentioned above, in the conventional MO8 type field effect transistor, punch-through occurs when the channel is shortened, and the VD
The saturation characteristic with respect to Ip deteriorates, and the drain breakdown voltage also deteriorates, causing problems in terms of characteristics.

In view of these conventional problems, the present invention aims to provide a structure of an MO8 field effect transistor suitable for shortening the gate length and channel.

The structure of the MO8 type field effect transistor of the present invention is described in the fifth example.
As shown in the figure.

In FIG. 6, 8 is a high impurity concentration semiconductor substrate of one conductivity type, 9 is an epitaxial layer of the same conductivity type as the low impurity concentration substrate 8 connected to the semiconductor substrate 8, and 11 and 12 are formed within this epitaxial layer. 1o is a high impurity concentration region of a conductivity type opposite to that of the drain region 12 formed to surround the drain region 12, 13 is a gate oxide film, and 14 is a gate electrode. It shows.

The MO8 type field effect transistor shown in FIG. 5 is designed to avoid the following two major drawbacks of the conventional MO8 type field effect transistor due to the shortened gate length and channel.

In other words, (1) in the conventional MO8 field effect transistor, the depletion layer from the drain region 3 contacts the depletion layer of the source region 2, so the potential near the source region 2 is affected not only by the gate voltage but also by the drain voltage. In order to control the electrostatic induction effect, the MO8 type field effect transistor shown in FIG. Since the substrate under the drain region 12 has a high impurity concentration, the elongation of the depletion layer is almost absorbed by these regions, so the depletion layer in the drain region 12 no longer comes into contact with the depletion layer in the source region 11. .

(2) In addition, in the conventional MO3 type field effect transistor, when the gate length is shortened, the current flows deep in the semiconductor substrate 1 as shown in Fig. 3, and the controllability with the gate voltage deteriorates. Although a subthreshold current flows even at 0 volts, in the MO3 type field effect transistor shown in FIG. Since the extension of the depletion layer from the source or drain is absorbed, the subthreshold current that flows due to the connection of the depletion layer is significantly improved.

FIG. 6 shows another embodiment of the invention. A high impurity concentration region 16 of the same conductivity type as the substrate 8' is formed into a low impurity concentration semiconductor substrate 8' of one conductivity type using an ion implantation method.
form inside. Therefore, in the case of Fig. 6, MOS)
A run sister is formed in the surface region of the substrate 8 instead of the epitaxial layer 9 of FIG. The configuration shown in FIG. 6 also provides the same effect as the configuration shown in FIG. 5.

In addition, in FIGS. 6 and 6, a region 1 of a conductivity type opposite to that of the drain region 12 is formed so as to completely surround the drain region 12.
However, the same effect can be obtained by forming a region 17 corresponding to the region 10 only in the direction in which the channel of the MOS (MOS) transistor is formed, as shown in FIG. Further, in FIGS. 6 and 7, the high impurity concentration region 10° 17 is formed only in the drain region, but it goes without saying that this region may be formed not only in the drain region but also around the source region 11. stomach.

Figures 8 and 9 are M corresponding to Figures 5 and 6 of the present invention.
1 in the structure of O8 type field effect transistor
The impurity profile below the gate electrode 14 is shown when channel doping is performed near the substrate surface for threshold voltage control. In FIGS. 8 and 9, the horizontal axis is the distance in the depth direction, and the vertical axis is the impurity concentration. As can be seen from these figures, the structure of this new MO5 field effect transistor is advantageous against α-rays in addition to the above. That is, the presence of a built-in field between the semiconductor substrate 8 of one conductivity type with a high impurity concentration and the epitaxial layer 9 of the same conductivity type connected thereto, or the existence of a built-in field between the semiconductor substrate 8 and the ion-implanted layer 16. Therefore, even if electrons and hole bears are formed by α rays, electrons, which are minority carriers, are difficult to flow into the device surface side.

As described above, even if the gate length of the field effect transistor of the present invention is shortened, the V-I characteristic does not become a triode characteristic, but exhibits a pentode characteristic, and the suppressed hold current is also significantly reduced. decreases to

In addition, it is possible to realize a device structure that is less susceptible to the effects of alpha rays, etc., which greatly contributes to the realization of fine, high-performance semiconductor devices.

[Brief explanation of drawings]

Figure 1 shows the V-I characteristics (hexode characteristics) of a MOS transistor when the gate length is long, and Figure 2 shows the V-I characteristics (triode characteristics) when the gate length is shortened. ,
FIG. 3 shows a conventional MO8 type field effect transistor; FIGS. 6 and 7 are structural cross-sectional views of an MO3 type single field effect transistor according to an embodiment of the present invention; and FIGS. 8 and 9 show a MO8 type field effect transistor of the present invention. FIG. 3 is a diagram showing the impurity profile under the gate electrode of a channel-doped device for controlling the threshold voltage of the structure. 8...High concentration one-side conductivity type semiconductor substrate, 9.
... Epitaxial layer of the same conductivity type connected to the semiconductor substrate, 11.12 ... Source region and drain region formed in the epitaxial layer, 10 ...
. . . A high impurity concentration region 8′ of a conductivity type opposite to that of the drain region 11, which is formed to surround the drain region 11.
...Low impurity concentration semiconductor substrate, 16...High impurity concentration region formed by ion implantation method. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 vB Figure 4 1eft (tone) Figure 5 Figure 8 l' Figure 9 Distance N lme town

Claims (2)

[Claims] (1) A high impurity concentration region having a conductivity type opposite to that of the source and drain regions surrounds a part or all of one or both of the source and drain regions of the insulated gate field transistor, and the source Alternatively, an insulated gate field effect semiconductor device 0 characterized in that it has a high impurity concentration region of a conductivity type opposite to that of the source and drain regions on the lower surface of the drain region. (2) A high impurity concentration region is formed by ion-implanting impurities of the same conductivity type into a semiconductor substrate of one conductivity type with a low impurity concentration, and source and drain regions are formed on the upper surface of this high impurity concentration region, and the A method for manufacturing an insulated gate field effect semiconductor device, comprising forming a highly impurity concentration region of a conductivity type opposite to that of the source or drain region so as to surround part or all of the source or drain region.