JPH05299437A - Soi-type substrate and its manufacture - Google Patents

Abstract

PURPOSE:To suppress short-channel effect and improve the operation speed, in an SOI-type MOSFET. CONSTITUTION:A p<+>-type semiconductor region 16 is made below the p-type channel region 24 of an SOI-type MOSFET through an insulating film 13. The p<+>-type semiconductor region 16 in contact with a p-type silicon substrate 18, and the potential of the p<+>-type semiconductor region 16 is fixed to be constant by giving substrate voltage Vb to this silicon substrate 18. Hereby, a source electrode 22 is electrically shielded from a drain region 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an SOI type MOSFET.
And a method of manufacturing the same, and more specifically, suppression of a short channel effect of an SOI type MOSFET.

[0002]

2. Description of the Related Art SOI type MOSF formed on an insulating film
The ET has features such as less parasitic capacitance, easier isolation between elements, and prevention of latch-up due to a parasitic thyristor as compared with a MOSFET formed on a bulk semiconductor, and has high integration and high speed of LSI. It is expected that the device structure will be suitable for commercialization.

FIG. 11 shows a conventional SOI type MOSFET.
FIG. In the figure, an insulating film (2) having a film thickness of 0.3 μm to 1.0 μm is formed on a P-type silicon substrate (1).
And a silicon layer (3) is formed on the insulating film (2). The silicon layer (3) inside, P-type channel region (4) is formed of, in contact with both sides of the P-type channel region (4), N ⁺ -type source region and (5) N ⁺
A mold drain region (6) is formed. A gate insulating film (7) is formed on the P-type channel region (4), and a gate electrode (8) is formed on the gate insulating film (7).

In the SOI MOSFET having the above structure, when a positive voltage is applied to the gate electrode (8), electrons are attracted to the surface of the P type channel region (4) and the surface is inverted to N type. This allows the source region (5)
Current can flow between the drain and the drain region (6).

[0005]

By the way, the conventional S
In OI type MOSFET, its channel length is 1μ
When the short channel is set to about m or less, the following problems occur. That is, as the source-drain voltage (Vds) is increased, the electric field lines (shown by broken lines in the figure) generated from the drain region 6 pass through the insulating film (2) and the channel region (4). 2) reaches the end of the source region (5) on the surface of (1).

FIG. 12 shows this as a potential distribution along the surface of the P-type channel region (4).
The height of the potential barrier at the end of the source region (5) decreases depending on the source-drain voltage, so-called DIB
L (Drain Induced Barrier L
owering) effect occurs. As a result, short channel effects such as an increase in leak current in the subthreshold region and a decrease in threshold voltage occur.

The present invention was created in view of the above-mentioned problems, and an object thereof is to provide an SOI type MOSFET in which the short channel effect is suppressed and a manufacturing method thereof.

[0008]

SOI type MOS of the present invention
The FET has a source region (22) by forming a P ⁺ -type semiconductor region (16) whose potential is fixed under the P-type channel region (24) through an insulating film (13).
Is electrically shielded from the drain region (23).

Further, in the method for manufacturing the SOI type MOSFET, the non-doping is performed by the low pressure CVD method through the element isolation film (12) and the insulating film (13) on the P type first silicon substrate (11). A first polysilicon film (14) is formed, and a P ⁺ type semiconductor region (1) is selectively formed in the first polysilicon film (14) by an ion implantation method.
6) is formed. Next, a non-doped second polysilicon film (17) is laminated on this, the surface is polished and flattened, and then a P-type second silicon substrate (18) is formed.
Stick together. Next, the P-type first silicon substrate (1
The P-type silicon layer (19) is formed by polishing the back surface of 1) until the upper surface of the element isolation film (12) is exposed. After that, the P-type silicon layer (19) is used as a substrate for S
An OI type MOSFET is formed. In addition, P ⁺
The semiconductor region (16) of the type is thermally diffused by using the heat treatment in the manufacturing process of the SOI type MOSFET, and is brought into contact with the second silicon substrate (18). This biases the second silicon substrate (18) to fix the P ⁺ type semiconductor region (16) at a constant potential.

[0010]

According to the SOI type MOSFET and the method of manufacturing the same of the present invention, the insulating film (1) is formed under the channel region (24).
3), a P ⁺ type semiconductor region (16) having a fixed potential is formed, and the source region (22) is electrically shielded from the drain electric field by the P ⁺ type semiconductor region (16). There is. This prevents the potential barrier at the end of the source region (22) from being lowered due to the influence of the drain electric field,
The short channel effect of the SOI type MOSFET can be effectively suppressed.

Further, below the source region (22) and the drain region (23), the non-doped first and second polysilicon films (14), (1) are provided via the insulating film (13).
Since 7) is formed by stacking, the expansion of the depletion layer in this portion can be increased. As a result, the junction capacitance can be reduced and the operating speed of the SOI type MOSFET can be improved.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 to 8 show S according to an embodiment of the present invention.
It is sectional drawing explaining the manufacturing process of OI type MOSFET one by one. FIG. 1: An element isolation film (12) is formed on a P-type first silicon substrate (11) by a selective oxidation method. Then, an insulating film (13) having a film thickness of about 300 Å is formed on the substrate (11) except the formation region of the element isolation film (12) by a thermal oxidation method.

FIG. 2: By applying the low pressure CVD method, a non-doped first polysilicon film (about 4000 Å) having a film thickness of about 4000 Å is formed on the device isolation film (12) and the insulating film (13). Then, a photoresist (15) is applied on the first polysilicon film (14) and a photolithography technique is applied to selectively remove the photoresist (15) to form an opening (15a). ). After this,
By the ion implantation method, boron ions ( ¹¹ B ⁺ ) are introduced into the first polysilicon film (14) from the opening portion (15a) under the conditions of an acceleration energy of −40 KeV and an implantation amount of 5 × 10 ¹⁵ / cm ^2. By implanting, a P ⁺ type semiconductor region (16) is formed.

FIG. 3: The photoresist (15) used as a mask for ion implantation is removed. And low pressure CVD
By applying the method, a non-doped second polysilicon film (17) is laminated on the first polysilicon film (14) to be formed. FIG. 4: The surface of the second polysilicon film (17) is mechanically polished to flatten the surface.

FIG. 5: A P-type second silicon substrate (18) is attached to the surface polished in the above step. Then, the back surface of the first silicon substrate (11) is mechanically polished, and when the upper surface of the element isolation film (12) is exposed, the polishing is finished and a P-type silicon layer (19) made of a single crystal is formed. To do. According to this method, since the element isolation film (12) is used as a polishing stopper, the P-type silicon layer (19) is used.
The film thickness of can be accurately controlled. For example, an element isolation film (1
By forming the film thickness of 2) to 2000Å, the film thickness of the P-type silicon layer (19) can be formed to a thin film thickness of about 1000Å.

FIG. 6: A gate insulating film (20) is formed on the surface of the P type silicon layer (19) by a thermal oxidation method, and a gate electrode (21) is formed on the gate insulating film (20). FIG. 7: An N ⁺ type source region (22) and an N ⁺ type drain region (23) are formed in the P type silicon layer (19) by an ion implantation method using the gate electrode (21) as a mask. The source region (2 in the P-type silicon layer (19)
The region between 2) and the drain region (23) becomes a P-type channel region (24). And 900 ℃ ~ 950 ℃
By subjecting the source region (22) and the drain region (23) to electrical activation,
The P ⁺ type semiconductor region (16) is thermally diffused and brought into contact with the second silicon substrate (18).

FIG. 8: An interlayer insulating film (25) made of a BPSG film or the like is formed by a low pressure CVD method. This interlayer insulating film (25) is selectively etched to form contact holes (26) on the source region (22) and the drain region (23). Then, in the contact hole (26), a source electrode (27) and a drain electrode (28) which are ohmic-connected to the source region (22) and the drain region (23) are formed. Then, a substrate electrode (29) is formed on the back surface of the second silicon substrate (18) to complete the SOI MOSFET.

FIG. 9 shows the SOI type MOSFE shown in FIG.
It is the elements on larger scale of T. Under the channel region (24) of the SOI type MOSFET, P is provided through the insulating film (13).
^{A +} type semiconductor region (16) is formed, and the P ⁺ type semiconductor region (16) is in contact with the second P type silicon substrate (18). The substrate electrode (29) is connected to a constant potential such as a ground potential, whereby the P ⁺ type semiconductor region (1
The potential of 6) is fixed.

According to this structure, the drain region (23)
When source-drain voltage (Vds) is applied to
A line of electric force (shown by a broken line in the figure) emitted from the drain region (23) does not reach the source region (22) as in the conventional example, but does not reach the P ⁺ type semiconductor region (16) or the second region. It comes to terminate on the surface of the silicon substrate (18). That is, the source region (22) is P
It is electrically shielded from the drain electric field by the ⁺ type semiconductor region (16).

FIG. 10 shows a P-type channel region (24).
3 shows the potential distribution along the surface of the. As described above, according to the present invention, since the drain region (23) is shielded by the P ⁺ type semiconductor region region (16),
The height of the potential barrier at the end of the drain region (22) maintains the height when the source-drain voltage is zero (Vds = 0V). This makes it possible to suppress short channel effects such as an increase in leakage current in the subthreshold region and a decrease in threshold voltage.

By applying the above-mentioned manufacturing process, the source region (22) and the drain region (2
3) In the lower region, a non-doped first polysilicon film (14) and a second polysilicon film (17) are laminated via an insulating film (13). A P-type impurity (for example, boron) diffuses upward from this second silicon substrate (18) into this region from the second silicon substrate (18). However, if the boron concentration in the second silicon substrate (18) is 8 ×
By setting it to about 10 ¹⁴ / cm ^{3 to} 5 × 10 ¹⁵ / cm ³ , a P-type polysilicon region close to intrinsic can be obtained when the wafer is completed. As a result, the depletion layer in the region under the source region (22) and the drain region (23) can be expanded and the junction capacitance can be reduced, so that the SOI type M
The operation of the OSFET can be speeded up.

[0022]

According to the present invention, an SOI type MOSFET
A P ⁺ -type semiconductor region (16) having a fixed potential is formed under the channel region (24) of the semiconductor via the insulating film (13), and the source region (22) is electrically connected to the drain region (23). It is shielded from. Thereby, the potential barrier at the end of the source region (21) due to the influence of the drain electric field can be prevented from being lowered, and the short channel effect of the SOI type MOSFET can be effectively suppressed.

Further, according to the present invention, since the formation position of the P ⁺ type semiconductor region (16) is limited to below the channel region (24), the junction of the source region (22) and the drain region (23) is formed. Reduced capacity, SOI type MOSF
It also has the advantage that the ET operation can be speeded up.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view showing a method for manufacturing an SOI MOSFET according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing the SOI-type MOSFET according to the embodiment of the present invention.

FIG. 3 is a third cross-sectional view showing the method of manufacturing the SOI-type MOSFET according to the embodiment of the present invention.

FIG. 4 is a fourth cross-sectional view showing the method of manufacturing the SOI-type MOSFET according to the embodiment of the present invention.

FIG. 5 is a fifth cross-sectional view showing the method of manufacturing the SOI-type MOSFET according to the embodiment of the invention.

FIG. 6 is a sixth cross-sectional view showing the method of manufacturing the SOI-type MOSFET according to the embodiment of the present invention.

FIG. 7 is a seventh cross-sectional view showing the method of manufacturing the SOI-type MOSFET according to the embodiment of the present invention.

FIG. 8 is an eighth cross-sectional view showing the method of manufacturing the SOI MOSFET according to the embodiment of the present invention.

9 is a partially enlarged view of the SOI type MOSFET shown in FIG.

FIG. 10 is a potential distribution diagram along the surface of the channel region of the SOI MOSFET of the present invention.

FIG. 11 is a cross-sectional view of a conventional SOI MOSFET.

FIG. 12 is a potential distribution diagram along the surface of a channel region of a conventional SOI MOSFET.

Claims (2)

[Claims] 1. An insulating film (13) formed on a main surface of a semiconductor substrate (18) of one conductivity type, a silicon layer (19) formed on the insulating film (13), and the silicon layer. (1
9) Channel region (24) of one conductivity type formed in
And a source region (22) and a drain region (23) of opposite conductivity type formed on both sides of the channel region (24).
And a gate insulating film (20) on the channel region (24).
Having a gate electrode (21) formed through
In the I-type MOSFET, a one-conductivity-type high-concentration semiconductor region (16) is formed below the channel region (24) through an insulating film (13), and the semiconductor region (16) is kept at a constant potential. By fixing the source region (22) to the drain region (23)
SOI type MOS characterized by being electrically shielded from
FET. 2. On a first semiconductor substrate of one conductivity type (11)
A step of forming an element isolation film (12) on the substrate by a selective oxidation method, a step of forming an insulating film (13) on the substrate (11) excluding the element isolation film (12) by a thermal oxidation method, and a low pressure CVD method. A step of forming a non-doped first polysilicon film (14) on the element isolation film (12) and the insulating film (13) by selectively using one conductivity type in the one polysilicon film (14). A step of forming a high-concentration semiconductor region (16), a step of stacking a non-doped second polysilicon film (17) on the first polysilicon film (14) by a low pressure CVD method, and a second step of A step of polishing the surface of the polysilicon film (17) to planarize the surface, and a second semiconductor substrate of one conductivity type on the surface of the second polysilicon film (17) planarized in the step. The step of attaching the upper part (18), Backside isolation layer on a semiconductor substrate (11) (1
A step of forming a silicon layer (19) of one conductivity type by polishing until 2) is exposed; a step of forming a gate insulating film (20) on the silicon layer (19) by thermal oxidation; A step of forming a gate electrode (21) on the insulating film (20) and ion implantation using the gate electrode (21) as a mask,
In the silicon layer (19), a source region (2
2) and a drain region (23) and a channel region (24) of one conductivity type, and thermally diffusing the high-concentration semiconductor region (16) of one conductivity type,
A step of contacting the second semiconductor substrate (18) with the second semiconductor substrate (18).