JP2001313392A - Power mosfet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOSFET having such a device structure which is hardly destroyed. SOLUTION: The impurity concentration in an n--type epitaxial layer 2 is kept constant to a prescribed depth from the principal plane. From the prescribed depth on, the impurity concentration is increased with linear gradient. Due to this structure, electric field distribution can be smoothly changed in the n--type epitaxial layer 2 and a drain current value, at which a MOSFET comes to have a negative resistance can be set higher than in the conventional method. Even if the drain current of part of a plurality of MOSFETs is higher than those of the other MOSFETs, since the MOSFETs having a higher drain current will hardly enter negative resistance, increase in an allowable current value until the MOSFETs come enters negative resistance, that is, the resistance to avalanche can be set high. Consequently, the dain current is prevented from becoming a large current in the part of the plurality of MOSFETs, making the MOSFETs have a device structure which is hardly destroyed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOSFET having a device structure having a high avalanche energy resistance.
About.

[0002]

2. Description of the Related Art An L load switching operation circuit of a power MOSFET 100 is shown in FIG. 15A, and a gate voltage V of the power MOSFET 100 at the time of L load switching.
FIG. 15B shows operation waveforms of g, the drain current Id, and the drain voltage Vd.

When a gate voltage Vg is applied in the switching operation circuit shown in FIG.
When the ET 100 is turned on, the drain current Id flows, and FIG.
An operation waveform as shown in FIG.

When the drain current increases, 1/2 L · I _peak ² of energy is stored in the inductance component L in the circuit. If this energy is large, a flyback voltage exceeding the withstand voltage between drain and source is generated at the time of turn-off, and the power MOSFET causes avalanche breakdown. At this time, the maximum value I of the drain current
_{When the peak} reaches the allowable current value of the power MOSFET, there is a problem that the element is destroyed.

[0005]

Generally, a power element has a configuration in which tens of thousands to hundreds of thousands of small transistors are connected in parallel, and an output is obtained by operating these transistors simultaneously. I have.

However, at this time, since not all transistors perform a uniform operation and flow a uniform current, a large current flows locally, causing the above-described element destruction.

The causes of the non-uniformity of the current include variations in the operating temperature in the chip, variations in the electrode resistance on the chip, and variations in the switching operation time.

Is caused by the increase in the temperature at the center of the chip during the operation of the MOSFET. When the temperature increases, the operating resistance increases. Therefore, the current at the center of the chip is reduced, and unevenness of the current is reduced. generate.

The reason for this is that the wiring resistance is small and the current easily flows as the distance from the wire bond portion increases, whereas the wiring resistance increases and the current hardly flows as the distance increases. , Causing non-uniform current.

[0010] This is caused by the wiring resistance of the gate. If the wiring resistance of the gate is large, it takes a longer time to reach a steady current in a place far from the gate bonding than in a place near the gate bonding. Causes a non-uniform current during the transition.

If the current becomes non-uniform due to these factors, only the transistor A having a large current enters the negative resistance region because the current-voltage characteristics of the transistor have the negative resistance characteristics shown in FIG. Positive feedback will be applied.

Considering the current balance in this state,
Since the resistance of the transistor A is in a negative state, the voltage decreases as the current flows, and the current flows more and more. On the other hand, the transistor B, which is not in the negative resistance region, has a positive state. Therefore, when a current is to flow, the voltage is increased, and the increase in the current is suppressed.

Therefore, current concentrates on the transistor A, and the transistor A is destroyed.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a MOSFET having an element structure that is hardly damaged.

[0015]

In order to achieve the above object, according to the present invention, the semiconductor layer (2)
Is characterized in that the impurity concentration of the first conductivity type is substantially constant from the main surface of the semiconductor layer to a predetermined depth, and becomes higher as the depth becomes larger than the predetermined depth.

With such a configuration, the electric field distribution in the semiconductor layer can be changed smoothly, and the drain current value entering the negative resistance can be made higher than in the prior art. Thereby, even if the drain current of some of the plurality of MOSFETs becomes larger than that of the other MOSFETs, the M
Since it is difficult for the OSFET to enter the negative resistance, the allowable current value until the OSFET enters the negative resistance, that is, the avalanche resistance can be increased. Therefore, it is possible to prevent the drain current from becoming large in a part of the plurality of MOSFETs, and to prevent the device from being destroyed.
It can be ET.

For example, when the depth is greater than a predetermined depth, the impurity concentration of the first conductivity type in the semiconductor layer may be increased with a linear slope. And
According to a fifth aspect of the present invention, in the semiconductor layer, the impurity concentration at the boundary with the semiconductor substrate is set to 8.0 × 10 ¹⁵ cm ⁻³ or more. By making the impurity concentration of the layer at the boundary with the semiconductor substrate seven times or more that of the region where the impurity concentration is almost constant, the drain current value entering the negative resistance is sharply increased. be able to.

The reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0019]

(First Embodiment) FIG. 1 shows a cross-sectional structure of a concave vertical power MOSFET formed by applying one embodiment of the present invention. Hereinafter, the configuration of the vertical power MOSFET will be described with reference to FIG.

This vertical power MOSFET has an M-type channel having the inner wall of a U-shaped groove 50 called a concave type as a channel region.
The OSFET has a structure in which a large number of unit cells are arranged in a matrix on a plane at a predetermined pitch width (unit cell size).

The wafer 21 used for the vertical power MOSFET has an n ⁻ -type epi layer (semiconductor layer) 2 having a thickness of about 17 μm formed on a semiconductor substrate 1 made of n ⁺ -type silicon. A unit cell is formed on the main surface of the wafer 21.

FIG. 2 shows an example of the impurity concentration distribution of the wafer 21. FIG. 3 is a simplified diagram of FIG.
FIG. 2 shows the impurity concentration distribution in the depth direction from the surface of the wafer 21, and shows the impurity concentration distribution after the vertical power MOSFET shown in FIG.

The impurity concentration of the semiconductor substrate 1 is 1 × 10 ¹⁹ to
It is about 3 × 10 ¹⁹ cm ⁻³ . The impurity concentration of the n ⁻ -type epi layer 2 is a predetermined depth (10 to 10) from the surface of the wafer 21.
Up to 12 μm), a uniform portion having a substantially constant density is formed, and as the depth increases, the density becomes higher as the depth increases. In this example, the density is 1.12 × in the uniform portion.
The resistance value is about 10 ¹⁵ cm ⁻³ and the resistance value is 4.3 Ω · cm. When the resistance is deeper than the uniform portion, the concentration is increased with a substantially linear slope up to the vicinity of the boundary of the semiconductor substrate 1, The concentration is 8.0 × 10 ¹⁵ cm near the boundary with 1.
^-3 , and the resistance value is set to 0.71 Ω · cm. Specifically, when the depth is X and the impurity concentration is Y, the linearly inclined portion is expressed by the following equation.

LogY = A × X + C where A is a slope and C is an arbitrary constant. This slope A
Can be changed according to the width (depth) of the inclined portion. For example, if the width of the inclined portion is about 3 to 10 μm, the inclination A can be changed at about 0.1 to 0.7. .

FIG. 4 shows a power MOS of this embodiment.
FIG. 4 is a diagram comparing the impurity concentration distributions of a FET and a conventional power MOSFET. As shown in this figure, in the conventional power MOSFET, the impurity concentration of the n ⁻ -type epi layer is almost constant up to the boundary with the semiconductor substrate, and the impurity concentration is steep at the boundary with the semiconductor substrate. Has changed. In contrast, the power MOS of the present embodiment
In the FET, the impurity concentration gradually changes at the boundary between the n ⁻ -type epi layer 2 and the semiconductor substrate 1.

As shown in FIG. 1, a U-groove 50 is formed on the main surface of the wafer 21 having the above-described structure, and the inner wall of the U-groove 50 and a part of the wafer surface have a thickness of 60 nm.
A gate electrode 4 made of polysilicon having a thickness of about 400 nm is formed via a gate oxide film 3 having a thickness of about 400 nm.
Then, an interlayer insulating film 6 made of BPSG is formed on the gate electrode 4.

On the other hand, the wafer 2 forming the side wall of the U groove 50
An n ⁺ -type source region 7 having a junction depth of approximately 0.4 μm and a p-type base region 8 having a junction depth of approximately 1.5 μm are formed in the surface layer portion 1. Then, on the side wall of the U groove 50, the p-type base region 8 becomes the n ⁺ -type source region 7 and n ⁻
The structure is sandwiched between the mold epi layers 2, and a channel region is set on the side wall of the U groove 50. Note that the junction depth of the p-type base region 8 is set to a depth that does not cause breakdown due to breakdown at the bottom edge of the U-shaped groove 50.

In the center of the p-type base region 8, p-type
Depth 2.5 where the junction depth is deeper than the mold base region 8
A p-type deep base layer 9 of about μm is formed.
The p-type deep base layer 9 causes breakdown at the p-type deep base layer 9 when a high voltage is applied between the drain and the source.

In the central part between the unit cells,
A high-concentration p-type contact region 11 is formed in the surface portion of the n ⁻ -type epi layer 2.

Then, a part of the n ⁺ type source region 7 and p
The interlayer insulating film 6 is exposed so that the mold contact region 11 is exposed.
Is formed with a contact hole 6a. further,
An interlayer insulating film 6 on the gate electrode 4, an n ⁺ type source region 7,
A source electrode 12 is formed on the p-type contact region 11, and a part of the n ⁺ -type source region 7 and the p-type contact region 11 are in ohmic contact with the source electrode 12. Thus, the configuration is such that the p-type base region 8 is connected to the source electrode 12 via the p-type contact region 11.

A drain electrode 13 is formed on the back surface of the wafer 21, that is, on the back surface side of the semiconductor substrate 1 so as to make ohmic contact with the semiconductor substrate 1.

The oxide film 15 in the figure is for isolating the active region and the non-active region of the device.

The power MOSFET thus configured
A simulation analysis was performed on the breakdown characteristics between the source and the drain. The result is shown in FIG. For reference, FIG. 5 shows the source of a conventional power MOSFET.
The breakdown characteristics between drains are shown.

As shown in this figure, in the power MOSFET of the present embodiment, the drain current value that enters the negative resistance, that is, the region where the drain current increases with the increase of the drain voltage and the drain voltage decreases. It can be seen that the inflection point with the region where the drain current increases is higher than in the conventional case. According to the simulation analysis result, the drain current value entering the negative resistance of the structure of the present embodiment is about 2.3 times higher than that of the power MOSFET of the conventional structure.

[0035] This, n ^- at the boundary between the type epi layer 2 and the semiconductor substrate 1, n ^- since the impurity concentration of the type epi layer 2 was made to change gradually, n ^- of the type epitaxial layer 2 It is assumed that this is because the electric field distribution was affected.

[0036] For this, the present inventors used a conventional wafer having an impurity concentration distribution shown in the wafer 21 and 6 of the present embodiment having the impurity concentration distribution of FIG. 2, the chip area 7.1 mm ² Even in this case, when the change in the electric field in the wafer due to the current rise was examined, the results shown in FIGS. 7 and 8 were obtained, respectively.

When the impurity concentration of the n ⁻ -type epi layer 2 is gradually changed as in the present embodiment, when a voltage is applied between the source and the drain, the depletion layer spreads mainly on the n ⁻ -type epi layer 2 side, A space charge region is created. When this region reaches the middle of the inclined portion and the electric field intensity at the PN junction reaches a critical point, breakdown occurs. Furthermore, as the breakdown current increases, the space charge region also spreads on the slope. As a result, when the n ⁻ -type epi layer 2 has a gradient as in the present embodiment, the electric field distribution changes gently as the current increases. On the other hand, when the n ⁻ -type epi layer changes steeply without inclination as in the related art, the electric field distribution changes steeply due to an increase in current.

According to the result, the electric field distribution in the n ⁻ -type epi layer 2 can be changed smoothly by gradually changing the impurity concentration of the n ⁻ -type epi layer 2 as in the present embodiment. It can be said that the drain current value falling into the conductive resistance can be made higher than before.

As described above, if the value of the drain current entering the negative resistance increases, even if the drain current of some of the plurality of MOSFETs becomes larger than that of the other MOSFETs,
The MOSFET can be made hard to enter the negative resistance, and the allowable current value until the MOSFET enters the negative resistance, that is, the avalanche resistance can be increased.

For this reason, it is possible to prevent a large drain current in a part of the plurality of MOSFETs, and to prevent the device from being destroyed.
It can be.

Next, the vertical power MOS having the above configuration
A method for manufacturing the FET will be described. 9 and 10,
The manufacturing process of a vertical power MOSFET is shown, and the above description will be made based on these drawings.

The main surface of the [FIG. 9 (a) step is shown in] First, a semiconductor substrate 1 made of n ⁺ -type silicon containing As a high concentration ^{(1 × 10 19 cm -3)} , n by epitaxial growth ^- type epi The layer 2 is grown by 17 μm to form a wafer 21. At this time, the condition of the epitaxial growth is performed at a temperature of 1100 to 1150 ° C. for about 15 to 20 minutes,
The n ⁻ -type epi layer 2 is grown at a thickness of about 1 μm per minute. Further, the n ^- type epi layer 2
Is introduced, but the amount of the n-type impurity to be introduced is changed with the growth time. That is, the introduction amount of the n-type impurity is reduced with the lapse of time until a predetermined time has elapsed from the start of growth (5.0 × 1).
0 ¹⁶ cm ^{−3 to} 1.12 × 10 ¹⁵ cm ⁻³ ), and after elapse of a predetermined time, growth of 5 μm, the introduction amount of the n-type impurity is reduced to 1.1.
It is kept constant at 2 × 10 ¹⁵ cm ^-3 and is grown to about 12 μm.

Then, through a photolithography process, n
^- After forming the predetermined mask pattern on the type epi layer 2, to form the p-type deep base layer 9 by ion implantation of boron (B).

Then, a thick oxide film 15 is formed in a region to be an inactive region of the device by the LOCOS oxidation method.

[Step shown in FIG. 9B] The surface is thermally oxidized to form a thermal oxide film (SiO ₂ film) 31 on the surface of the n ⁻ -type epi layer 2.
Is formed, a silicon nitride film (Si ₃ N ₄ film) 32 is deposited.

Thereafter, predetermined regions of the silicon nitride film 32 and the thermal oxide film 31 are opened through a photolithography process. Then, using the silicon nitride film 32 as a mask, the n ⁻ -type epi layer 2 is etched by an isotropic CDE (chemical dry etching) method with less damage to form an initial groove.

Further, using the silicon nitride film 32 as a mask, the portion of the initial groove is selectively LOCOS-oxidized. This oxidation forms a LOCOS oxide film 33,
A U-shaped groove 50 having a U-shaped cross section is formed on the surface of the n ⁻ -type epi layer 2 eroded by the COS oxidation.

[Step shown in FIG. 9C] After the silicon nitride film 32 is removed, a photoresist is deposited on the wafer 21 so that the photoresist remains in the central portion between the LOCOS oxide films 33. I do. And LOCO
Using the S oxide film 33 and the photoresist as a mask, boron ion implantation for forming the p-type base region 8 is performed.

Further, phosphorus (P) ions for forming the n ⁺ -type source region 7 are implanted using the LOCOS oxide film 33 and the photoresist as a mask. Then, by thermally diffusing the implanted ions, a p-type base region 8 and an n ⁺ -type source region 7 are formed.

[0050] Thus, since forming the p-type base region 8 and the n ⁺ -type source region 7 and the LOCOS oxide film 33 as a mask, U grooves 50 of p-type base region 8 and the n ⁺ -type source region 7 The side end is defined in a self-aligned position.

Next, after removing the photoresist, the photoresist is deposited again, and the central portion of the photoresist between the LOCOS oxide films 33 is opened.
Then, using this photoresist as a mask, boron ions are implanted to form a high-concentration p-type contact layer 11.

[Step shown in FIG. 10A] The LOCOS oxide film 33 is removed to expose the inner wall of the U groove 50. Then, thermal oxidation is performed on the p-type base region 8 located on the side wall of the U groove 50 where the channel is to be formed.

Thereafter, after removing the oxide film formed by the thermal oxidation, thermal oxidation is performed again to oxidize the entire surface of the wafer 21 including the side surface of the U-groove 50 and the bottom surface 50a, thereby forming the gate oxide film 3.

[Step shown in FIG. 10B] After depositing polysilicon on the gate oxide film 3, the polysilicon is patterned to form a gate electrode 4.

After oxidizing the polysilicon constituting the gate electrode 4, although not shown, BPSG (or PSG) is used.
1) by depositing an interlayer insulating film 6 made of the same type as above, or forming a source electrode 12, a passivation film, and a drain electrode 13 as shown in FIG.
T is completed.

Further, due to the heat treatment during the manufacturing process, as shown in FIG.
The impurity distribution transitions from the side to the n ⁻ -type epi layer 2 side, and the boundary portion concentration is from 5.0 × 10 ¹⁶ cm ⁻³ to 8.0 × 10 ¹⁵ cm ^−3.
About.

(Other Embodiments) In the above embodiment, n ⁻
Although the case where the impurity concentration distribution of the n ^- type epi layer 2 is shown in FIG. 2 has been mainly described, the gradient of the slope portion of the impurity concentration distribution of the n ⁻ -type epi layer 2 and the width (depth) of the gradient region can be appropriately changed. is there.

For example, as shown in FIG. 11, the inclination of the inclined portion may be made larger than that of the above embodiment, or as shown in FIG. 12, the inclination of the inclined portion may be made smaller than that of the above embodiment. When the gradient of the inclined portion is changed in this manner, the source-drain breakdown characteristics change as shown in FIG.
In FIG. 13, the characteristic of the impurity concentration distribution shown in FIG. 2 is denoted by a, the characteristic of the impurity concentration distribution shown in FIG. 11 is denoted by b, and the characteristic of the impurity concentration distribution shown in FIG. 12 is denoted by c. FIG. 13 shows the source-drain breakdown characteristics of a conventional power MOSFET.

As shown in this figure, the n ⁻ -type epi layer 2
The source-drain breakdown characteristics change in accordance with the gradient of the slope portion of the impurity concentration distribution, and the drain current value entering the negative resistance increases as the gradient increases.

As described above, by adjusting the gradient of the slope of the impurity concentration distribution of the n ⁻ -type epi layer 2, the drain current value falling into the negative resistance can be further increased.

The relationship between the change in the slope of the slope and the change in the drain current value entering the negative resistance was determined by simulation analysis. The result is shown in FIG. In this figure, the impurity concentration of the n ⁻ -type epi layer 2 at the boundary between the n ⁻ -type epi layer 2 and the semiconductor substrate 1 is changed, and depending on the change in the impurity concentration, How it changes. That is, FIG. 14, the inclined portion the thickness of which is shown in FIG. 3, the impurity concentration of the uniform portion, and the impurity concentration of the semiconductor substrate 1 at a constant, n at the boundary between the semiconductor substrate 1 ^- the impurity concentration of the type epi layer 2 Shows the permissible drain current when is changed.

From this figure, it can be seen that the drain current value entering the negative resistance can be increased by increasing the slope of the slope. From this figure, it can be seen that the impurity concentration at the boundary is about 8.0 × 10 ¹⁵ cm ⁻³ , about 7 to 10 times or more the impurity concentration of the uniform part (1.12 × 10 ¹⁵ cm ⁻³ ), or the slope is The inclination of the part is (8.0-1.12) × 1
It can be seen that the drain current value entering the negative resistance can be sharply increased by setting it to 0 ¹⁵ cm ⁻³ / 5 μm or more.

However, in the example shown in FIG. 14, the result was obtained that the drain current value entering the negative resistance increased as the gradient increased, but if the gradient was too large, the drain-source breakdown voltage and the negative Since the drain voltage value that enters the resistor becomes lower, the drain current value that enters the negative resistance can be increased while minimizing the drain voltage drop by optimizing the magnitude of the gradient and the width of the gradient region. It becomes possible.

In the above description, a concave type power MOSFET has been described as an example. However, the present invention is applied to a planar type power MOSFET in which a groove is not formed, a trench type power MOSFET in which a groove is formed by etching, and the like. You may. Of course, the present invention may be applied to a MOSFET in which the n-type and p-type conductivity types are reversed.

[Brief description of the drawings]

FIG. 1 shows a power MOSF to which an embodiment of the present invention is applied.
It is a figure showing the section composition of ET.

FIG. 2 is a diagram showing an impurity concentration distribution of a wafer used for the power MOSFET shown in FIG.

FIG. 3 is a simplified diagram of the impurity concentration distribution shown in FIG. 2;

4 is a diagram comparing the impurity concentration distributions of the power MOSFET shown in FIG. 1 and a conventional power MOSFET.

5 is a diagram comparing the source-drain breakdown characteristics of the power MOSFET shown in FIG. 1 and a conventional power MOSFET.

FIG. 6 is a diagram showing an impurity concentration distribution of a conventional power MOSFET.

FIG. 7 is a diagram showing a change in electric field distribution in a wafer of the power MOSFET shown in FIG. 1;

FIG. 8 is a diagram showing a change in electric field distribution in the wafer of the power MOSFET shown in FIG. 6;

FIG. 9 is a view showing a manufacturing process of the power MOSFET shown in FIG. 1;

FIG. 10 is a view illustrating a manufacturing step of the power MOSFET following FIG. 9;

FIG. 11 is a diagram showing an impurity concentration distribution of a power MOSFET according to another embodiment.

FIG. 12 is a diagram showing an impurity concentration distribution of a power MOSFET according to another embodiment.

FIG. 13 is a diagram comparing the source-drain breakdown characteristics with the change in the gradient of the slope portion of the impurity concentration.

FIG. 14 is a diagram showing the relationship between a change in the slope of the slope and a change in the drain current value entering the negative resistance.

FIG. 15A is a schematic circuit diagram of a MOSFET,
(B) is a diagram showing operation waveforms of the circuit shown in (a).

FIG. 16 is a diagram for explaining negative resistance.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... n ^- type epi layer, 3 ... Gate oxide film, 4 ... Gate electrode, 7 ... n ⁺ type source region, 8 ... p-type base region, 9 ... p-type deep base layer, 11 ... Contact Region, 12: source electrode, 13: drain electrode, 2
1 ... wafer, 50 ... U groove.

Claims (6)

[Claims] A first conductivity type semiconductor substrate; a first conductivity type semiconductor layer formed on a main surface of the semiconductor substrate; and a predetermined depth in a surface portion of the semiconductor layer. A second conductivity type base region (8) formed by: a first conductivity type source region (7) formed shallower than the base region in a surface layer portion of the semiconductor layer; A gate insulating film (3) formed on the channel region using a portion sandwiched between the source region and the semiconductor layer as a channel region; and a gate electrode (4) formed on the gate insulating film. A source electrode (12) electrically connected to the source region and the base region; and a drain electrode (1) formed on the back side of the semiconductor substrate.
3) wherein the impurity concentration of the first conductivity type in the semiconductor layer is substantially constant from the main surface of the semiconductor layer to a predetermined depth, and becomes higher as the depth becomes higher than the predetermined depth. A power MOSFET characterized in that: 2. The power MO according to claim 1, wherein when the depth is greater than the predetermined depth, the impurity concentration of the first conductivity type in the semiconductor layer increases linearly with an increase in concentration.
SFET. 3. The linear slope satisfies the relationship of logY = A · X + C, where X is the depth of the semiconductor layer, Y is the impurity concentration of the first conductivity type, A is the slope, and C is a constant. 3. The power MOSFET according to claim 2, wherein: 4. The power MOSFET according to claim 2, wherein the thickness of the linearly inclined region in the semiconductor layer of the first conductivity type is 3 to 10 μm. 5. The semiconductor device according to claim 2, wherein an impurity concentration in a boundary portion between the semiconductor layer and the semiconductor substrate is 8.0 × 10 ¹⁵ cm ⁻³ or more. A power MOSFET as described. 6. The semiconductor layer according to claim 2, wherein an impurity concentration at a boundary between the semiconductor layer and the semiconductor substrate is seven times or more as large as a region where the impurity concentration is substantially constant. 5. The power MOSFET according to any one of items 4 to 4.