JPH039573A - Electrostatic induction transistor - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the breakdown strength of an element and the breakdown of the element by a method wherein part of a second conductivity type gate region, which is formed in the vicinity of one main surface at the end part of a first conductivity type semiconductor layer, is provided with a protrusion part, which is formed deeper in the direction of first conductivity type drain regions. CONSTITUTION:A second conductivity type gate region 31 provided in the vicinity of one main surface of a first conductivity type semiconductor layer has a protrusion part 31a, which is formed deeper on the sides of first conductivity type drain regions 12' and 11 than the depth of the part other than the protrusion part 31a of the region 31, at part of the region 31. Accordingly, the generation of an avalanche breakdown at the interface part between the first conductivity type semiconductor layer directly under first conductivity type source regions 14 and the drain regions 12' and 11 is eliminated. Even if a reverse bias voltage value not smaller than the value of breakdown strength is applied between the gate region 31 and the drain regions 12' and 11, the inflow of hot carriers, which are generated due to the avalanche breakdown at the interface part, into the regions 14 is eliminated. Thereby, the deterioration of the breakdown strength of an element and the breakdown of the element in the case where the reverse bias voltage of a withstand voltage value or higher is applied between the gate region and the drain regions are prevented.

Description

Detailed Description of the Invention [Summary] In a surface-gate type or buried-gate type static induction transistor, a semiconductor layer having a predetermined interval near one main surface of a semiconductor layer of a first conductivity type or within the semiconductor layer of a first conductivity type is used. A part of the gate region of the second conductivity type formed at the end of the first conductivity type semiconductor layer is
Since the structure is formed deeper in the direction of the drain region of the first conductivity type, avalanche breakdown is caused by the avalanche breakdown in the first conductivity type semiconductor layer located below a part of the 6U region. The method is limited to the interface between the first conductivity type semiconductor layer and the first conductivity type drain region to prevent hot carriers generated by avalanche breakdown from flowing into the first conductivity type source region. It becomes possible to prevent the deterioration of the breakdown voltage of the device and the destruction of the device, which would otherwise occur due to carrier injection into the source region when a reverse bias voltage higher than the breakdown voltage is applied between the gate and the drain.

[Industrial application field]

The present invention provides a static induction transistor (StaticIn
The present invention relates to a static induction transistor that can prevent deterioration of the breakdown voltage of the device and prevent destruction of the device even when a reverse bias voltage higher than the breakdown voltage is applied between the gate and drain.

[Prior Art] Static induction transistors (hereinafter abbreviated as SIT) can easily be made into multi-channel transistors by having a vertical structure, so they can handle large currents, and the gate
By inserting a high resistance layer between the drains, the gate
Since it is possible to make the breakdown voltage between the drains high, it is suitable for high power applications.

FIG. 4 is a sectional view showing the structure of a conventional 5ITIO.

In the figure, an n-type substrate 11 made of Si or the like has an n
- type epitaxial layer 12 is formed, and its n- type epitaxial layer 12 is formed.
In the surface region of the type epitaxial layer 12, there is a p type gate layer).
61 area 13. An n+ type source region 14 is formed.

Further, the p+ type gate region 13 and the n'' type source region 14 are connected to A2 through contact holes formed by partially etching the oxide film 15 formed on the n− type epitaxial layer 12. The gate electrode 16 is connected to the source electrode 5.

Further, on the other main surface of the n° substrate 11, a drain electrode 18 made of A1 or the like is formed. Note that the n-type source region 14 is connected to the source electrode 1 through the polycrystalline silicon 21.
7.

In the above structure, n in the n-type epitaxial layer 12
p-type gate region 13.1 below °-type source region 14
3 is a channel region 19, and n-
The type epitaxial Ji 12 and the n' type substrate 11 serve as a drain region.

The 5ITIO having the above configuration is a normally-off type SIT, and the gate electrode 16. When a forward bias voltage higher than a predetermined voltage value is not applied between the source electrodes 17, the channel region 19 is completely depleted, and no current flows between the source and drain. .

Next, FIGS. 5(a) and 5(b) show the gate electrode (G) 16. when measuring the drain-source breakdown voltage (B Voss) and drain-gate breakdown voltage (BVOGO), respectively. 5 is a diagram showing a method of applying voltage to a source electrode (S) 17 and a drain electrode (D) 18. FIG.

When measuring the drain-source breakdown voltage (BVoss), as shown in FIG.
A reverse bias voltage (1) is applied to the drain electrode 18.

Further, when measuring the drain-gate breakdown voltage (BVIIGO), a reverse bias voltage (2) is applied between the gate electrode 16 and the drain electrode 18.

In this way, the drain-source breakdown voltage (B Vnss)
.

In any measurement of drain-gate breakdown voltage (BVDGO), the gate-drain region is reverse biased. Therefore, when measuring both the drain-source breakdown voltage (BVnss) and the drain-gate breakdown voltage (BVi+Go), the junction between the p-type gate (R11) region 13 and the n-type epitaxial layer (drain layer) 12 is reversed. As the bias is applied, a depletion region 20 is widened (formed) on both sides of the junction, especially in the n-type epitaxial layer 12 with a low impurity concentration. Then, when the reverse bias voltage V is further increased, as shown in FIG. As shown in FIG.
The electric field E at the junction between the ゛-type gate region 13 and the n-type epitaxial layer 12 is the critical electric field E at which avalanche breakdown occurs.
When crit is reached, the p' type gate region 13 and n
Avalanche breakdown occurs at the junction surface of the −-type epitaxial layer 12, and an avalanche of electron-positive pairs are generated within the depletion region 20 (in FIG. 5, the generated electrons are shown as black circles, and the holes are shown as white circles). ). Then, the internal electrons of the generated electron-hole pairs are accelerated by the electric field E in the depletion region 20, and their kinetic energy increases (becomes hot electrons), forming an n-type epitaxial layer with many crystal defects. Secondary avalanche breakdown occurs at the interface between 12 and the n-type substrate 11. Of the electron-hole pairs generated at the interface between the 〇-type epitaxial layer 12 and the n゛-type substrate 11, the electrons are accelerated by the electric field within the depletion region 20 and become so-called hot electrons, forming the n0-type substrate. 11, the genuine bill is similarly accelerated by the electric field within the depletion region 20, becomes a so-called true hole, and flows toward the p° type age region Mi13, but some of the holes (true holes) are It flows into the channel region 19 and the n° source region 14 .

[Problem to be solved by the invention]

As described above, holes generated due to secondary avalanche breakdown are transferred to the channel HMU 19 and the n-type source region 14.
If hot holes flow into the device, the breakdown voltage characteristics of the device may deteriorate, and furthermore, the device may be destroyed. Drain-source breakdown voltage E3 as shown in FIG. 5(a)
When measuring voss, the presence of holes flowing into the n0 type source region 14 can be observed as the source current 11.

The above-mentioned elemental breakdown occurs when holes (hot holes) generated by the above-mentioned secondary avalanche breakdown occur in the n-type source region 14.
It is predicted that the energy generated by the electric field E in the depletion region 20 is released as heat at the interface between the n'-type source region 14 and the n--type epitaxial layer 12.

The present invention provides a static induction transistor (SIT) that can prevent carriers generated by avalanche breakdown of the drain layer from flowing into the channel region and source region, resulting in breakdown voltage deterioration and device destruction. The purpose is to

[Means to solve the problem]

In order to achieve the above object, a static induction transistor according to a first aspect of the present invention includes a second conductive type semiconductor layer disposed at a predetermined interval near one main surface of a semiconductor layer of a first conductivity type. the source region of the first conductivity type formed shallower than the gate region between the gate region of the conductivity type and the gate region of the second conductivity type near one main surface of the semiconductor layer of the first conductivity type; and a drain region of a first conductivity type formed on the other main surface of the semiconductor layer of the first conductivity type, in the vicinity of one main surface of the semiconductor layer of the first conductivity type. The provided gate region of the second conductivity type has a protrusion formed deeper on the side of the drain region of the first conductivity type than the other gate region of the second conductivity type. Features.

Further, in order to achieve the above object, the static induction transistor of the second invention includes a semiconductor layer of a first conductivity type and a predetermined interval inside the semiconductor layer of the first conductivity type. a buried gate region of a second conductivity type buried in the first conductivity type semiconductor layer;
In a static induction transistor comprising a source region of a conductive type and a drain region of a first conductive type formed on the other main surface of the semiconductor layer of the first conductive type, The buried gate of the second conductivity type (65 region) is formed deeper in the direction of the drain region of the first conductivity type than the other buried gate of the second conductivity type (N region) in a part thereof. It is characterized in that it has a protrusion.

[Created for]

In the first invention according to claim 1, a second conductivity type gate region (hereinafter referred to as a peripheral second conductivity type gate region ) has a structure in which a part thereof has a protrusion that is formed deeper toward the drain region of the first conductivity type, so that the protrusion from the protrusion of the peripheral second conductivity type gate region The distance from the other gate region of the second conductivity type to the interface between the semiconductor layer of the second conductivity type and the drain region of the first conductivity type is the distance between the semiconductor layer of the second conductivity type and the semiconductor substrate of the first conductivity type. It is shorter than the distance to the interface. Therefore, when a reverse bias voltage is applied between the gate and drain, avalanche breakdown at the interface between the first conductivity type semiconductor layer and the first conductivity type semiconductor substrate will occur in the peripheral second conductivity type semiconductor layer.
This occurs only in the interface region directly under the protrusion of the conductive type gate region. Since the electric field of the depletion layer formed between the peripheral second conductivity type gate region and the interface section is perpendicular to the device, hot carriers generated by the avalanche breakdown are generated by the first conductivity type. It does not flow into the source region, but flows only into the peripheral second conductivity type gate region.

Therefore, avalanche breakdown does not occur at the interface between the first conductivity type semiconductor layer directly under the first conductivity type source region and the first conductivity type drain region, and a reverse bias voltage higher than the withstand voltage is prevented. Even if the voltage is applied between the gate and the drain, one hot carrier generated by avalanche breakdown at the interface will not flow into the source region of the first conductivity type, unlike in conventional static induction transistors, and the withstand voltage will decrease. When the above reverse bias voltage is applied between the gate and the drain, deterioration of the breakdown voltage of the device and destruction of the device are prevented.

Further, in the second invention as set forth in claim 2, a second conductivity type buried gate region (for convenience, expressed as a peripheral second conductivity type buried gate region) formed within the first conductivity type semiconductor layer is provided. Since the structure has a protrusion formed deeper on the side of the drain region of the first conductivity type than the buried gate region of the other second conductivity type in the negative part, the same effect as in the first invention is obtained. Therefore, avalanche breakdown at the interface between the semiconductor layer of the first conductivity type and the drain region of the first conductivity type when a reverse bias voltage higher than the withstand voltage is applied between the gate and drain is caused by
(Conductivity Type Buried Ga) Occurs only in the interface area located directly under the protrusion in the SR region. For this reason,
Similar to the first invention, avalanche breakdown does not occur at the interface directly under the first conductivity type source region,
Even if a reverse bias voltage higher than the breakdown voltage is applied, hot carriers generated due to avalanche breakdown at the interface will not flow into the source region of the first conductivity type, unlike in conventional static induction transistors, and the voltage will not exceed the breakdown voltage. This prevents the breakdown voltage of the device from deteriorating and the device from being destroyed when a reverse bias voltage of 1 is applied between the gate and drain.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional configuration diagram of a static induction transistor (SIT) which is an embodiment of the present invention.

Note that the same regions as the SIT shown in FIG.
).

The difference from the conventional 5TTIO shown in FIG. 4 is that the lateral length of the p-type gate jJ region 31 provided at the periphery of the device is longer than that of the p+-type gate region 13 of the conventional SIT. Second, the peripheral p° gate 617 region 31 (hereinafter referred to as peripheral p゛ type agate region 1) has another P゛ gate in a part of the end side of the element. The diffusion region (protrusion 31a) is provided about 2 μm deeper than the region 13.

Because of the above structure, the protrusion 31a of the peripheral p-type agate region 1 and the n-type substrate 11 are connected to each other.
The vertical distance 12 to the interface with the n-type epitaxial layer 12 is the vertical distance p° to the interface between the n-type substrate 11 and the n-type epitaxial layer 12' other than the peripheral p-type gate region 31. Distance from mold gate area 12! , is necessarily shorter than (j!+<j!z).

Therefore, as shown in FIG. 5(a), the gate electrode 16 and the drain electrode 18 are
3 or peripheral P' type gate area 31)/drain (n-
A voltage V such that the type epitaxial [12 and n' board 11] is reverse biased.

When , the depletion layer region 32 spreads in the n-type epitaxial layer 12 with a low impurity concentration, and when the reverse bias voltage (1) reaches a predetermined voltage, the peripheral p°-type gate region 3 expands.
The depletion HB SM region 32a below the protrusion 31a of No. 1 is
It first reaches the interface 33 between the n- type epitaxial layer 12' and the n+ type substrate 11. Then, after the depletion layer region 32a reaches the interface 33 between the n-type epitaxial layer 12' and the n+-type substrate 11, when the reverse bias voltage 1 is further increased, the depletion layer region 32a becomes n゛゛However, since the impurity concentration of the n-type substrate 11 is much higher than that of the n-type epitaxial layer 12', the depletion layer region 32a expands with respect to the increase in reverse bias voltage 1. The increase in width becomes smaller, and therefore, the protrusion 3 of the peripheral p+ type gate region 31
The electric field E1 at the junction 41 between the n-type epitaxial layer 1a and the n-type epitaxial layer 12' is equal to the electric field E2 at the junction between the n-type epitaxial layer 12' and a portion of the peripheral p-type agate region 1 other than the protrusion 31a. p° type gate region 13 and n-
The electric field E3 of the junction 43 with the type epitaxial layer N12' becomes larger than that of the protrusion 3 of the peripheral p° type gate region 31.
First-order avalanche breakdown occurs first at the junction between 1a and the n-type epitaxial layer N12'. This first avalanche breakdown occurs at the interface between the n-type epitaxial layer 12' and the n+-type substrate 11, which contain many crystal defects, in the same manner as described above in the [Prior Art] section. cause the next avalanche surrender.

The electric field in the depletion layer region 32 where this secondary avalanche breakdown occurs is approximately perpendicular to the n'' type substrate 11.
From the n° type substrate 11 to the peripheral p type gate? Since the holes in the generated electron-hole pairs go toward the protrusion 31a of the IL region 31, most of the holes are directed to the protrusion 3 of the peripheral p' type gate t=M region 31.
1a.

As a result, avalanche breakdown does not occur in the depletion layer region 32 directly under the n2 type source region J4, and therefore, as in the conventional case, the channel region 19 and the n2 type source region 1
Holes (hot holes) no longer flow into 4.

In this way, before avalanche breakdown occurs in the depletion layer region 32 directly under the n° type source region 14, avalanche breakdown occurs first in the depleted NeM region 32 directly under the protrusion 31a of the peripheral p'' type agate region 1. Since the channel regions 19 and n are generated in the conventional manner.

It becomes possible to prevent holes (hot holes) from flowing into the type source region 14, and it is possible to prevent deterioration of the element breakdown voltage and furthermore prevent element breakdown.

Next, a method for manufacturing an n-channel SIT having the above structure will be described with reference to FIGS. 3(a) to 3(a).

These figures are cross-sectional views showing parts of one unit of n-channel SIT, and the dimensional relationships of each part are exaggerated to make it easier to understand the process and are not proportional to the actual device.

First, as shown in FIG. 3(a), an n-type epitaxial layer is formed to a thickness of about 30μ by epitaxial growth on the entire one main surface of an n-type substrate 11 doped with a donor such as sb at a high concentration. Form 52.

Subsequently, as shown in FIG. 2), a first oxide film 41 made of 5iOz or the like is formed on the entire surface of the n-type epitaxial layer 52 to a thickness of approximately 700 nm, and then as shown in FIG. ), the first oxide film 41 located above the protrusion 31a of the peripheral P'' type gate LQ region 31 is removed by etching using a photolithography method. and,
Next, an acceptor such as B (boron) is deposited using the insulating film 41 and the photoresist 42 as a mask, and an n-type epitaxial film W on which the first oxide 1141 is not formed on the upper surface is deposited. A P-type region 43 having an impurity concentration of approximately 1019c and i is formed near the surface of I52.

Furthermore, as shown in FIG.
Using the first oxide film 41 and the photoresist 42 as a mask, an acceptor such as B (boron) is deposited again above the portion where the '-type agate region 1 is to be formed, thereby forming a p-type region 45.

Further, drive-in diffusion is performed as shown in FIG.
is further deeply diffused into the n'' type epitaxial layer 52 to form a p'' type gate 2M region 31 around the p'' type gate region 131, respectively.

Further, following this drive-in diffusion, a second insulating film 46 made of Sing is formed on the surface of the n-type epitaxial layer H52.

Furthermore, as shown in FIG.
After removing the portion above the position where Sfl is formed, SiH4 thermal decomposition method (Sfl
thermal decomposition
) etc., the second oxide film 46 is formed.
- type epitaxial layer 52 on the upper surface of polycrystalline silicon (P).
olysilicon) 47. Subsequently, donor ions such as AS (arsenic) are implanted into the upper surface of the n-type epitaxial layer 52 on which the second oxide film 46 is formed, and as shown in FIG. N-type epitaxial layer 5 on which oxide film 46 is not formed
An n° source region 14 having an impurity concentration of about 1020 cmI102O is formed at a depth of about 0.4 μm near the surface of the semiconductor substrate 2 by solid-phase diffusion. Then, the polycrystalline silicon 47 is selectively removed by photolithography, and a second oxide film 46 is deposited on the upper part of the n2 type source region 14 and a portion of the second oxide film 46 at both ends of the n2 type source region 14. Polycrystalline silicon 21 is formed.

Furthermore, as shown in FIG.

The second oxide film 46 above the mold gate region 31 is selectively removed to form a contact hole (at this time, the oxide film 15' is formed), and then sputtering or vacuum evaporation is performed. An electrode material such as No. 11 or Al-3i is formed on the entire upper surface of the n-type epitaxial layer 12' on which the oxide film 15' and the polycrystalline silicon 21 are formed. Then, the electrode material is selectively removed by photolithography to form the source electrode 15 and the gate electrode 16. Furthermore, AN,
An electrode material such as Af-3t is formed to form the drain electrode 18.

Although the above embodiment is an example of application to a surface gate type n-channel SIT, it goes without saying that the present invention can also be applied to a surface gate type p-channel SIT with the conductivity type reversed. Alternatively, it can be easily applied to an n-channel buried gate type SIT. Also, St.
The device is not limited to a device, and may be a compound semiconductor such as Ge or GaAs.

〔Effect of the invention〕

According to the present invention, when a reverse bias voltage equal to or higher than the withstand voltage is applied between the gate and the drain, avalanche breakdown that occurs at the interface between the semiconductor layer of the first conductivity type and the drain region of the first conductivity type can be suppressed. Immediately below the protrusion of the gate region of the second conductivity type provided on the endmost side near one main surface of the semiconductor layer of the first conductivity type or embedded in the endmost side of the semiconductor layer of the first conductivity type. Since the generation is made only directly under the protrusion of the buried gate region of the second conductivity type, hot carriers generated by avalanche breakdown occurring at the interface are prevented from flowing into the source region of the first conductivity type. - Even when a reverse bias voltage higher than the withstand voltage value is applied between the drains, it is possible to prevent the deterioration of the withstand voltage of the element and the destruction of the element.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional diagram of a static induction transistor (SIT) according to an embodiment of the present invention, and Fig. 2 shows the depletion layer region in the above embodiment when a reverse bias voltage is applied between the gate and drain. 3(a) to 3(c) are manufacturing process diagrams explaining the manufacturing method of the above embodiment; FIG. 4 is a cross-sectional configuration diagram of a conventional static induction transistor (SIT); FIG. 5 (a) and (b) are the drain-source breakdown voltage BV oss *drain-gate breakdown voltage BVoc, respectively. FIG. 6 is a diagram showing the spread of the depletion layer 'vM region when a reverse bias voltage is applied between the gate and drain in the conventional static induction transistor. DESCRIPTION OF SYMBOLS 11... n'' type substrate, 12'... n- type epitaxial layer, 13... p' type gate region, 14... n'' type source region, 15'... oxide film, 16. ...Gate electrode, 17...Source electrode, 18...Drain electrode, 19...Channel region, 31...Peripheral p'-type gate region, 31a...Protrusion.

Claims (2)

[Claims] (1) a second conductivity type gate region disposed at a predetermined interval near one main surface of the first conductivity type semiconductor layer; and a second conductivity type gate region disposed near one main surface of the first conductivity type semiconductor layer; a source region of the first conductivity type formed shallower than the gate region between the gate regions of the conductivity type; and a source region of the first conductivity type formed on the other main surface of the semiconductor layer of the first conductivity type. In the static induction transistor including a drain region, the second conductivity type gate region provided near one main surface of the first conductivity type semiconductor layer has a portion of the second conductivity type gate region provided with the second conductivity type semiconductor layer.
A static induction transistor characterized by having a protrusion formed deeper in the drain region of the first conductivity type than in the gate region of the conductivity type. (2) a semiconductor layer of a first conductivity type, a buried gate region of a second conductivity type embedded at a predetermined interval inside the semiconductor layer of the first conductivity type, and a main part of the semiconductor layer of the first conductivity type; the first conductivity type source region having a higher impurity concentration than the first conductivity type semiconductor layer formed near the surface; and a first conductivity type formed on the other main surface of the first conductivity type semiconductor layer. In the static induction transistor, the buried gate region of the second conductivity type at the endmost part buried in the semiconductor layer of the first conductivity type has a portion of the buried gate region of the second conductivity type buried in the semiconductor layer of the first conductivity type. 2 conductivity type buried gate region.
A static induction transistor characterized by having a protrusion formed deeper on a drain region side of a conductivity type.