JP2000188399A - Silicon carbide semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress outer diffusion of impurity and to prevent the contact resistance of a source region connected to a source electrode from becoming high. SOLUTION: Regions 4a where nitrogen is made to be dopant are formed in positions deeper than in upper faces connected to a source electrode 10 and regions 4b, where phosphorus whose mass is larger than that of nitrogen is set as a dopant are formed in places, which are brought into contact with a source electrode in a state shallower than the regions 4b in n+-type source regions 4. In phosphorus whose mass is larger than nitrogen, diffusion rate becomes slow, since mass is heavier and it is difficult to diffuse outward as compared to nitrogen. Thus, outer diffusion in the part which is brought into contact with the source electrode 10 can be reduced in the n+-type source regions 4 and the contact resistance of the n+-type source regions 4 can be prevented from becoming high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate field effect transistor, particularly a vertical power MOSF for high power.
It is about ET.

[0002]

2. Description of the Related Art In a silicon carbide semiconductor device, for example, an n-channel type vertical power MOSFET, an n-type impurity is heavily doped at a connection portion with a source electrode.
^{A +} type source region is provided.

The n ⁺ -type source region is formed by doping nitrogen (N), which is an n-type impurity, at a high concentration and then activating the nitrogen. In this case, so that in order to reduce the contact resistance with the source electrode, and as the resistance value of the n ⁺ -type source region is as low as possible, to form the n ⁺ -type source region as concentrated as possible.

[0004]

However, during the heat treatment for activating the nitrogen, the nitrogen diffuses out (O
out diffusion, the concentration of the n ⁺ -type source region decreases in the surface layer of the n ⁺ -type source region, that is, in the contact portion with the source electrode, and the contact resistance between the source electrode and the n ⁺ -type source region decreases. And n
There is a problem that the sheet resistance of the ⁺ type source region is increased.

The present invention has been made in view of the above problems, and has as its object to suppress the external diffusion of impurities so that the contact resistance of the source region connected to the source electrode and the sheet resistance of the source region do not increase. I do.

[0006]

In order to achieve the above object, the following technical means are employed.

According to the first aspect of the present invention, the step of forming the source region (4) includes the step of forming the source region (4) at a position deeper than the upper surface connected to the source electrode (10) by a predetermined depth. A first source region including a first dopant (4
forming a) and forming a second source region (4b) including a second dopant having a larger mass than the first dopant at a position shallower than the first source region. Features.

The second dopant, which has a larger mass than the first dopant, has a slower diffusion speed due to the higher mass, and is less likely to diffuse outside than the first dopant.

Therefore, the first region is located at a position deeper than the upper surface connected to the source electrode by a predetermined depth in the source region.
A first source region containing a dopant is formed, and a position shallower than the first source region is formed as a second source region containing a second dopant having a larger mass than the first dopant. External diffusion at the portion where the contact is made can be reduced, and the contact resistance of the source region and the sheet resistance of the source region can be prevented from increasing.

According to a second aspect of the present invention, a storage-type silicon carbide semiconductor device in which a first conductivity type surface channel layer (5) is formed in a surface layer portion of a base region (3) is similar to the first aspect. The effect of can be obtained.

[0013] The third aspect of the present invention is characterized in that the same mask is used for both the mask for forming the first source region and the mask for forming the second source region.

Thus, the first source region and the second source region can be formed without displacement. Therefore, there is no need to design a cell in consideration of the shift amount, and the cell size can be reduced. In addition, the manufacturing process can be simplified by using the same mask.

According to the fourth aspect of the present invention, in the lateral MOSFET having a channel formed on the surface, the drain region side of the junction between the well region (103) and the drain region (107) is ion-implanted with a light dopant. Since it is formed, there are few defects generated at the time of ion implantation, the reverse leak current at the junction is small, and the lateral MOSFET can be favorably operated.

According to the fifth aspect of the present invention, even in a vertical structure in which a signal is applied to the source electrode (57) and the base electrode (58) separately, the source region is formed in the same manner as in the fourth aspect. In this case, since the junction is formed by ion implantation of a light dopant, the number of defects generated at the time of ion implantation is small, the reverse leakage current of the junction is reduced, and the vertical MOSFET can be operated satisfactorily.

As described in claim 6, by using nitrogen as the light first dopant and phosphorus as the heavy second dopant, the effects described in claims 1 to 5 can be obtained. Further, in this case, since nitrogen has a lower activation energy than phosphorus, the carrier concentration can be increased as compared with the case where the same impurity concentration profile is formed using only phosphorus. As a result, the sheet resistance of the source region can be reduced.

According to the eighth and ninth aspects of the present invention, when nitrogen is used as the dopant, the contact between the source region and the source electrode material can obtain good ohmic characteristics, so that the source region is formed using only phosphorus as the dopant. In this case, the Schottky characteristic does not occur, and the contact resistance can be reduced.

Since the outdiffusion is suppressed by the presence of the second dopant as in claims 7 and 8, the first dopant may be ion-implanted to a portion in contact with the source electrode. In addition, since the volume of the first source region formed by the first dopant can be increased, the sheet resistance of the source region can be further reduced as compared with the structure of the first aspect.

According to the eleventh aspect, the source region has a first source region containing a first dopant at a position deeper by a predetermined depth from an upper surface in contact with the source electrode; A second source region including a second dopant having a larger mass than the first dopant is provided at a position shallower than the source region and in contact with the source electrode.

As described above, the second source region formed at a position in contact with the source electrode has a second source region having a heavier mass than the first source region formed at a position where the junction depth is deeper than the second source region. When the source region is formed using a dopant, the contact resistance of the source region can be reduced.

According to a twelfth aspect of the present invention, the source region has a first source region (4c) containing a first dopant from a top surface in contact with the source electrode to a position at a predetermined depth, and at least the first source region includes a first dopant. Even if it has a second source region (4b) containing a second dopant heavier than the first dopant so as to overlap on an upper surface where the first source region and the source electrode are in contact with each other, Item 1
The same effect as that of No. 1 can be obtained.

Note that the reference numerals in parentheses indicate the correspondence with specific means described in the embodiment described later.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 1 shows a normally-off type n-channel planar MOSFET (hereinafter referred to as a vertical power MOSFET) formed by applying an embodiment of the present invention.
1 shows a cross-sectional configuration. This device is suitable for application to a rectifier of an inverter or a vehicle alternator. Hereinafter, a vertical power MOSFET based on FIG.
Will be described.

The n ⁺ type semiconductor substrate 1 made of silicon carbide has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. Main surface 1a of this n ⁺ type semiconductor substrate 1
An n ⁻ -type epitaxial layer (hereinafter, referred to as an n ⁻ -type epi layer) 2 made of silicon carbide having a lower dopant concentration than the substrate 1 is stacked thereon.

A p-type base region 3 having a predetermined depth is formed in a predetermined region in the surface layer portion of n ⁻ -type epi layer 2. This p-type base region 3 is formed using B as a dopant, and has a concentration of about 1 × 10 ¹⁷ cm ⁻³ or more.

A low resistance n ⁺ -type source region 4 shallower than the base region 3 is formed in a predetermined region of the surface of the p-type base region 3. A region (first source region) 4a having a deep junction depth in the n ⁺ type source region 4
A relatively light mass of nitrogen (N) is doped as the type impurity, and a region (second source region) 4b having a shallow junction depth in the n ⁺ type source region 4 is more n-type impurity than nitrogen. Is also doped with heavy phosphorus (P) or the like.

Specifically, as shown in the concentration profile of each element shown in FIG. 2, the concentration of phosphorus (P) is n ⁺
Has become darkest between the surface of the source region 4 to a predetermined depth, the concentration of nitrogen (N) is, n ⁺ -type source region 4
From the position deeper than the surface by a predetermined depth. As described above, the region 4a and the region 4b respectively distinguish the region where the nitrogen is the highest and the region where the phosphorus is the highest. Actually, nitrogen and phosphorus are mixed near the interface between the region 4a and the region 4b. It is in a state where it has been done.

Further, as can be seen from FIG. 2, in the region 4b, phosphorus has a high concentration entirely from the surface to the inside of the n ⁺ type source region 4.

Furthermore, n ⁺ -type source region 4 and the n ^- so as to connect the type epi layer 2, the surface portion of the p-type base region 3 n
^The -type SiC layer 5 is extended. This n ⁻ -type SiC layer 5 is formed by epitaxial growth.
Epitaxial films having 4H, 6H and 3C crystals are used. The n ⁻ -type SiC layer 5 functions as a channel forming layer during operation of the device. Hereinafter, n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The surface channel layer 5 is formed using N (nitrogen) as a dopant, and the dopant concentration is as low as about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , for example. , N ⁻ -type epi layer 2 and p-type base region 3 are lower than the dopant concentration. By operating in the storage mode with such a structure, the mobility of the channel portion can be increased and the channel resistance can be reduced as compared with the inversion type. As a result, low on-resistance is achieved.

The n ^- type epi layer 2 located between the p-type base regions 3 constitutes a so-called J-FET section 6.

Gate oxide film 7 is formed on the upper surface of surface channel layer 5 and the upper surface of n ⁺ type source region 4 by thermal oxidation. Further, a gate electrode 8 is formed on the gate oxide film 7. Gate electrode 8 is covered with insulating film 9. LTO (Low Tempe) as the insulating film 9
(Rate oxide) film is used. A source electrode 10 is formed on insulating film 9, and source electrode 10 is in contact with n ⁺ -type source region 4 and p-type base region 3. A drain electrode layer 11 is formed on the back surface 1b of the n ⁺ type semiconductor substrate 1.

Next, a manufacturing process of the MOSFET shown in FIG. 1 will be described with reference to FIGS.

[Step shown in FIG. 3A] First, the n-type 4
An H, 6H, or 3C-SiC substrate, that is, an n ⁺ type semiconductor substrate 1 is prepared. Here, the n ⁺ type semiconductor substrate 1
Has a thickness of 400 μm and a main surface 1a of (000
1) Si plane or (112-0) a plane. On the main surface 1a of the substrate 1, an n ⁻ -type epi layer 2 having a thickness of 5 μm is epitaxially grown. In this example, the n ⁻ -type epi layer 2 has the same crystal as that of the underlying substrate 1 and has n-type 4H or
Or it becomes a 3C-SiC layer.

[Step shown in FIG. 3B] n ^- type epi layer 2
The LTO film 20 is disposed in a predetermined region above the mask, and B ions are implanted using the LTO film 20 as a mask. At this time, the ion implantation conditions are that the temperature is 700 ° C. and the dose is 1 × 10 ¹⁶ cm ⁻² . Thereafter, activation annealing at 1600 ° C. for 30 minutes is performed as a heat treatment to activate B in the impurity implantation layer 30 to form the p-type base region 3. As a result, a J-FET portion 6 is formed between the p-type base regions 3.

[Step shown in FIG. 3C] After the LTO film 20 is removed, the impurity concentration is 1 × 10 ¹⁶ cm ⁻² or less on the n ⁻ -type epi layer 2 including the surface of the p-type base region 3. Then, an n-type surface channel layer 5 having a thickness of 0.3 μm or less is epitaxially grown.

At this time, in order to make the vertical power MOSFET a normally-off type, the thickness (film thickness) of the surface channel layer 5 is changed from the p-type base region 3 when no voltage is applied to the gate electrode 8 to the surface channel. It is set to be smaller than the sum of the extension amount of the depletion layer extending to the layer 5 and the extension amount of the depletion layer extending from the gate oxide film 7 to the surface channel layer 5.

Specifically, the amount of extension of the depletion layer extending from p-type base region 3 to surface channel layer 5 is determined by the built-in voltage of the PN junction between surface channel layer 5 and p-type base region 3, and the gate oxide From film 7 to surface channel layer 5
The amount of extension of the depletion layer that spreads is determined by the charge of the gate oxide film 7 and the work function difference between the gate electrode 8 (metal) and the surface channel layer 5 (semiconductor). The film thickness is determined.

Such a normally-off type vertical power M
The OSFET can prevent a current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like, so that safety can be ensured as compared with a normally-on type.

As shown in FIG. 1, the p-type base region 3 is in contact with the source electrode 10 and is in a ground state. Therefore, the surface channel layer 5 and the p-type base region 3
The surface channel layer 5 can be pinched off using the built-in voltage of the PN junction. For example, when the p-type base region 3 is not grounded and is in a floating state, the depletion layer cannot be extended from the p-type base region 3 using the built-in voltage.
It can be said that bringing the p-type base region 3 into contact with the source electrode 10 is an effective structure for pinching off the surface channel layer 5.

By increasing the impurity concentration of the p-type base region 3, the built-in voltage can be more utilized.

With the above configuration, a normally-off type MOSFET that operates in the accumulation mode can be formed.

In this embodiment, the vertical power MOSFET is manufactured from silicon carbide. However, if it is to be manufactured using silicon, the impurity layers such as the p-type base region 3 and the surface channel layer 5 are formed. Since it is difficult to control the amount of thermal diffusion of the dopant forming the p-type base region 3 and the dopant forming the n ⁺ -type source region 4 in the above-described operation, the semiconductor device operates in the same accumulation type mode as the above configuration, In addition, it becomes difficult to manufacture a normally-off type MOSFET. Therefore, by using SiC as in the present embodiment, a vertical power MOSFET can be manufactured with higher accuracy than when silicon is used.

A normally-off type vertical power MOS
In order to form an FET, it is necessary to set the thickness of the surface channel layer 5 so as to satisfy the above conditions. However, since silicon has a low built-in voltage, the thickness of the surface channel layer 5 may be reduced. Considering that the impurity concentration must be reduced and the diffusion amount of the impurity ions is difficult to control, it can be said that manufacturing is extremely difficult.
However, when SiC is used, the built-in voltage is about three times as high as that of silicon, and the surface channel layer 5 can be formed thicker or with a higher impurity concentration. Therefore, it is necessary to manufacture a normally-off type storage MOSFET. Can be said to be easy.

[Step shown in FIG. 4A] Next, an LTO film 21 is disposed in a predetermined region on the surface channel layer 5, and using this as a mask, nitrogen (N) as an n-type impurity is ion-implanted. . The ion implantation conditions at this time are as follows.
And changing the ion implantation energy (for example, 2
00 eV, 130 eV), and the dose amount is 5 × 10 ¹⁵ cm ^−2.
I am trying to be. Thereby, the surface channel layer 5
Is doped with nitrogen in the region 4a which is deeper than the surface by a predetermined depth.

[Step shown in FIG. 4 (b)]
Using the film 21 as a mask, phosphorus (P), which is an n-type impurity having a higher mass than nitrogen, is ion-implanted. The ion implantation conditions at this time are as follows: the temperature is 700 ° C., and the ion implantation energy is changed (for example, 200 eV, 120 eV,
60 eV, 25 eV) with a dose of 3.5 × 10 ¹⁵ cm
^-2 . As a result, the region 4b from the surface of the surface channel layer 5 to a predetermined depth is doped with phosphorus.

Thereafter, the n ⁺ -type source region 4 is formed by activating the n-type impurity ions (nitrogen and phosphorus) implanted by the heat treatment.

At this time, since phosphorus has a higher mass than nitrogen, the diffusion rate during the heat treatment is low, and the amount of phosphorus that is diffused outside is smaller than when the n ⁺ -type source region 4 is formed using only nitrogen as a dopant. Less is.

[0049] Therefore, as shown in FIG. 2 described above, the remaining phosphorus high concentration in a surface portion of the n ⁺ -type source region 4, the source electrode 10 of the n ⁺ -type source region 4 (see FIG. 1) The region 4b serving as the contact portion can be made to have a high concentration, that is, a low resistance.

Thus, a region 4a having a deep junction depth is doped with a high concentration of nitrogen, and a region 4b having a small junction depth is doped with a high concentration of phosphorus.
^{A +} type source region 4 can be formed. In such a configuration, since the energy level of nitrogen is 52.1 meV and the energy level of phosphorus is 85.0 meV, when the same impurity concentration is given, the carrier concentration of nitrogen becomes higher. Become. Therefore, the resistance of n ⁺ -type source region 4 can be reduced as compared with the case where the same impurity profile is formed only with phosphorus.

In a portion where nitrogen and phosphorus coexist in the vicinity of the interface between region 4a and region 4b, both nitrogen and phosphorus are donors (negative charges), so they repel each other in the crystal and are separated from each other. It will be stably present at the position where it is located. Therefore, the energy level of nitrogen is usually 52.1
and the energy level of phosphorus is 85.0 meV.
However, the effect that the energy level can be made lower than the energy level of nitrogen in the portion where nitrogen and phosphorus coexist is also obtained.

[Step shown in FIG. 4 (c)]
After removing the film 21, the LTO film 22 is disposed in a predetermined region on the surface channel layer 5 by using a photoresist method, and the surface channel layer 5 on the p-type base region 3 is partially Is removed by etching.

[Step shown in FIG. 5 (a)] After the LTO film 22 is removed, a gate oxide film 7 is formed on the substrate by wet oxidation (including a pyrogenic method using H ₂ + O ₂ ). At this time, the ambient temperature is 1080 ° C.

Thereafter, a gate electrode 8 made of polysilicon is deposited on the gate insulating film 7 by LPCVD.
The film formation temperature at this time is 600 ° C.

[Step shown in FIG. 5B] Subsequently, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the gate insulating film 7. More specifically,
The film formation temperature is 425 ° C., and annealing is performed at 1000 ° C. after the film formation.

Thereafter, after the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature, annealing is performed at 1000 ° C., whereby the vertical power MOSFET shown in FIG. 1 is completed.

The vertical power MOS completed as described above
The operation (operation) of the FET will be described.

The MOSFET operates in a normally-off type accumulation mode. When no voltage is applied to the gate electrode 8, carriers in the surface channel layer 5 are formed between the p-type base region 3 and the surface channel layer 5. The entire region is depleted by a potential difference caused by a difference in electrostatic potential between them and a difference in work function between the surface channel layer 5 and the gate electrode 8. Then, by applying a voltage to the gate electrode 8, a potential difference caused by the sum of a work function difference between the surface channel layer 5 and the gate electrode 8 and an externally applied voltage is changed. As a result, the state of the channel can be controlled.

That is, the work function of the gate electrode 8 is set to the first work function, the work function of the p-type base region 3 is set to the second work function, and the work function of the surface channel layer 5 is set to the third work function. At this time, by utilizing the difference between the first to third work functions, the first to third work functions and the impurity concentration and the film thickness of the surface channel layer 5 are depleted so that n-type carriers in the surface channel layer 5 are depleted. The thickness can be set.

In the off state, the depletion region is p
It is formed in the surface channel layer 5 by the electric field created by the mold base region 3 and the gate electrode 8. When a positive bias is supplied to the gate electrode 8 from this state, the interface between the gate insulating film (SiO ₂ ) 7 and the surface channel layer 5 moves from the n ⁺ type source region 4 to the n ⁻ type drift region 2. An extended channel region is formed and is switched on. At this time, electrons flow from the n ⁺ type source region 4 through the surface channel layer 5 to the surface channel layer 5.
To the n ⁻ -type epi layer 2. Then, the n ^- type epi layer 2
When reaching the (drift region), the electrons flow vertically to the n ⁺ type semiconductor substrate 1 (n ⁺ drain).

As described above, by applying a positive voltage to the gate electrode 8, a storage channel is induced in the surface channel layer 5, and carriers flow between the source electrode 10 and the drain electrode 11.

Here, the vertical power MOSFET shown in FIG.
For T, the applied voltage to the gate electrode 8 is changed,
The change in drain current was examined. FIG. 6 shows the result.
For reference, the vertical power MOSFET shown in FIG.
The experimental results for those obtained by doping only n with the n ⁺ -type source region 4 as the n-type impurity are also indicated by dotted lines in FIG.

The change in the drain current depends on the vertical power MOS.
It depends on the magnitude of the contact resistance of the FET, and when an equivalent voltage is applied to the gate electrode 8, the larger the drain current, the lower the contact resistance.

As can be seen from the results shown in FIG. 6, the region 4a of the n ⁺ type source region 4 having a large junction depth is formed by using nitrogen as a dopant, and the region 4b having a small junction depth is formed by using phosphorus as a dopant. , The contact resistance is smaller than when only nitrogen is used as the dopant for the n ⁺ type source region 4.

[0065] The results also by using a heavy mass such as phosphorus than nitrogen as a dopant for a shallow region 4b junction depth of the n ⁺ -type source region 4, from the surface portion of the n ⁺ -type source region 4 It can be said that a reduction in impurity concentration due to external diffusion can be prevented, and contact resistance can be reduced.

Further, the sheet resistance when the n ⁺ -type source region 4 was formed using nitrogen and phosphorus as dopants was examined. Specifically, the length (d) of the contact portion of the n ⁺ type source region 4 was changed using the TLM method, and the respective resistance values (R) were measured. The result is shown in FIG.
Note that, in this figure, a dotted line shows a change in the resistance value when the dopant of the n ⁺ type source region 4 is only nitrogen as a reference. In this figure, the rate of change of the resistance value when the contact interval is changed, that is, the slope of the graph is proportional to the sheet resistance.

As shown in this figure, the sheet resistance is lower when the n ⁺ -type source region 4 is formed using nitrogen and phosphorus as dopants than when only nitrogen is used as the dopant. The effect that can be obtained is also obtained.

(Second Embodiment) A second embodiment of the present invention will be described. In the first embodiment, the region 4a formed of light nitrogen in the n ⁺ -type source region 4 is made deeper than the region 4b heavier than nitrogen.
As in the present embodiment, the region 4b may be completely covered by the region 4a, and the region 4b may be separated from the p-type base region 3. FIG. 8 shows the MOS in the present embodiment.
The manufacturing process of the FET will be described with reference to FIGS. Since the MOSFET of the present embodiment has substantially the same configuration as the MOSFET of the first embodiment, only different portions will be described.

First, as in the first embodiment, FIG.
(C) are performed. Then, after performing the processes of FIGS. 8A and 8B described below, the MOSFET of the present embodiment is manufactured by performing the processes of FIG. 4C and the subsequent processes as in the first embodiment. You. [Step shown in FIG. 8 (a)] An LTO film 21 is disposed in a predetermined region on the surface channel layer 5 and n is
Phosphorus (P) as a type impurity is ion-implanted. The ion implantation conditions at this time are as follows: the temperature is set to 700 ° C., and the ion implantation energy is changed (for example, 200 keV, 120 keV).
keV, 60 keV, 25 keV), and the dose amount is 3.5.
× 10 ¹⁵ cm ^-2 . As a result, the region 4b from the surface of the surface channel layer 5 to a predetermined depth is doped with phosphorus.

[Step shown in FIG. 8B] Next, the periphery of the opening of the LTO film 21 is lightly etched with, for example, dilute HF to form an LTO film 23 having an enlarged opening.

Using this LTO film 23 as a mask, nitrogen (N), which is an n-type impurity lighter in mass than phosphorus, is ion-implanted. The ion implantation conditions at this time are such that the temperature is 700 ° C. and the ion implantation energy is changed (for example, 20 ° C.).
0 keV, 120 keV, 60 keV, 50 keV, 2
5 keV), and the dose is set to 5 × 10 ¹⁵ cm ⁻² . As a result, the region 4a located from the surface of the surface channel layer 5 to a predetermined depth is doped with nitrogen,
The region 4b is covered with the region 4a, and the region 4b is separated from the p-type base region 3.

[0072] Then, the implanted n-type impurity ions (nitrogen and phosphorus) by activating to form the n ⁺ -type source region 4 by heat treatment.

At this time, since phosphorus has a higher mass than nitrogen, the diffusion rate during the heat treatment is low, and the amount of phosphorus that is diffused outside is smaller than when the n ⁺ -type source region 4 is formed using only nitrogen as a dopant. Is reduced. Since the potential inside the crystal is distorted by the presence of the phosphorus dopant layer, diffusion is suppressed even when nitrogen is ion-implanted to the surface.

[0074] Therefore, the remaining phosphorus and nitrogen high concentration in a surface portion of the n ⁺ -type source region 4, high concentration contact portion and a region 4b of the source electrode 10 of the n ⁺ -type source region 4, i.e. low Can be resistance.

In the overlapping portion between the region 4b and the region 4a, since both nitrogen and phosphorus are donors (negative charges), they are repelled in the crystal and stably exist at positions separated from each other. Become. For this reason, the energy level of nitrogen is usually 52.1 meV, and the energy level of phosphorus is 85.0 meV. In the portion where nitrogen and phosphorus coexist, the energy level is higher than that of nitrogen. Is also obtained.

As described above, the p-type base region 3 and the n-type
By forming the n-type layer at the junction of the ⁺ type source region 4 with nitrogen, which is a lighter element than phosphorus, implantation damage can be reduced and leak current can be reduced.

FIG. 9 shows a case where only nitrogen is ion-implanted into the p-type substrate, a case where only phosphorus is ion-implanted, and a case where nitrogen and phosphorus are ion-implanted so that phosphorus is covered with nitrogen. 5 shows the result of measuring the reverse leakage current of the PN junction. From this figure, it can be seen that the leakage current can be suppressed by forming so that the phosphorus injection layer is covered with nitrogen.

This indicates that the configuration is suitable for application to an application in which a source electrode and a base electrode are separately used as electrodes. For example, as shown in FIG. 10, the present invention can be applied to a case where a current detection function cell is built in a MOSFET (see Japanese Patent Publication No. 7-77262).

That is, in the MOSFET shown in FIG. 10, a p-type base region 53 is formed in a surface layer portion of an n ⁻ -type layer 52 formed on an n-type substrate 51, and
An n ⁺ -type source region 54 is formed in the surface layer of p-type base region 53, and a gate oxide is formed on p-type base region 53 sandwiched between n ⁺ -type source region 54 and n ⁻ -type layer 52. A gate electrode 56 is formed via the film 55. The source electrode 57 electrically connected to the n ⁺ -type source region 54 is separated from the base electrode 58 electrically connected to the p-type base region 53.

In the MOSFET thus configured, the source electrode 57 and the base electrode 58 are electrically separated from each other.
The source electrode 57 relative to the base electrode 58 is operated in the state a positive voltage, i.e., a reverse bias to the PN junction is applied, but such MOSFET n ⁺ -type source region 54
It is preferred that the above method be applied to the formation of.

Further, as shown in this embodiment, when the region 4a using phosphorus as a dopant is covered with the region 4a using nitrogen as a dopant, the volume of the region 4a formed by the nitrogen dopant can be increased. it can. For this reason, compared to a structure in which nitrogen is not ion-implanted into the surface,
The sheet resistance of the source region can be further reduced. Furthermore, since the ohmic contact between the region 4a using nitrogen as a dopant and the metal alloy layer formed by implanting the electrode material with SiC is better than the contact with the region 4b using phosphorus as a dopant, the contact resistance is reduced. There is also an effect.

FIGS. 11 (a) to 11 (c) show that the ohmic property of the nickel (Ni) electrode was measured by IV measurement when the dopant was nitrogen, phosphorus, and when phosphorus and nitrogen were overlapped. The result of the measurement is shown. From this figure, it can be seen that good ohmic properties are obtained when the dopant is nitrogen and nitrogen and phosphorus are superimposed, but that when phosphorus is used alone, it has Schottky characteristics.

(Other Embodiments) In the above embodiment, n ⁺
Phosphorus is used as the dopant in the region 4 to suppress external diffusion from the shallow junction region 4b of the mold source region 4, but a dopant having a heavier mass than the dopant implanted into the deep junction region 4a. Therefore, the effect of suppressing external diffusion can be obtained even with other materials.

In the above embodiment, the case where the present invention is applied to the storage type planar MOSFET is described. However, other silicon carbide may be used as long as a high concentration contact region is formed at the junction with the electrode. It is also possible to apply the present invention to a semiconductor device, for example, an inversion type MOSFET or a trench gate type MOSFET.

Further, such a configuration that nitrogen of the dopant is ion-implanted to the surface together with phosphorus to cover the phosphorus doping layer is also effective for a lateral type MOSFET. FIG. 12 shows a lateral type MOS of a power IC.
This shows a case where the present invention is applied to an FET.

The power IC is composed of one p-type semiconductor substrate 10
NMOSF is added to the n-type well layer 102 grown on
CMOSFET equipped with ET and pMOSFET,
The configuration is such that an npn transistor, a pnp transistor, and a diode are formed.

The nMOSFET includes a p-type well region 10 formed in a predetermined region of the n-type well layer 102.
3. A gate oxide film 104 formed on the surface of the p-type well region 103, a gate electrode 105 formed on the gate oxide film 104, and a surface layer portion of the p-type well region 103 below the gate electrode 105 as a channel region. An n-type source region 106 and a drain region 107 formed on both sides of the channel region, and a source electrode 1 connected to each of the source region 106 and the drain region 107.
08 and the drain electrode 109.

The drain electrode 109 of this nMOSFET
Since the p-well region 103 and the p-well region 103 need to be electrically isolated from each other, it is effective to employ the above configuration in forming the drain region 107. Thereby, the source electrode 1
08 and the drain electrode 109, and the junction between the drain and the p-well region is formed of nitrogen, which is a lighter element than phosphorus. Can be reduced. Thereby, a good MOSFET operation can be obtained.

[0089]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a planar MOSFET formed by applying an embodiment of the present invention.

FIG. 2 is a diagram showing a concentration profile of an n-type impurity in an n ⁺ -type source region 4.

FIG. 3 is a view showing a manufacturing process of the planar MOSFET shown in FIG. 1;

FIG. 4 is a view showing a manufacturing step of the planar MOSFET following FIG. 3;

FIG. 5 is a view showing a manufacturing step of the planar MOSFET following FIG. 4;

FIG. 6 is a diagram for explaining a contact resistance of an n ⁺ type source region 4;

FIG. 7 is a diagram for explaining a sheet resistance of an n ⁺ type source region 4;

FIG. 8 is a view showing a manufacturing process of the MOSFET according to the second embodiment of the present invention.

FIG. 9 is a diagram showing a reverse current-leakage current characteristic of each n-type impurity.

FIG. 10 is a diagram showing a cross-sectional configuration of a MOSFET in which a base electrode 58 and a source electrode 57 are separated.

FIG. 11 is a diagram showing a result of measuring ohmic characteristics of each n-type impurity.

FIG. 12 is a diagram illustrating a cross-sectional configuration of a power IC according to another embodiment.

[Explanation of symbols]

1 ... n ⁺ -type semiconductor substrate, 2 ... n ^-- type epi layer, 3 ... p-type base region, 4 ... n ⁺ -type source region, 4a ... region using nitrogen as dopant, 4b ... region using phosphorus as dopant, 5: surface channel layer, 7: gate insulating film, 8: gate electrode, 9: insulating film, 10: source electrode, 11: drain electrode.

Claims (13)

[Claims] A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a second conductivity type base region (3) in a predetermined region of a surface layer portion of the semiconductor layer; and forming a first region shallower than a depth of the base region in a predetermined region of the surface layer portion of the base region. Forming a conductive type source region (4); and forming a gate electrode (8) on the base region sandwiched between the source region and the semiconductor layer via a gate insulating film (7). A step of forming a source electrode (10) in contact with the base region and the source region; and a step of forming a drain electrode (11) on the semiconductor substrate. Of the source region, First comprising a first dopant in serial becomes a predetermined depth deeper than the upper surface in contact with the source electrode position
Forming a source region (4a); having a depth smaller than the first source region, overlapping with the first source region, and having a mass greater than the first dopant at a position in contact with the source electrode. Forming a second source region (4b) containing a large second dopant. 2. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. A step of forming a second conductivity type base region (3) in a predetermined region of a surface layer portion of the semiconductor layer; and forming a first conductivity type surface channel layer (5) in a surface layer portion of the base region. Forming a first conductivity type source region (4) in contact with the surface channel layer in a predetermined region of a surface portion of the base region and shallower than a depth of the base region; Forming a gate electrode (8) via a gate insulating film (7), forming a source electrode (10) in contact with the base region and the source region, and forming a drain electrode (11) on the semiconductor substrate. ) To form Forming the source region, the first region including the first dopant at a position deeper than the upper surface in contact with the source electrode by a predetermined depth in the source region.
Forming a source region (4a); having a depth smaller than the first source region, overlapping with the first source region, and having a mass greater than the first dopant at a position in contact with the source electrode. Forming a second source region (4b) containing a large second dopant. 3. The carbonization device according to claim 1, wherein the same mask is used as a mask for forming the first source region and a mask for forming the second source region. A method for manufacturing a silicon semiconductor device. 4. A first conductivity type semiconductor layer (102) made of silicon carbide having a higher resistance than the semiconductor substrate on a main surface of a first conductivity type semiconductor substrate (101) made of silicon carbide.
Forming a second conductivity type well region (103) in a predetermined region of the semiconductor layer; and forming a gate electrode (105) on the well region via a gate insulating film (104). Forming a first conductive type source region (106) and a first conductive type drain region (107) on both sides of the gate electrode in the well region to form a channel region below the gate electrode. ), Forming a source electrode (108) in contact with the well region and the source region, and forming a drain electrode (109) in contact with the drain region. The step of forming a region includes forming a first drain region containing a first dopant in at least a portion of the drain region that forms a junction with the well region. A second drain region having a second dopant having a larger mass than the first dopant in the first drain region so as to have an overlapping portion with the first drain region and to be separated from the well region. Forming a silicon carbide semiconductor device. 5. A first conductivity type semiconductor layer made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate made of silicon carbide. Forming a second conductivity type base region (53) in a predetermined region of the semiconductor layer; and forming a first conductivity type source region (shallower than the depth of the base region) in a predetermined region of the base region. Forming a gate electrode (56) via a gate insulating film (55) on the base region sandwiched between the source region and the semiconductor layer; Forming a contact source electrode (57), forming a base electrode (58) in contact with the base region, and forming a drain electrode (59) on the back side of the semiconductor substrate; The saw Forming a first source region containing a first dopant in at least a portion of the source region that forms a junction with the base region; and forming an overlapping portion with the first source region. The first source region is separated from the base region by the first source region.
Forming a second source region containing a second dopant having a larger mass than the dopant. 2. A method for manufacturing a silicon carbide semiconductor device, comprising: 6. Use of nitrogen as the first dopant,
The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein phosphorus is used as the second dopant. 7. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a second conductivity type base region (3) in a predetermined region of the semiconductor layer; and forming a first conductivity type source region (shallower than a depth of the base region) in a predetermined region of the base region. 4) forming a gate electrode (8) on the base region sandwiched between the source region and the semiconductor layer via a gate insulating film (7); Forming a source electrode (10) in contact with the source region; and forming a drain electrode (11) on the back surface side of the semiconductor substrate. At least before Forming a first source region (4a) containing a first dopant in a portion forming a junction with the base region; and having an overlapping portion with the first source region so as to be separated from the well region. The first source region in the first source region;
Forming a second source region (4b) containing a second dopant having a larger mass than the dopant. 4. A method for manufacturing a silicon carbide semiconductor device, comprising: 8. The semiconductor device according to claim 7, wherein the second source region is formed so as to overlap the first source region.
3. The method for manufacturing a silicon carbide semiconductor device according to item 1. 9. The method according to claim 9, wherein nitrogen is used as the first dopant and phosphorus is used as the second dopant, and at a contact portion between the source electrode and the source region, an alloy layer made of the source electrode and silicon carbide has at least the first source. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the semiconductor device is brought into contact with the region. 10. The method of manufacturing a silicon carbide semiconductor device according to claim 9, wherein nickel is used for said source electrode. 11. A semiconductor substrate (1) having a main surface and a back surface opposite to the main surface, the semiconductor substrate being of a first conductivity type made of silicon carbide, and the semiconductor formed on the main surface of the semiconductor substrate, A first conductivity type semiconductor layer (2) made of silicon carbide having higher resistance than the substrate; and a second conductivity type base region (3) formed in a predetermined region of a surface layer portion of the semiconductor layer and having a predetermined depth. A source region of a first conductivity type formed in a predetermined region of a surface portion of the base region and shallower than a depth of the base region;
A first conductivity type surface channel layer (5) made of silicon carbide formed so as to connect a surface layer portion of the base region and the semiconductor layer; and a gate insulation formed on a surface of the surface channel layer. A film (7), a gate electrode (8) formed on the gate insulating film, a source electrode (10) formed in contact with the base region and the source region, and formed on the semiconductor substrate. The source region includes a first source region (4a) containing a first dopant at a position deeper by a predetermined depth from an upper surface in contact with the source electrode, and A second source region which is in contact with the first source electrode at a position shallower than the first source region and in contact with the source electrode, the second source region including a second dopant having a larger mass than the first dopant; 4
A silicon carbide semiconductor device, comprising: b). 12. A semiconductor substrate (1) of a first conductivity type having a main surface and a back surface opposite to the main surface and made of silicon carbide; and a semiconductor formed on the main surface of the semiconductor substrate, A first conductivity type semiconductor layer (2) made of silicon carbide having higher resistance than the substrate; and a second conductivity type base region (3) formed in a predetermined region of a surface layer portion of the semiconductor layer and having a predetermined depth. A source region of a first conductivity type formed in a predetermined region of a surface portion of the base region and shallower than a depth of the base region;
A first conductivity type surface channel layer (5) made of silicon carbide formed so as to connect a surface layer portion of the base region and the semiconductor layer; and a gate insulation formed on a surface of the surface channel layer. A film (7), a gate electrode (8) formed on the gate insulating film, a source electrode (10) formed in contact with the base region and the source region, and formed on the semiconductor substrate. The source region has a first source region (4c) including a first dopant from an upper surface in contact with the source electrode to a position at a predetermined depth, and at least the A second source region (4b) containing a second dopant heavier than the first dopant so as to overlap on an upper surface where the first source region and the source electrode are in contact with each other; Silicon carbide semiconductor device according to symptoms. 13. The silicon carbide semiconductor device according to claim 11, wherein said first dopant is nitrogen, and said second dopant is phosphorus.