JP3893734B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to an insulated gate field effect transistor, particularly a vertical power MOSFET for high power.
[0002]
[Prior art]
In recent years, power devices having low on-resistance and capable of operating at high temperatures have been eagerly desired as inverters for hybrid cars (HEV) and electric vehicles (EV), and silicon carbide (SiC) was used as the promising power device. Things are being researched and developed.
[0003]
When manufacturing a power device using silicon carbide, it is difficult to form an impurity layer by thermal diffusion because the impurity diffusion coefficient in silicon carbide is small. Therefore, in many cases, a technique for doping impurities into silicon carbide by an ion implantation method to form an impurity layer has become common.
[0004]
[Problems to be solved by the invention]
However, the activation rate of ion species implanted into silicon carbide is extremely low (for example, the activation rate is 10% or less in the case of nitrogen and 5% or less in the case of boron), and is formed by ion implantation. There is a problem that the resistivity of the impurity layer is increased. In order to improve the activation rate, it has been reported that a high temperature ion implantation method at 1000 ° C. or higher and a high temperature heat treatment at 1500 ° C. or higher are effective, but the activation rate does not fall within the above range.
[0005]
In the case of silicon carbide, since the diffusion coefficient of ion species is about two orders of magnitude smaller than that of silicon, it is difficult to manufacture a device by a thermal diffusion process. For example, 500 keV is required to form an impurity layer having a depth of about 1 μm. There is a problem in that high energy ion implantation as described above is required, and thus a device capable of performing high energy ion implantation is required.
[0006]
The present invention has been made in view of the above points, and provides a method for manufacturing a semiconductor device capable of increasing a diffusion coefficient and increasing an activation rate when forming an impurity layer in a silicon carbide semiconductor by ion implantation. With the goal.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the following technical means are adopted.
In the first aspect of the present invention, a step of performing low concentration ion implantation with an impurity concentration lower than a desired impurity concentration, and a heat treatment for activating ion species implanted by the low concentration ion implantation at a heat treatment temperature And an impurity layer having a desired concentration is formed by repeatedly performing a low concentration ion implantation step and a heat treatment step.
[0008]
As described above, when the heat treatment is performed after the low-concentration ion implantation is performed, when the implanted ion species is diffused as compared with the case where the impurity layer is formed by performing the high-concentration ion implantation at a time. The diffusion coefficient can be increased, and the activation rate of ionic species can be increased.
In the invention according to claim 2, the step of forming the base region (3a, 3b) includes a step of performing low concentration ion implantation in the surface layer portion of the semiconductor layer so that the impurity concentration is lower than a desired impurity concentration. A heat treatment step of activating ion species implanted by low-concentration ion implantation at a heat treatment temperature, and an impurity layer having a desired concentration is formed by repeatedly performing the low-concentration ion implantation step and the heat treatment step. It is characterized by that.
[0009]
Since the diffusion coefficient and the activation rate can be increased by the low concentration ion implantation and heat treatment, the low energy ion implantation can be performed by performing the step of forming the base region having a deep junction depth by the low concentration ion implantation and heat treatment. Can increase the junction depth.
Specifically, as shown in claim 3, the heat treatment step includes a step of raising the heat treatment temperature to a predetermined temperature after the low-concentration ion implantation step, a step of holding the predetermined temperature for a predetermined time, The temperature can be lowered to a temperature at which the concentration ion implantation step is performed.
[0010]
The invention according to claim 4 is characterized in that it includes a step of performing low-concentration ion implantation with an impurity concentration lower than a desired impurity concentration while activating the ion species implanted at the heat treatment temperature. .
As described above, the same effect as in the first aspect can be obtained even if the low concentration ion implantation is performed at the heat treatment temperature and the heat treatment is performed as it is every time the low concentration ion implantation is performed.
[0011]
According to a fifth aspect of the present invention, in the step of forming the base region (3a, 3b), a desired impurity concentration is applied to the surface layer portion of the semiconductor layer while activating the ion species implanted at the heat treatment temperature. In particular, it is preferable to perform low-concentration ion implantation with a low impurity concentration because the junction depth can be increased by low-energy ion implantation.
[0012]
Specifically, in the low-concentration ion implantation, as shown in claim 6, the dose can be set to 1 × 10 ¹⁴ cm ⁻² or less.
Further, the heat treatment temperature in the heat treatment step is specifically set to 1000 ° C. or more as shown in claim 7.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below.
A cross-sectional view of a normally-off type n-channel type planar MOSFET manufactured by applying an embodiment of the present invention is shown in FIG. This device is suitable when applied to a rectifier for an inverter or an alternator for a vehicle. Hereinafter, the structure of the planar MOSFET will be described with reference to FIG.
[0014]
N ⁺ type silicon carbide semiconductor substrate 1 has a top surface as main surface 1a and a bottom surface opposite to the main surface as back surface 1b. On main surface 1a of n ⁺ -type silicon carbide semiconductor substrate (hereinafter referred to as n ⁺ -type semiconductor substrate) 1, an n ⁻ -type silicon carbide epitaxial layer (hereinafter referred to as n ⁻ -type epitaxial layer) having a dopant concentration lower than that of substrate 1 is provided. 2) are stacked.
[0015]
In the present embodiment, the upper surfaces of the n ⁺ type semiconductor substrate 1 and the n ⁻ type epi layer 2 are (0001) Si planes. However, the upper surfaces of the n ⁺ type semiconductor substrate 1 and the n ⁻ type epi layer 2 may be the (112-0) a plane. That is, when the (0001) Si plane is used, a low surface state density is obtained, and when the (112-0) a plane is used, a crystal having a low surface state density and completely free of screw dislocations is obtained.
[0016]
A p ⁻ type base region 3 a and a p ⁻ type base region 3 b having a predetermined depth are formed in a predetermined region in the surface layer portion of the n ⁻ type epi layer 2 so as to be separated from each other. Further, the n ⁺ type source region 4a shallower than the base region 3a is formed in a predetermined region in the surface layer portion of the p ⁻ type base region 3a, and the base region is formed in a predetermined region in the surface layer portion of the p ⁻ type base region 3b. N ⁺ type source regions 4b shallower than 3b are formed.
[0017]
Further, n ⁻ type SiC layer 5 is extended on the surface portions of n ⁻ type epi layer 2 and p ⁻ type base regions 3a and 3b between n ⁺ type source region 4a and n ⁺ type source region 4b. Yes. That is, the n-type SiC layer 5 is arranged so as to connect the source regions 4a and 4b and the n ⁻ -type epi layer 2 at the surface portions of the p ⁻ -type base regions 3a and 3b. The n-type SiC layer 5 is composed of an n ⁻ type layer 5a and an n ⁺ type layer 5b. The n ⁻ -type layer 5a functions as a channel formation layer on the device surface during device operation. Further, since the portion that does not function as the channel formation layer is the high-concentration n ⁺ -type layer 5b, the resistance value in this portion can be lowered, and the on-resistance is reduced. Hereinafter, the n-type SiC layer 5 is referred to as a surface channel layer.
[0018]
The dopant concentration of the surface channel layer 5 is a low concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and the n ⁻ type epi layer 2 and the p ⁻ type base regions 3a and 3b. It is below the dopant concentration. Thereby, low on-resistance is achieved.
A gate oxide film (gate insulating film) 7 is provided on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ -type source regions 4a and 4b.
[0019]
Further, a polysilicon gate electrode 8 is formed on the gate insulating film 7. The polysilicon gate electrode 8 is covered with an insulating film 9 made of an LTO (Low Temperature Oxide) film. A source electrode 10 electrically connected to the p ⁻ type base regions 3a and 3b and the n ⁺ type source regions 4a and 4b is formed thereon, and the source electrode 10 is formed of the n ⁺ type source regions 4a, 4b and p ^−. It is in contact with the mold base regions 3a and 3b. A drain electrode layer 11 is formed on the back surface 1 b of the n ⁺ type semiconductor substrate 1.
[0020]
In the base regions 3a and 3b, deep base layers 30a and 30b having a partially increased thickness are formed. The deep base layers 30a and 30b are formed in portions that do not overlap the n ⁺ type source region, and the portions where the deep base layers 30a and 30b are formed in the p ⁻ type base regions 3a and 3b are thickened. However, the impurity concentration is higher than that of the thin portion where the deep base layer 30a is not formed. Such deep base layers 30a and 30b reduce the thickness of the n ⁻ type epi layer 2 below the deep base layers 30a and 30b (the distance between the n ⁺ type semiconductor substrate 1 and the deep base layers 30a and 30b is short). It is possible to increase the electric field strength and facilitate avalanche breakdown (hereinafter abbreviated as breakdown). Since the deep base layers 30a and 30b are formed so as not to overlap the n ⁺ type source regions 4a and 4b, it is possible to make the parasitic NPN transistor difficult to operate.
[0021]
Next, the manufacturing process of the vertical power MOSFET shown in FIG. 1 will be described with reference to FIGS.
[Step shown in FIG. 2 (a)]
First, an n-type 4H or 6H or 3C—SiC substrate, that is, an n ⁺ -type semiconductor substrate 1 is prepared. Here, the n ⁺ type semiconductor substrate 1 has a thickness of 400 μm, and the main surface 1a is a (0001) Si plane or a (112-0) a plane. An n ⁻ type epi layer 2 having a thickness of 5 μm is epitaxially grown on the main surface 1 a of the substrate 1. In this example, the n ⁻ -type epi layer 2 has the same crystal as the underlying substrate 1 and becomes an n-type 4H or 6H or 3C—SiC layer.
[0022]
[Step shown in FIG. 2 (b)]
An LTO film 20 is disposed in a predetermined region on the n ⁻ -type epi layer 2 and boron (or aluminum) is ion-implanted using the LTO film 20 as a mask to form p ⁻ -type base regions 3a and 3b.
Specifically, first, after setting the temperature to 700 ° C. and the acceleration voltage to 100 keV, the dose is set to 1 × 10 ¹⁴ cm ⁻² and boron is ion-implanted. After this ion implantation, the substrate temperature is raised to 1300 ° C. and heat treatment is performed for 30 minutes. Then, the substrate temperature is lowered to 700 ° C.
[0023]
Subsequently, as described above, after ion implantation is performed under the above conditions, the substrate temperature is raised to 1300 ° C. or higher, heat treatment is performed for 30 minutes, and then the substrate temperature is lowered to 700 ° C.
Such ion implantation and heat treatment are repeated until the p ⁻ type base regions 3a and 3b have a desired dose. For example, doping can be performed at a concentration of 1 × 10 ¹⁹ cm ⁻³ by controlling the diffusion length to be 1 × 10 ¹⁵ cm ⁻² by 10 repetitions and 1 μm. Further, by repeating the ion implantation method after changing the acceleration voltage to 50 keV, 100 keV, 200 keV, and 400 keV, an impurity layer having an accurate concentration can be formed at a more accurate position.
[0024]
Thereby, p ⁻ type base regions 3a and 3b having a desired impurity concentration are formed.
Here, a case where heat treatment is performed after low-concentration ion implantation is described.
It was found that when heat treatment was performed with low concentration ion implantation, the diffusion coefficient in thermal diffusion was higher and the activation rate was higher than when heat treatment was performed with high concentration ion implantation. .
[0025]
The specific reason why such a phenomenon occurs has not been elucidated. However, according to the study by the present inventors, for example, as one of the reasons that the diffusion coefficient becomes high, when high-concentration ion implantation is performed, many It is considered that the thermal diffusion coefficient becomes small because crystal defects are formed.
For example, when the base regions 3a and 3b are formed by low-concentration ion implantation with a dose amount of 1 × 10 ¹⁴ cm ⁻² , the crystal is larger than when the dose amount is 1 × 10 ¹⁵ cm ^−2. Defects can be reduced by several orders of magnitude.
[0026]
Another reason is that when high-concentration ion implantation is performed, the density of the implanted ion species is too high, and the nearby ion species cannot be diffused during thermal diffusion. It is done.
This will be described with reference to the comparative diagrams shown in FIGS. FIG. 5 (a) shows a case in which a low concentration (dose amount: 1 × 10 ¹⁴ cm ⁻² ) ion implantation is performed on the silicon carbide semiconductor substrate 50, and a heat treatment at 1300 ° C. for 30 minutes is further performed four times. (B) shows a case where ion implantation at a high concentration (dose amount: 1 × 10 ¹⁵ cm ⁻² ) is performed on the silicon carbide semiconductor substrate 50 and then heat treatment is performed at 1700 ° C. for 1 hour. 5A and 5B, the characteristic diagrams shown on the right side of the drawing show the dopant concentration with respect to the depth of the silicon carbide semiconductor substrate 50. The numbers shown in FIG. It shows whether it is ion implantation.
[0027]
As can be seen from these figures, when the heat treatment is performed after the low-concentration ion implantation, the implanted ion species are sufficiently thermally diffused to spread the impurity layer 51, and the high-concentration ion In the case where the heat treatment is performed after the implantation, the impurity layer 51 does not spread almost because of thermal diffusion.
For example, when low-energy ion implantation of about 50 keV is performed, a heat treatment is performed at 1300 ° C. for about 30 minutes, and impurities are thermally diffused to a depth of about 1 μm. In this manner, when a heat treatment layer is performed after ion implantation at a low concentration, it is possible to dope impurities into a wide area.
[0028]
Further, when the ion species concentration at the initial stage of ion implantation is low, impurity levels formed by lattice-substituted ion species are formed shallow. For example, in the case of boron, it is formed at 300 meV. For this reason, it can be said that the activation rate is greatly improved when low concentration ion implantation is performed.
Thus, by repeating the step of performing low concentration ion implantation and the step of performing heat treatment, the diffusion coefficient and the activation rate can be increased as compared with the case where the base regions 3a and 3b are formed by one high concentration ion implantation. Can be high.
[0029]
According to such low concentration ion implantation, the base regions 3a and 3b can be formed by low energy ion implantation. That is, in order to form the base regions 3a and 3b having a deep junction depth by a single ion implantation, an ion implantation apparatus capable of performing high-energy ion implantation is required, which has a cost problem. Can be eliminated.
[0030]
[Step shown in FIG. 2 (c)]
After removing the LTO film 20, nitrogen is ion-implanted from the upper surface of the substrate 1, and the surface channel layer 5 is formed on the surface layer portion of the n ⁻ -type epi layer 2 and the surface portions (surface layer portions) of the p ⁻ -type base regions 3a and 3b. Form. The ion implantation conditions at this time are a temperature of 700 ° C. and a dose of 1 × 10 ¹⁵ cm ⁻² . As a result, the surface channel layer 5 is compensated in the surface portions of the p ⁻ type base regions 3 a and 3 b to be formed as an n ⁻ type layer 5 a having a low n type impurity concentration, and in the surface portion of the n ⁻ type epi layer 2. The n ⁺ -type layer 5b having a high n-type impurity concentration is formed. Therefore, the on-resistance is reduced by the n ⁺ -type layer 5b having a high impurity concentration.
[0031]
Further, in order to make the vertical power MOSFET normally-off type, the thickness (film thickness) of the surface channel layer 5 is changed from the p ⁻ type base regions 3a and 3b when no voltage is applied to the gate electrode 8 to the surface channel layer. 5 is smaller than the sum of the extension amount of the depletion layer extending to 5 and the extension amount of the depletion layer extending from the gate insulating film 7 to the surface channel layer 5.
[0032]
Specifically, the extension amount of the depletion layer extending from the p ⁻ type base regions 3a and 3b to the surface channel layer 5 is determined by the built-in voltage of the PN junction between the surface channel layer 5 and the p ⁻ type base regions 3a and 3b. The extension amount of the depletion layer extending from the gate insulating film 7 to the surface channel layer 5 is determined by the charge of the gate insulating film 7 and the work function difference between the gate electrode 8 (metal) and the surface channel layer 5 (semiconductor). Based on these, the film thickness of the surface channel layer 5 is determined.
[0033]
Such a normally-off type vertical power MOSFET can prevent current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like. Safety can be ensured.
Further, as shown in FIG. 1, the p ⁻ type base regions 3a and 3b are in contact with the source electrode 10 and are in a grounded state. Therefore, the surface channel layer 5 can be pinched off using the built-in voltage of the PN junction between the surface channel layer 5 and the p ⁻ -type base regions 3a and 3b. For example, when the p ⁻ type base regions 3a and 3b are not grounded and are in a floating state, it is impossible to extend a depletion layer from the p ⁻ type base regions 3a and 3b using a built-in voltage. It can be said that bringing the p ⁻ type base regions 3 a and 3 b into contact with the source electrode 10 is an effective structure for pinching off the surface channel layer 5.
[0034]
In this embodiment, the p ⁻ -type base regions 3a and 3b are formed with a low impurity concentration. However, the built-in voltage can be used more greatly by increasing the impurity concentration.
In the present embodiment, the vertical power MOSFET is manufactured using silicon carbide. However, if an attempt is made to manufacture the vertical power MOSFET using silicon, impurity layers such as p ⁻ type base regions 3 a and 3 b and the surface channel layer 5 are formed. Since it is difficult to control the diffusion amount of the thermal diffusion at the time, it is difficult to manufacture a normally-off type MOSFET similar to the above configuration. For this reason, by using SiC as in the present embodiment, a vertical power MOSFET can be manufactured with higher accuracy than when silicon is used.
[0035]
In order to obtain a normally-off type vertical power MOSFET, it is necessary to set the thickness of the surface channel layer 5 so as to satisfy the above conditions. However, when silicon is used, the built-in voltage is low. In view of the fact that the thickness of the layer 5 must be reduced or the impurity concentration must be reduced, and it is difficult to control the diffusion amount of impurity ions, it can be said that the production is very difficult. However, when SiC is used, the built-in voltage is about three times as high as that of silicon, and the surface channel layer 5 can be formed with a thicker thickness or higher impurity concentration. Therefore, a normally-off type storage MOSFET is manufactured. Can be said to be easy.
[0036]
[Step shown in FIG. 3 (a)]
An LTO film 21 is arranged in a predetermined region on the surface channel layer 5, and N ⁺ ions are implanted using the LTO film 21 as a mask to form n ⁺ type source regions 4a and 4b. The ion implantation conditions at this time are a temperature of 700 ° C. and a dose of 1 × 10 ¹⁵ cm ⁻² .
[Step shown in FIG. 3B]
Then, after removing the LTO film 21, the LTO film 22 is disposed in a predetermined region on the surface channel layer 5 using a photoresist method, and the surface on the p ⁻ type base regions 3a and 3b is formed by RIE using this as a mask. The channel layer 5 is partially etched away.
[0037]
[Step shown in FIG. 3 (c)]
Further, boron is ion-implanted using the LTO film 22 as a mask to form deep base layers 30a and 30b.
At this time, as in the case of forming the p ⁻ type base region described above, first, boron is ionized under the conditions of a temperature of 700 ° C. and an acceleration voltage of 400 keV and a dose of 1 × 10 ¹⁴ cm ^−2. After the implantation, an ion implantation process is repeated in which the substrate temperature is raised to 1300 ° C., heat treatment is performed for 30 minutes, and the substrate temperature is further lowered to 700 ° C., so that the deep base layer 30a, 30b is formed.
[0038]
At this time, by setting the acceleration voltage to 400 keV, the implantation depth becomes about 0.5 to 1 μm. By diffusing the ion species implanted by the repetitive ion implantation method, the deep base layers 30a, 30b and n ⁻ The bonding position with the type epi layer 2 can be 1.5 to 2 μm.
Thereby, a part of base region 3a, 3b becomes thick. The deep base layers 30a and 30b are formed in portions that do not overlap the n ⁺ -type source regions 4a and 4b, and the deep base layers 30a and 30b are formed thick in the p ⁻ -type base regions 3a and 3b. The formed portion has a higher impurity concentration than the thin portion where the deep base layers 30a and 30b are not formed.
[0039]
In this way, by forming the deep base layers 30a and 30b having a deep junction depth by repeating low-concentration ion implantation and heat treatment, the same effects as those obtained when the base regions 3a and 3b are formed can be obtained. .
[Step shown in FIG. 4 (a)]
After removing the LTO film 22, a gate oxide film (gate insulating film) 7 is formed on the substrate by wet oxidation. At this time, the ambient temperature is set to 1080 ° C.
[0040]
Thereafter, a polysilicon gate electrode 8 is deposited on the gate oxide film 7 by LPCVD. The film forming temperature at this time is 600 ° C.
[Step shown in FIG. 4B]
Subsequently, after unnecessary portions of the gate insulating film 7 are removed, an insulating film 9 made of LTO is formed to cover the gate insulating film 7. More specifically, the film formation temperature is 425 ° C., and 1000 ° C. annealing is performed after the film formation.
[0041]
[Step shown in FIG. 4 (c)]
Then, the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. Further, annealing at 1000 ° C. is performed after film formation.
In this way, the vertical power MOSFET shown in FIG. 1 is completed.
Next, the operation (operation) of this vertical power MOSFET will be described.
[0042]
This MOSFET operates in a normally-off type accumulation mode, and when no voltage is applied to the polysilicon gate electrode, carriers in the surface channel layer 5 are p ⁻ type base regions 3a and 3b, surface channel layer 5 and Are depleted by the potential generated by the difference in electrostatic potential between the two and the work function difference between the surface channel layer 5 and the polysilicon gate electrode 8. By applying a voltage to the polysilicon gate electrode 8, the potential difference caused by the sum of the work function difference between the surface channel layer 5 and the polysilicon gate electrode 8 and the externally applied voltage is changed. This makes it possible to control the channel state.
[0043]
That is, the work function of the polysilicon gate electrode 8 is the first work function, the work function of the p ⁻ -type base regions 3a and 3b is the second work function, and the work function of the surface channel layer 5 is the third work function. Then, using the difference between the first to third work functions, the impurity concentrations of the first to third work functions and the surface channel layer 5 are used to deplete the n-type carriers of the surface channel layer 5. And the film thickness can be set.
[0044]
In the off state, the depletion region is formed in the surface channel layer 5 by the electric field created by the p ⁻ type base regions 3 a and 3 b and the polysilicon gate electrode 8. When a positive bias is supplied to the polysilicon gate electrode 8 from this state, the n ⁻ type drift from the n ⁺ type source regions 4a and 4b at the interface between the gate insulating film (SiO ₂ ) 7 and the surface channel layer 5 occurs. A channel region extending in the direction of region 2 is formed and switched to the on state. At this time, electrons flow from the n ⁺ type source regions 4 a and 4 b through the surface channel layer 5 to the n ⁻ type epi layer 2. When the n ⁻ type epi layer 2 (drift region) is reached, electrons flow vertically to the n ⁺ type semiconductor substrate 1 (n ⁺ drain).
[0045]
Thus, by applying a positive voltage to the gate electrode 8, an accumulation channel is induced in the surface channel layer 5, and carriers flow between the source electrode 10 and the drain electrode 11.
(Other embodiments)
In the above embodiment, the base regions 3a and 3b and the deep base layers 30a and 30b having a deep junction depth are formed by performing low-concentration ion implantation and heat treatment processes. However, when an impurity layer is formed by ion implantation, For example, when the surface channel layer 5 and the source regions 4a and 4b are formed, they can be formed by such a low concentration ion implantation and heat treatment process.
[0046]
The low concentration ion implantation and heat treatment step may be performed by intermittently performing ion implantation while maintaining the substrate temperature at 1300 ° C.
Furthermore, even if the ion implantation speed (current amount) is set to a low speed and the heat treatment is performed simultaneously with the ion implantation, the same effect as described above can be obtained.
For example, when 1 × 10 ¹⁴ cm ⁻² is performed for 5 minutes at a voltage of 100 keV, an impurity layer having a desired concentration can be formed in a process of 35 minutes including a subsequent annealing time of 30 minutes. However, in this case, the same effect can be obtained by reducing the dose amount to about 1/7 and performing ion implantation for 35 minutes under the condition of 3 × 10 ¹³ cm ^−2. . As described above, when the dose amount is reduced to reduce the ion implantation amount, crystal defects can be further reduced. Further, the temperature raising and lowering steps can be omitted, and an impurity layer having a desired concentration can be effectively formed in a short time.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a vertical power MOSFET according to an embodiment of the present invention.
2 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 1. FIG.
3 is a diagram showing manufacturing steps of the vertical power MOSFET subsequent to FIG. 2. FIG.
4 is a diagram showing manufacturing steps of the vertical power MOSFET subsequent to FIG. 3. FIG.
5A and 5B are diagrams showing a state of thermal diffusion in ion implantation, where FIG. 5A is a diagram showing a case of low-concentration ion implantation, and FIG. 5B is a diagram showing a case of high-concentration ion implantation.
[Explanation of symbols]
1 ... n ⁺ -type semiconductor substrate, 2 ... n ^- -type epitaxial layer, 3a, 3b ... p ^- type base region,
4a, 4b... N ⁺ type source region, 5... Surface channel layer (n ⁻ type SiC layer),
5a ... n ^- type layer part, 5b ... n ⁺ type layer part, 7 ... gate insulating film,
8 ... Gate electrode, 9 ... Insulating film, 10 ... Source electrode, 11 ... Drain electrode layer.

Claims (7)

In a method for manufacturing a silicon carbide semiconductor device in which an impurity layer having a desired impurity concentration is formed by ion implantation into a semiconductor layer made of silicon carbide.
Performing a low concentration ion implantation that results in an impurity concentration lower than the desired impurity concentration;
A heat treatment step of activating the ion species implanted by the low-concentration ion implantation at a heat treatment temperature,
A method of manufacturing a silicon carbide semiconductor device, wherein the impurity layer having the desired concentration is formed by repeatedly performing the low concentration ion implantation step and the heat treatment step. Forming a first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on the main surface of the first conductivity type semiconductor substrate (1);
Forming a second conductivity type base region (3a, 3b) having a predetermined depth as an impurity layer having a desired impurity concentration in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a surface channel layer (5) serving as the semiconductor layer and an upper channel formation region before Symbol base region,
Forming a first conductivity type source region (4a, 4b) in a predetermined region of a surface layer portion of the base region, which is shallower than the depth of the base region and connected to the semiconductor layer via the surface channel layer; When,
Forming a gate electrode (8) via a gate insulating film (7) on at least the surface channel layer using the surface channel layer as a channel region;
Forming a source electrode (10) in contact with the source region and the base region;
Forming a drain electrode (11) formed on the opposite side of the main surface of the semiconductor substrate, and a method for manufacturing a silicon carbide semiconductor device comprising:
The step of forming the base region includes:
A step of performing low-concentration ion implantation in the surface layer portion of the semiconductor layer to achieve an impurity concentration lower than the desired impurity concentration;
A heat treatment step of activating the ion species implanted by the low-concentration ion implantation at a heat treatment temperature,
A method of manufacturing a silicon carbide semiconductor device, wherein the impurity layer having the desired concentration is formed by repeatedly performing the low concentration ion implantation step and the heat treatment step. The heat treatment step includes
After finishing the low-concentration ion implantation step, raising the heat treatment temperature to a predetermined temperature;
Holding the predetermined temperature for a predetermined time;
The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of lowering the temperature to a temperature at which the low concentration ion implantation step is performed. In a method for manufacturing a silicon carbide semiconductor device in which an impurity layer having a desired impurity concentration is formed by ion implantation into a semiconductor layer made of silicon carbide.
A method for manufacturing a silicon carbide semiconductor device, comprising activating ion species implanted at a heat treatment temperature and performing low-concentration ion implantation with an impurity concentration lower than the desired impurity concentration. Forming a first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on the main surface of the first conductivity type semiconductor substrate (1);
Forming a second conductivity type base region (3a, 3b) having a predetermined depth as an impurity layer having a desired impurity concentration in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a surface channel layer (5) serving as the semiconductor layer and an upper channel formation region before Symbol base region,
Forming a first conductivity type source region (4a, 4b) in a predetermined region of a surface layer portion of the base region, which is shallower than the depth of the base region and connected to the semiconductor layer via the surface channel layer; When,
Forming a gate electrode (8) via a gate insulating film (7) on at least the surface channel layer using the surface channel layer as a channel region;
Forming a source electrode (10) in contact with the source region and the base region;
Forming a drain electrode (11) formed on the opposite side of the main surface of the semiconductor substrate, and a method for manufacturing a silicon carbide semiconductor device comprising:
The step of forming the base region performs low-concentration ion implantation with an impurity concentration lower than the desired impurity concentration in the surface layer portion of the semiconductor layer while activating ion species implanted at a heat treatment temperature. The manufacturing method of the silicon carbide semiconductor device characterized by having a process. 6. The method of manufacturing a semiconductor device according to claim 1, wherein in the low-concentration ion implantation step, a dose is set to 1 × 10 ¹⁴ cm ⁻² or less. The method for manufacturing a semiconductor device according to claim 1, wherein in the heat treatment step, the heat treatment temperature is set to 1000 ° C. or higher.

Images