CN111341651A - Method for manufacturing transistor epitaxial layer - Google Patents
Method for manufacturing transistor epitaxial layer Download PDFInfo
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- CN111341651A CN111341651A CN202010165542.XA CN202010165542A CN111341651A CN 111341651 A CN111341651 A CN 111341651A CN 202010165542 A CN202010165542 A CN 202010165542A CN 111341651 A CN111341651 A CN 111341651A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000005468 ion implantation Methods 0.000 claims abstract description 46
- 150000002500 ions Chemical class 0.000 claims abstract description 34
- 239000013078 crystal Substances 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 230000008569 process Effects 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- -1 phosphorus ions Chemical class 0.000 claims description 6
- 229910001439 antimony ion Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000004321 preservation Methods 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000008859 change Effects 0.000 abstract description 2
- 238000001764 infiltration Methods 0.000 abstract description 2
- 230000008595 infiltration Effects 0.000 abstract description 2
- 239000012466 permeate Substances 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000010420 art technique Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
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Abstract
The invention discloses a method for manufacturing a transistor epitaxial layer, which comprises the following steps: carrying out one or more times of ion implantation treatment on the crystal substrate to enable the ion doping depth to reach a first preset depth; and performing high-temperature diffusion treatment on the crystal substrate after the ion implantation treatment to ensure that the ion doping depth reaches a second preset depth and is stable, thereby obtaining the transistor epitaxial layer with the ion doping depth reaching the second preset depth. The invention adopts a physical infiltration mode of multiple times and various forms, and can construct a doping layer with large depth at low cost and high quality. The method adopts a high-energy ion implantation technology, can solve the problem of sudden change of ions entering the substrate from the outside, and is matched with low-cost high-temperature diffusion and permeation to enable the ions to freely diffuse and permeate to form a deeper doped layer.
Description
Technical Field
The invention relates to an epitaxial layer manufacturing technology, in particular to a transistor epitaxial layer manufacturing method.
Background
Epitaxy is one of semiconductor processes, the lowest layer of a silicon wafer is P-type substrate silicon, then a layer of monocrystalline silicon grows on the substrate, the layer of monocrystalline silicon is called an epitaxial layer, and then a main and arbitrary base region, an emitter region and the like are formed on the epitaxial layer.
There are various methods for growing epitaxial layers, which can be classified into a chemical reaction growth method and a physical reaction growth method according to a reaction mechanism.
In the existing epitaxial processing, most of the adopted surface growth methods are used for completing the epitaxy, such as chemical reaction growth on the surface of a substrate, deposition, sputtering and the like. Most commonly substrate surface deposition chemical reaction growth.
In prior art techniques for growing epitaxial layers inward, it is common to use ion implantation followed by an annealing process to restore the complete crystal lattice. This process typically employs multiple anneals below 400 c to achieve the problem of restoring intact lattice integrity.
However, the surface epitaxy treatment process and the in-growth epitaxy treatment process have the prominent problems: the existing process is complex and high in cost, and an epitaxial layer with large doping depth and good uniformity cannot be obtained.
Disclosure of Invention
One of the main objects of the present invention is to provide an epitaxial substrate which can be manufactured at low cost with improved production quality.
To achieve the above objects, the present invention provides a method for manufacturing an epitaxial layer of a transistor,
the manufacturing method of the transistor epitaxial layer comprises at least the following processes:
carrying out one or more times of ion implantation treatment on the crystal substrate to enable the ion doping depth to reach a first preset depth;
and performing high-temperature diffusion treatment on the crystal substrate after the ion implantation treatment to ensure that the ion doping depth reaches a second preset depth and is stable, thereby obtaining the transistor epitaxial layer with the ion doping depth reaching the second preset depth.
The manufacturing method of the transistor epitaxial layer comprises the following specific steps of: and carrying out gradient temperature rise treatment on the crystal substrate subjected to the ion implantation treatment to a preset temperature, carrying out heat preservation treatment at the preset temperature for a preset time, and then carrying out gradient temperature reduction treatment at the first preset temperature.
The manufacturing method of the transistor epitaxial layer comprises the following specific steps of: and (3) placing the crystal substrate subjected to the ion implantation treatment, keeping the temperature for a preset time at a preset temperature, and then taking out the crystal substrate for natural cooling.
According to the manufacturing method of the transistor epitaxial layer, the preset temperature is T, and T is more than or equal to 1000 ℃ and less than 1414 ℃.
According to the manufacturing method of the transistor epitaxial layer, the preset temperature is T, and T is more than or equal to 1100 ℃ and less than or equal to 1200 ℃.
According to the manufacturing method of the transistor epitaxial layer, the ion implantation treatment is carried out by adopting a high-energy ion implantation machine.
According to the manufacturing method of the transistor epitaxial layer, ion implantation is carried out by adopting an ion implantation machine with million-level electron volts.
According to the manufacturing method of the transistor epitaxial layer, the crystal substrate is a silicon substrate, and the ions are at least 1 of phosphorus ions, arsenic ions and antimony ions.
The manufacturing method of the transistor epitaxial layer further comprises the step of adjusting the ion implantation dosage before the ion implantation treatment, wherein the ion implantation dosage is adjusted according to the required resistivity.
According to the manufacturing method of the transistor epitaxial layer, the first preset depth is in direct proportion to the ion implantation treatment times.
Compared with the prior art, the invention provides a different epitaxial manufacturing mode on the basis of a silicon substrate (n-p type substrate). High energy ion doses are implanted into a silicon substrate using a high energy implantation technique with an ion implanter. The high temperature diffusion mode is used in a matching way, implanted ions are further pushed to the deep part of the silicon substrate, and finally an epitaxial substrate is formed, so that the current epitaxial manufacturing method is replaced. In this way, a high-quality, low-cost epitaxial substrate can be produced. The invention can also make epitaxy with different resistivity by adjusting the size of the implantation dosage. The invention can also use multiple times of high-energy ion implantation to adjust the epitaxial thickness. The invention can also adjust the epitaxial thickness by using a mode of multiple high-temperature annealing. The invention can also be used for manufacturing a double-layer epitaxial substrate. The invention can also be used for manufacturing epitaxial substrates suitable for high-voltage and low-voltage power devices.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a flow chart of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
As shown in figure 1 of the drawings, in which,
in order to realize a deeper doping layer, the present embodiment adopts a design concept of multi-level structure doping depth, that is, firstly, an ion implantation process is adopted to obtain an ion doping layer with a first predetermined depth, and then, the ion doping layer with the first predetermined depth is continuously diffused on the basis of the ion doping layer with the first predetermined depth by matching with a high temperature process, so that the dopant is continuously diffused to the deep of the substrate, thereby obtaining an ion doping layer with a second predetermined depth and a higher depth. Thereby improving the quality of the epitaxial layer, and the technical conception has lower cost and simple operation. Based on the above concept, a method for manufacturing a transistor epitaxial layer can be provided, which includes at least the following steps: carrying out one or more times of ion implantation treatment on the crystal substrate to enable the ion doping depth to reach a first preset depth; and then carrying out high-temperature diffusion treatment on the crystal substrate subjected to the ion implantation treatment to ensure that the ion doping depth reaches a second preset depth and is stable, thereby obtaining the transistor epitaxial layer with the ion doping depth reaching the second preset depth. This embodiment utilizes an ion implanter to implant high energy ion doses into a silicon substrate using high energy implantation techniques. The high temperature diffusion mode is used to push the implanted ions to the deep part of the silicon substrate, and finally an epitaxial substrate is formed, so that the current epitaxial manufacturing method is replaced. In this way, a high-quality, low-cost epitaxial substrate can be produced.
Referring to fig. 1, a crystalline substrate with a predetermined thickness is selected, the crystalline substrate is selected as a silicon substrate, a predetermined amount of dopant is loaded in a High Energy ion implanter (High Energy Lon lmplant), the High Energy ion implanter is started to perform ion implantation operation on the silicon substrate (si substrate), a doped layer with a first predetermined depth is formed on the upper surface of the silicon substrate in an inward direction, then the whole is placed in a High temperature process to perform thermal diffusion, so that the doped ions are forced to further diffuse to a second predetermined depth in the depth direction of the silicon substrate, and the formed diffusion region is an EPl layer.
Example 2
As shown in figure 1 of the drawings, in which,
on the basis of the above-described embodiments,
the embodiment may provide a more specific high-temperature treatment process, that is, the high-temperature diffusion treatment specifically includes: and carrying out gradient temperature rise treatment on the crystal substrate subjected to the ion implantation treatment to a preset temperature, carrying out heat preservation treatment at the preset temperature for a preset time, and then carrying out gradient temperature reduction treatment at the first preset temperature. The embodiment adopts gradual temperature rise treatment, so that ion diffusion can be gradually transited from high-concentration slow expansion to low-concentration rapid diffusion, thereby leading the diffusion to be uniform and obtaining a uniform epitaxial layer.
Example 3
As shown in figure 1 of the drawings, in which,
on the basis of the above-described embodiments,
the embodiment may provide another more specific high-temperature treatment process, that is, the high-temperature diffusion treatment specifically includes: and (3) placing the crystal substrate subjected to the ion implantation treatment, keeping the temperature for a preset time at a preset temperature, and then taking out the crystal substrate for natural cooling.
In addition, in the above-described embodiments 2 and 3, it is preferable that the predetermined temperature is T, and 1000 degrees celsius ≦ T < 1414 degrees celsius. The optimal parameters can be set as follows: the preset temperature is T, and T is more than or equal to 1100 ℃ and less than or equal to 1200 ℃. The 1414 ℃ is the silicon melting temperature.
In addition, in the above embodiment, it is preferable that the ion implantation process is performed by using a high-energy ion implanter.
The ion implantation treatment adopts an ion implantation machine with million-level electron volts to carry out the ion implantation treatment.
The ions are at least 1 of phosphorus ions, arsenic ions and antimony ions.
And before the ion implantation treatment, adjusting the ion implantation dosage, wherein the ion implantation dosage is adjusted according to the required resistivity.
The first predetermined depth is proportional to the number of ion implantation processes.
The invention adopts a physical infiltration mode of multiple times and various forms, and can construct a doping layer with large depth at low cost and high quality. The method adopts a high-energy ion implantation technology, can solve the problem of sudden change of ions entering the substrate from the outside, and is matched with low-cost high-temperature diffusion and permeation to enable the ions to freely diffuse and permeate to form a deeper doped layer.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. The manufacturing method of the transistor epitaxial layer is characterized by comprising the following steps:
carrying out one or more times of ion implantation treatment on the crystal substrate to enable the ion doping depth to reach a first preset depth;
and performing high-temperature diffusion treatment on the crystal substrate after the ion implantation treatment to ensure that the ion doping depth reaches a second preset depth and is stable, thereby obtaining the transistor epitaxial layer with the ion doping depth reaching the second preset depth.
2. The method for manufacturing the epitaxial layer of the transistor according to claim 1, wherein:
the high-temperature diffusion treatment specifically comprises the following steps: and carrying out gradient temperature rise treatment on the crystal substrate subjected to the ion implantation treatment to a preset temperature, carrying out heat preservation treatment at the preset temperature for a preset time, and then carrying out gradient temperature reduction treatment at the first preset temperature.
3. The method for manufacturing the epitaxial layer of the transistor according to claim 1, wherein:
the high-temperature diffusion treatment specifically comprises the following steps: and (3) placing the crystal substrate subjected to the ion implantation treatment, keeping the temperature for a preset time at a preset temperature, and then taking out the crystal substrate for natural cooling.
4. A method for manufacturing an epitaxial layer of a transistor according to claim 2 or 3, wherein:
the preset temperature is T, and T is more than or equal to 1000 ℃ and less than 1414 ℃.
5. A method for manufacturing an epitaxial layer of a transistor according to claim 2 or 3, wherein:
the preset temperature is T, and T is more than or equal to 1100 ℃ and less than or equal to 1200 ℃.
6. The method for manufacturing the epitaxial layer of the transistor according to claim 1, wherein:
and the ion implantation treatment adopts a high-energy ion implantation machine to carry out the ion implantation treatment.
7. The method for manufacturing the epitaxial layer of the transistor according to claim 1, wherein:
the ion implantation treatment adopts an ion implantation machine with million-level electron volts to carry out the ion implantation treatment.
8. The method for manufacturing the epitaxial layer of the transistor according to claim 1, wherein:
the crystal substrate is a silicon substrate, and the ions are at least 1 of phosphorus ions, arsenic ions and antimony ions.
9. The method for manufacturing the epitaxial layer of the transistor according to claim 1, wherein:
and before the ion implantation treatment, adjusting the ion implantation dosage, wherein the ion implantation dosage is adjusted according to the required resistivity.
10. The method for manufacturing the epitaxial layer of the transistor according to claim 1, wherein:
the first predetermined depth is proportional to the number of ion implantation processes.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010165542.XA CN111341651A (en) | 2020-03-11 | 2020-03-11 | Method for manufacturing transistor epitaxial layer |
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| CN202010165542.XA CN111341651A (en) | 2020-03-11 | 2020-03-11 | Method for manufacturing transistor epitaxial layer |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05326680A (en) * | 1992-05-20 | 1993-12-10 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| US5851908A (en) * | 1995-04-10 | 1998-12-22 | Abb Research Ltd. | Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of highly doped amorphous layer as a source for dopant diffusion into SiC |
| JPH11307545A (en) * | 1998-04-23 | 1999-11-05 | Denso Corp | Producing method for silicon carbide semiconductor device |
| CN108538716A (en) * | 2017-03-06 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | Reduce the method and semiconductor structure of autodoping effect |
-
2020
- 2020-03-11 CN CN202010165542.XA patent/CN111341651A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05326680A (en) * | 1992-05-20 | 1993-12-10 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| US5851908A (en) * | 1995-04-10 | 1998-12-22 | Abb Research Ltd. | Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of highly doped amorphous layer as a source for dopant diffusion into SiC |
| JPH11307545A (en) * | 1998-04-23 | 1999-11-05 | Denso Corp | Producing method for silicon carbide semiconductor device |
| CN108538716A (en) * | 2017-03-06 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | Reduce the method and semiconductor structure of autodoping effect |
Non-Patent Citations (1)
| Title |
|---|
| 毕克允, 国防工业出版社 * |
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