JP2808871B2 - Method for manufacturing MOS type semiconductor device - Google Patents
Method for manufacturing MOS type semiconductor deviceInfo
- Publication number
- JP2808871B2 JP2808871B2 JP2246561A JP24656190A JP2808871B2 JP 2808871 B2 JP2808871 B2 JP 2808871B2 JP 2246561 A JP2246561 A JP 2246561A JP 24656190 A JP24656190 A JP 24656190A JP 2808871 B2 JP2808871 B2 JP 2808871B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- region
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000000034 method Methods 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000010410 layer Substances 0.000 claims description 27
- 239000012535 impurity Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 239000002344 surface layer Substances 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims 1
- 108091006146 Channels Proteins 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体基板の表面上にゲート絶縁膜を介し
て設けられたゲートへの電圧印加により、半導体基板の
表面層に設けられた逆導電型の領域の一部にチャネルを
形成してその逆導電型の領域に接触する主電極から基板
本来の領域に流れ込む電流を制御するMOS型半導体素子
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of applying a voltage to a gate provided on a surface of a semiconductor substrate via a gate insulating film to thereby apply a voltage to a gate formed on a surface layer of the semiconductor substrate. The present invention relates to a method of manufacturing a MOS semiconductor device in which a channel is formed in a part of a conductive type region and a current flowing from a main electrode in contact with a region of the opposite conductive type to an original region of a substrate is controlled.
主電極に流れる電流を、主電極を囲んで設けられたゲ
ートへの電圧印加により制御するMOS型半導体素子とし
ては電力用MOSFETあるいは絶縁ゲートバイポーラトラン
ジスタ（IGBT）などがある。このような素子のオン抵抗
を低減させるには、主表面上において主電極を囲むゲー
トの面積の比率をゲートのない部分にくらべて高くする
ことにより、基板本来の領域とチャネルの形成される逆
導電型の領域との間の接合によるＪ−FET効果を減少せ
しめる方法、あるいはゲート下部の半導体基板の表面層
の不純物濃度を高くして抵抗を下げ同時にＪ−FET効果
を減少させる方法がある。第２図はそのような表面層の
不純物濃度を高めたMOSFETを示す。図において、n-シリ
コン基板１の表面層にはｐ型チャネル領域２が間隔を介
して形成され、その中央にp+ウエル領域３、また外周に
近い所に環状のn+ソース領域４が形成されている。そし
て、チャネル領域２のn+ソース領域４とn-層１の間にｎ
チャネルを形成するために、ゲート酸化膜５を介して多
結晶シリコン層６が形成され、ゲートとして働く。多結
晶シリコン層６は平面図（ａ）に示すようにn+ソース領
域４をとり囲んでいる。そして、p+ウエル領域３および
n+ソース領域４に共通にAl−Si合金よりなるソース電極
７が多結晶シリコン層との絶縁のためのPSG膜８に明け
られたコンタクトホール81で接触している。n-基板１の
表面にはドナー不純物が低不純物濃度で拡散され、第２
図（ｂ）の点線より上の表面層にｎ層11が形成されてい
る。As a MOS type semiconductor element which controls a current flowing through a main electrode by applying a voltage to a gate provided surrounding the main electrode, there is a power MOSFET or an insulated gate bipolar transistor (IGBT). In order to reduce the on-resistance of such an element, the ratio of the area of the gate surrounding the main electrode on the main surface is made higher than that of the part without the gate, so that the region where the substrate is originally formed and the channel are formed. There is a method of reducing the J-FET effect due to the junction with the conductive type region, or a method of increasing the impurity concentration of the surface layer of the semiconductor substrate below the gate to lower the resistance and simultaneously reducing the J-FET effect. FIG. 2 shows a MOSFET in which the impurity concentration of such a surface layer is increased. In the figure, a p-type channel region 2 is formed at intervals in a surface layer of an n - silicon substrate 1, ap + well region 3 is formed in the center thereof, and an annular n + source region 4 is formed near an outer periphery. Have been. Then, n is between n + source region 4 of channel region 2 and n − layer 1.
In order to form a channel, a polycrystalline silicon layer 6 is formed via a gate oxide film 5 and functions as a gate. Polycrystalline silicon layer 6 surrounds n + source region 4 as shown in plan view (a). And p + well region 3 and
A source electrode 7 commonly made of an Al-Si alloy is in contact with the n + source region 4 through a contact hole 81 formed in the PSG film 8 for insulation from the polycrystalline silicon layer. On the surface of the n - substrate 1, donor impurities are diffused at a low impurity concentration,
The n-layer 11 is formed on the surface layer above the dotted line in FIG.
また、オフ時のスイッチング速度を速くするためにゲ
ート・ドレイン間のゲート容量を小さくするには、ゲー
ト面積を小さくする方法、ゲート酸化膜の全部あるいは
一部を厚くする方法あるいは半導体基板表面に基板と逆
の導電型にする働きをもつ不純物を拡散させる方法など
がある。第３図はゲート酸化膜の一部を厚くしたMOSFET
を示し、第２図と共通の部分には同一の符号が付されて
いるが、図より明らかなようにゲート酸化膜５の一部51
は厚くされている。平面図の第３図（ａ）ではこの厚い
部分51の境界が点線で示されている。In order to reduce the gate capacitance between the gate and the drain in order to increase the switching speed at the time of off, a method of reducing the gate area, a method of increasing the thickness of all or part of the gate oxide film, or a method of forming the substrate on the surface of the semiconductor substrate. For example, there is a method of diffusing impurities having a function of making the conductivity type opposite to the above. Fig. 3 shows a MOSFET with a part of the gate oxide film thickened.
2 are denoted by the same reference numerals as in FIG. 2, but as is clear from the drawing, a portion 51
Is thicker. In FIG. 3 (a) of a plan view, the boundary of the thick portion 51 is indicated by a dotted line.
オン抵抗を低減させるためにセル寸法を変更し、ｐ領
域２およびn+ソース領域４の面積に比して多結晶シリコ
ン層の面積の比率を高くしても、低減には限度があり、
ｐ領域２とn-層１の間の空乏層が広がりにくくなって耐
圧の低下という現象も発生してくる。第２図に示した低
不純物濃度の拡散層11を形成する方法は、ドープしすぎ
ると耐圧の低下やその他の特性を悪化させてしまうほ
か、ゲート下部の半導体基板表面の不純物濃度を上げて
しまうためにゲート容量が増加してしまうという問題が
ある。Even if the cell size is changed to reduce the on-resistance and the ratio of the area of the polycrystalline silicon layer to the area of the p region 2 and the area of the n + source region 4 is increased, the reduction is limited.
A depletion layer between the p region 2 and the n − layer 1 is hardly spread, and a phenomenon that the breakdown voltage is reduced also occurs. In the method of forming the diffusion layer 11 having a low impurity concentration shown in FIG. 2, if the doping is too much, the breakdown voltage is reduced and other characteristics are deteriorated, and the impurity concentration on the surface of the semiconductor substrate below the gate is increased. Therefore, there is a problem that the gate capacitance increases.
ゲート容量を低減させるために、第３図に示したよう
にゲート酸化膜５の一部を厚くする方法は、その厚い酸
化膜51の幅が広いとフィールドプレート効果がなくなっ
て耐圧が低下する問題がある。それ以外の方法は容量は
低減できるが、オン抵抗やしきい値電圧などの電気特性
が変化してしまう問題がある。The method of increasing the thickness of a part of the gate oxide film 5 as shown in FIG. 3 in order to reduce the gate capacitance has a problem that if the width of the thick oxide film 51 is large, the field plate effect is lost and the withstand voltage is reduced. There is. The other methods can reduce the capacitance, but have a problem in that electrical characteristics such as on-resistance and threshold voltage change.
本発明の目的は、これらの問題を解決し、耐圧を低下
させることなくオン抵抗を小さくし、ゲート容量を低減
させたMOS型半導体素子およびその製造方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and to provide a MOS type semiconductor device in which the ON resistance is reduced without lowering the breakdown voltage and the gate capacitance is reduced, and a method of manufacturing the same.
上記の目的を達成するために、本発明は、第一導電型
の半導体基板の表面層に複数の第二導電型のチャネル領
域を形成する工程と、半導体基板の表面上にそのチャネ
ル領域を相互間の中間部上からチャネル領域の周辺部上
にかけて延びるゲート絶縁膜であって、前記中間部上の
領域では厚く、前記周辺部上にかけての領域では薄くさ
れたゲート絶縁膜を形成する工程と、そのゲート絶縁膜
をマスクとしてゲート絶縁膜の薄い領域のみを通して不
純物を導入し、半導体基板の表面層に半導体基板より不
純物濃度の高い第一導電型の層を形成する工程と、ゲー
ト絶縁膜の上にゲートを積層する工程を含むものとす
る。In order to achieve the above object, the present invention provides a step of forming a plurality of channel regions of a second conductivity type on a surface layer of a semiconductor substrate of a first conductivity type, and forming the channel regions on a surface of the semiconductor substrate. A step of forming a gate insulating film extending from the intermediate portion on the peripheral portion of the channel region to the peripheral portion of the channel region, the gate insulating film being thick in the region on the intermediate portion and thinned in the region over the peripheral portion; Using the gate insulating film as a mask, introducing impurities only through the thin region of the gate insulating film, forming a first conductivity type layer having a higher impurity concentration than the semiconductor substrate on the surface layer of the semiconductor substrate; And a step of stacking gates.
半導体基板の表面層のチャネル領域を囲む限られた領
域のみに半導体基板より不純物濃度の高い同一導電型の
層を形成することにより、その高不純物濃度層による空
乏層容量の増加はほとんどなくなり、また、空乏層の広
がりが少なくなってＪ−FET効果が弱くなるので耐圧の
低下も起こらなく、オン抵抗が低減される。また、この
高不純物濃度を表面より少し離して形成した場合は、し
きい値電圧の低下も防ぐことができる。さらに、高不純
物濃度層によりオン抵抗を低減させたことにより、チャ
ネル領域間の寸法を小さくすることができるため、ゲー
ト絶縁膜の一部を厚くしてもフィールドプレート効果の
減退による耐圧の低下が起こらず、ゲート容量を小さく
することができる。そして厚い絶縁膜と薄い絶縁膜の境
界に傾斜面を形成することにより、電界の集中を防ぎ、
耐圧低下を防ぐことができる。これらの顕著な効果を奏
する高不純物濃度層をゲート絶縁膜の厚い部分をマスク
として容易に形成することができる。By forming a layer of the same conductivity type having a higher impurity concentration than the semiconductor substrate only in a limited region surrounding the channel region of the surface layer of the semiconductor substrate, the high impurity concentration layer hardly increases the depletion layer capacitance, and In addition, the spread of the depletion layer is reduced and the J-FET effect is weakened, so that the breakdown voltage does not decrease and the on-resistance is reduced. If the high impurity concentration is formed slightly away from the surface, the threshold voltage can be prevented from lowering. Further, since the on-resistance is reduced by the high impurity concentration layer, the dimension between the channel regions can be reduced. Therefore, even if a part of the gate insulating film is thickened, the withstand voltage is reduced due to the reduction of the field plate effect. This does not occur, and the gate capacitance can be reduced. By forming an inclined surface at the boundary between the thick insulating film and the thin insulating film, concentration of the electric field is prevented,
A decrease in withstand voltage can be prevented. A high impurity concentration layer exhibiting these remarkable effects can be easily formed using the thick portion of the gate insulating film as a mask.
第１図は本発明の一実施例を示し、以下の各図同様第
２図，第３図と共通の部分には同一の符号が付されてい
る。この場合は、第３図と同様、500〜1200Åの厚さの
ゲート酸化膜５の一部分51は6000Å近くに厚くされてい
るが、そのほかにこのゲート酸化膜を通してのドナー不
純物ドープにより、薄い部分の下にのみソース領域４よ
りも深く、p+ウエル領域３よりも浅い不純物濃度1015〜
1016/cm3のｎ層11が形成されている。このｎ層11により
オン抵抗は増加するが、領域が限られているため、空乏
層容量の増加はほとんどなくなる。FIG. 1 shows an embodiment of the present invention, and like parts to those in the following figures, parts common to FIGS. 2 and 3 are denoted by the same reference numerals. In this case, as in FIG. 3, a portion 51 of the gate oxide film 5 having a thickness of 500 to 1200 ° is thickened to about 6000 °. deeper than the source region 4 only under, p + shallow impurity concentration of 10 15 than the well region 3 to
An n layer 11 of 10 16 / cm 3 is formed. Although the ON resistance is increased by the n-layer 11, the increase in the depletion layer capacitance hardly occurs because the region is limited.
第４図は別の実施例を示し、厚い酸化膜51の周縁部に
エッチングを施し、15〜40゜の角度のテーパ面52を形成
して電界の集中を防いだものである。FIG. 4 shows another embodiment, in which the peripheral portion of the thick oxide film 51 is etched to form a tapered surface 52 having an angle of 15 to 40 ° to prevent the concentration of the electric field.
このように、ゲート酸化膜の薄い部分と厚い部分の境
界に、望ましくは15〜40゜の角度の傾斜面を形成するこ
とで耐圧低下の防止に有効である。第５図のさらに別の
実施例では、一部厚くされたゲート酸化膜５を通しての
ドナー不純物ドープにより形成したｎ層11の表面層にア
クセプタ不純物をドープし、基板１と同程度の不純物濃
度のn-層12としたもので、ドナー不純物ドープにより発
生するしきい値電圧の低下を防いだものである。As described above, by forming an inclined surface having an angle of preferably 15 to 40 ° at the boundary between the thin portion and the thick portion of the gate oxide film, it is effective to prevent a reduction in breakdown voltage. In another embodiment shown in FIG. 5, an acceptor impurity is doped into the surface layer of the n-layer 11 formed by donor impurity doping through the gate oxide film 5 partially thickened, so that the impurity concentration is substantially the same as that of the substrate 1. This is an n − layer 12, which prevents a decrease in threshold voltage caused by donor impurity doping.
このように、チャネル領域を囲む限られた領域の半導
体基板表面層を基板と同一導電型で不純物濃度の高い層
にすることにより、耐圧の低下、ゲート容量の増加を招
くことなく、オン抵抗を低減させることができ、さらに
この高不純物濃度層を表面より少し離れて形成した場合
はしきい値電圧の低下を防ぐこともできる。このように
オン抵抗を低減させることにより、ゲート酸化膜の一部
を厚くしてゲート容量の低減をはかることも可能であ
る。As described above, by making the semiconductor substrate surface layer of the limited region surrounding the channel region a layer of the same conductivity type as the substrate and having a high impurity concentration, the on-resistance can be reduced without lowering the breakdown voltage and increasing the gate capacitance. When the high impurity concentration layer is formed slightly away from the surface, a decrease in threshold voltage can be prevented. By reducing the on-resistance in this manner, it is possible to increase the thickness of a part of the gate oxide film to reduce the gate capacitance.
本発明によれば、ゲート酸化膜の厚い部分をドープの
際のマスクに利用することにより、チャネル領域を囲む
限られた領域への高不純物濃度層を容易に形成すること
ができる。また、ゲート酸化膜の薄い部分と厚い部分の
境界に、望ましくは15〜40゜の角度の傾斜面を形成する
ことが耐圧低下の防止に有効である。According to the present invention, a high impurity concentration layer in a limited region surrounding a channel region can be easily formed by using a thick portion of a gate oxide film as a mask for doping. Also, it is effective to prevent a decrease in breakdown voltage by forming an inclined surface having an angle of preferably 15 to 40 ° at a boundary between a thin portion and a thick portion of the gate oxide film.
第１図は本発明の一実施例のMOSFETを示し、そのうち
（ａ）は基板表面の平面図、（ｂ）は（ａ）のＡ−Ａ線
断面図、第２図，第３図はMOSFETの二つの従来例をそれ
ぞれ示し、そのうち（ａ）は平面図、（ｂ）は（ａ）の
Ｂ−Ｂ線およびＣ−Ｃ線断面図、第４図，第５図は本発
明の二つの異なる実施例のMOSFETの断面図である。 1:n-シリコン基板、11:n層、12:n-層、2:p型チャネル領
域、4:n+ソース領域、5:ゲート酸化膜、51:厚いゲート
酸化膜、52:テーパ面、6:多結晶シリコンゲート、7:ソ
ース電極、8:PSG膜。FIG. 1 shows a MOSFET according to an embodiment of the present invention, in which (a) is a plan view of a substrate surface, (b) is a cross-sectional view taken along the line AA of (a), and FIGS. (A) is a plan view, (b) is a cross-sectional view taken along line BB and CC of (a), and FIGS. 4 and 5 are two examples of the present invention. It is sectional drawing of the MOSFET of a different Example. 1: n - silicon substrate, 11: n-layer, 12: n - layer, 2: p-type channel region, 4: n + source region, 5: gate oxide film, 51: thick gate oxide film, 52: tapered surface, 6: polycrystalline silicon gate, 7: source electrode, 8: PSG film.
Claims (1)
第二導電型のチャネル領域を形成する工程と、半導体基
板の表面上にそのチャネル領域の相互間の中間部上から
チャネル領域の周辺部上にかけて延びるゲート絶縁膜で
あって、前記中間部上の領域では厚く、前記周辺部上に
かけての領域では薄くされたゲート絶縁膜を形成する工
程と、そのゲート絶縁膜をマスクとしてゲート絶縁膜の
薄い領域のみを通して不純物を導入し、半導体基板の表
面層より不純物濃度の高い第一導電型の層を形成する工
程と、ゲート絶縁膜の上にゲートを積層する工程とを含
むことを特徴とするMOS型半導体素子の製造方法。A step of forming a plurality of channel regions of a second conductivity type on a surface layer of a semiconductor substrate of a first conductivity type; and a step of forming a channel region on a surface of the semiconductor substrate from an intermediate portion between the channel regions. Forming a gate insulating film extending over the peripheral portion of the gate insulating film, the gate insulating film being thicker in the region above the intermediate portion and thinned in the region above the peripheral portion; and forming the gate using the gate insulating film as a mask. Introducing a impurity only through a thin region of the insulating film, forming a first conductivity type layer having a higher impurity concentration than the surface layer of the semiconductor substrate, and laminating a gate on the gate insulating film. Characteristic method for manufacturing a MOS type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2246561A JP2808871B2 (en) | 1990-09-17 | 1990-09-17 | Method for manufacturing MOS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2246561A JP2808871B2 (en) | 1990-09-17 | 1990-09-17 | Method for manufacturing MOS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04125972A JPH04125972A (en) | 1992-04-27 |
| JP2808871B2 true JP2808871B2 (en) | 1998-10-08 |
Family
ID=17150247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2246561A Expired - Lifetime JP2808871B2 (en) | 1990-09-17 | 1990-09-17 | Method for manufacturing MOS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2808871B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2689874B2 (en) * | 1993-12-17 | 1997-12-10 | 関西日本電気株式会社 | High voltage MOS transistor |
| JP2007081436A (en) * | 1996-10-18 | 2007-03-29 | Hitachi Ltd | Semiconductor device and power converter using the same |
| EP1531497A1 (en) * | 2003-11-17 | 2005-05-18 | ABB Technology AG | IGBT cathode design with improved safe operating area capability |
| JP2008262982A (en) * | 2007-04-10 | 2008-10-30 | Toyota Central R&D Labs Inc | Group iii nitride semiconductor device, and manufacturing method thereof |
| JP5246638B2 (en) * | 2007-09-14 | 2013-07-24 | 三菱電機株式会社 | Semiconductor device |
| JP5597217B2 (en) * | 2012-02-29 | 2014-10-01 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP6700648B2 (en) | 2012-10-18 | 2020-05-27 | 富士電機株式会社 | Method of manufacturing semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59151466A (en) * | 1983-02-17 | 1984-08-29 | Nissan Motor Co Ltd | Vertical type metal oxide semiconductor field-effect transistor |
| JPS6457675A (en) * | 1987-08-27 | 1989-03-03 | Nec Corp | Vertical field-effect transistor |
| JPH0237777A (en) * | 1988-07-27 | 1990-02-07 | Nec Corp | Vertical type field-effect transistor |
-
1990
- 1990-09-17 JP JP2246561A patent/JP2808871B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04125972A (en) | 1992-04-27 |
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