JP2008262982A - Group iii nitride semiconductor device, and manufacturing method thereof - Google Patents

Group iii nitride semiconductor device, and manufacturing method thereof Download PDF

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JP2008262982A
JP2008262982A JP2007103053A JP2007103053A JP2008262982A JP 2008262982 A JP2008262982 A JP 2008262982A JP 2007103053 A JP2007103053 A JP 2007103053A JP 2007103053 A JP2007103053 A JP 2007103053A JP 2008262982 A JP2008262982 A JP 2008262982A
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group iii
iii nitride
nitride semiconductor
semiconductor region
region
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Tsutomu Uesugi
勉 上杉
Hiroyuki Ueda
博之 上田
Shigemasa Soejima
成雅 副島
Toru Kachi
徹 加地
Masahiro Sugimoto
雅裕 杉本
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent a gate insulating film being broken when a plurality of semiconductor regions are formed without controlling the size or the impurity concentration thereof with high precision, and without increasing the on resistance of a semiconductor device. <P>SOLUTION: At a position opposing a part of a second group III nitride semiconductor region 16 but not opposing a third group III nitride semiconductor region 2, a gate electrode 6 is opposing a fourth group III nitride semiconductor region 12 through a gate insulating film 4. When a semiconductor device 100 is powered off, a voltage acts on the gate insulating film 4 even if depletion layers 18a and 18b extending from adjoining semiconductor regions 16 toward the semiconductor region 12 are not connected and the gate insulating film 4 is prevented from being broken. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、高耐圧デバイスあるいは高周波デバイス等に使用されるIII族窒化物半導体を利用した半導体装置に関する。特に、ゲート絶縁膜を介して半導体領域にゲート電極が対向している半導体装置において、半導体装置に高電圧が印加されたときに、そのゲート絶縁膜が破壊されることを防止する技術に関する。本発明は、その半導体装置の製造方法にも関する。   The present invention relates to a semiconductor device using a group III nitride semiconductor used for a high voltage device or a high frequency device. In particular, the present invention relates to a technique for preventing a gate insulating film from being broken when a high voltage is applied to the semiconductor device in a semiconductor device in which a gate electrode is opposed to a semiconductor region through a gate insulating film. The present invention also relates to a method for manufacturing the semiconductor device.

図１４に、従来のIII族窒化物半導体装置５００の断面図を示す。この半導体装置の基本構造は特許文献１に開示されている。半導体装置５００は、ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域２０と、III族窒化物半導体領域２０の表面において間隙１６ａを残して不連続に形成されているとともに、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域１６と、前記間隙１６ａにおいてIII族窒化物半導体領域２０の表面に形成されており、前記間隙１６ａを充填しているとともに、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域２と、III族窒化物半導体領域１６とIII族窒化物半導体領域２に跨る範囲の両領域１６，２の表面に形成されているとともに、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域１２と、III族窒化物半導体領域１２にゲート絶縁膜５０４を介して対向しているゲート電極５０６が形成されている。III族窒化物半導体領域２０の裏面に、ｎ＋型のIII族窒化物半導体領域２２が形成されている。 FIG. 14 shows a cross-sectional view of a conventional group III nitride semiconductor device 500. The basic structure of this semiconductor device is disclosed in Patent Document 1. The semiconductor device 500 is formed discontinuously with a first group III nitride semiconductor region 20 containing an n-type impurity, and leaving a gap 16a on the surface of the group III nitride semiconductor region 20. A second group III nitride semiconductor region 16 containing a type impurity, and is formed on the surface of the group III nitride semiconductor region 20 in the gap 16a, filling the gap 16a, and n-type And the third group III nitride semiconductor region 2 containing the impurities, and the surfaces of both the regions 16 and 2 in the range extending over the group III nitride semiconductor region 16 and the group III nitride semiconductor region 2. A fourth group III nitride semiconductor region 12 containing n-type impurities and a gate electrode 506 facing the group III nitride semiconductor region 12 with a gate insulating film 504 interposed therebetween are formed. An n + -type group III nitride semiconductor region 22 is formed on the back surface of the group III nitride semiconductor region 20.

従来の半導体装置５００は、ゲート電極５０６に電圧を印加していない状態では、III族窒化物半導体領域１６とIII族窒化物半導体領域１２の界面からビルトイン電圧に相当する空乏層が伸びる。その結果、III族窒化物半導体領域１６の表面に形成されている部分ではIII族窒化物半導体領域１２が空乏化されるため、電子が走行することができない。ゲート電極５０６に正電圧が印加されると、III族窒化物半導体領域１２に伸びていた空乏層が縮小し、III族窒化物半導体領域１２内を電子が走行することができる。従来の半導体装置５００は、ノーマリーオフ型であり、ゲート電極５０６によってオンオフを制御している。   In the conventional semiconductor device 500, when no voltage is applied to the gate electrode 506, a depletion layer corresponding to the built-in voltage extends from the interface between the group III nitride semiconductor region 16 and the group III nitride semiconductor region 12. As a result, the group formed on the surface of the group III nitride semiconductor region 16 is depleted in the group III nitride semiconductor region 12, and electrons cannot travel. When a positive voltage is applied to the gate electrode 506, the depletion layer extending to the group III nitride semiconductor region 12 is reduced, and electrons can travel in the group III nitride semiconductor region 12. The conventional semiconductor device 500 is a normally-off type, and on / off is controlled by a gate electrode 506.

特開２００４−２６０１４０号公報JP 2004-260140 A

従来の半導体装置５００では、半導体装置５００をオフしたときに、III族窒化物半導体領域１６とIII族窒化物半導体領域１２の界面から空乏層が伸びる他に、III族窒化物半導体領域１６とIII族窒化物半導体領域２の界面ならびに、III族窒化物半導体領域１６とIII族窒化物半導体領域２０の界面からも空乏層が伸びる。
図１４に示しているように、空乏層は、前記した界面からライン１８ａ，１８ｂに示すように伸び、最終的にはライン１９に示すようにつながる。空乏層がつながることによって、III族窒化物半導体領域２は空乏化され、III族窒化物半導体領域２の表面側に形成されているゲート絶縁膜５０４に高い電界がかかることを防止している。
上述したように、従来の半導体装置５００は、ゲート電極５０６によって、オンオフを制御している。すなわち、ゲート電極５０６に印加する電圧を高くし、電圧が閾値電圧を超えると半導体装置５００がオンする。ゲート電極５０６に印加する電圧が閾値電圧よりも低くなると半導体装置５００がオフする。閾値電圧を下げるためにはゲート絶縁膜５０４を薄くする必要がある。そのため、ゲート絶縁膜５０４は過大電圧が作用すると、破壊されやすい。 In the conventional semiconductor device 500, when the semiconductor device 500 is turned off, a depletion layer extends from the interface between the group III nitride semiconductor region 16 and the group III nitride semiconductor region 12, and the group III nitride semiconductor region 16 and III A depletion layer also extends from the interface between group nitride semiconductor region 2 and the interface between group III nitride semiconductor region 16 and group III nitride semiconductor region 20.
As shown in FIG. 14, the depletion layer extends from the above-described interface as indicated by lines 18 a and 18 b and is finally connected as indicated by line 19. By connecting the depletion layer, the group III nitride semiconductor region 2 is depleted, and a high electric field is prevented from being applied to the gate insulating film 504 formed on the surface side of the group III nitride semiconductor region 2.
As described above, in the conventional semiconductor device 500, on / off is controlled by the gate electrode 506. That is, when the voltage applied to the gate electrode 506 is increased and the voltage exceeds the threshold voltage, the semiconductor device 500 is turned on. When the voltage applied to the gate electrode 506 is lower than the threshold voltage, the semiconductor device 500 is turned off. In order to reduce the threshold voltage, the gate insulating film 504 needs to be thin. Therefore, the gate insulating film 504 is easily destroyed when an excessive voltage is applied.

ゲート絶縁膜５０４に過大な電圧が作用しないようにするためには、半導体装置５００をオフしたときに、ｐ型のIII族窒化物半導体領域１６とその周囲に存在するｎ型のIII族窒化物半導体領域１２，２，２０の界面から伸びる空乏層が、図１４のライン１９に示すようにをつながることが重要である。そのために、III族窒化物半導体領域１６に残す間隙１６ａの距離や、III族窒化物半導体領域２の不純物濃度を高精度に制御することが必要である。しかしながら、間隙１６ａやIII族窒化物半導体領域２は、複数の工程を経て製造されるため、間隙１６ａの幅やIII族窒化物半導体領域２の不純物濃度を高精度に制御することは困難である。   In order to prevent an excessive voltage from acting on the gate insulating film 504, when the semiconductor device 500 is turned off, the p-type group III nitride semiconductor region 16 and the n-type group III nitride existing therearound are provided. It is important that the depletion layer extending from the interface of the semiconductor regions 12, 2, 20 is connected as shown by the line 19 in FIG. Therefore, it is necessary to control the distance of the gap 16a remaining in the group III nitride semiconductor region 16 and the impurity concentration of the group III nitride semiconductor region 2 with high accuracy. However, since the gap 16a and the group III nitride semiconductor region 2 are manufactured through a plurality of processes, it is difficult to control the width of the gap 16a and the impurity concentration of the group III nitride semiconductor region 2 with high accuracy. .

従来の半導体装置５００では、左右のIII族窒化物半導体領域１６から伸びる空乏層を確実につなげるために、間隙１６ａの幅を必要以上に狭くするか、あるいは、III族窒化物半導体領域２の不純物濃度を必要以上に薄くしなくてはいけない。しかしながら、間隙１６ａの幅を過剰に狭くしたり、III族窒化物半導体領域２の不純物濃度を過剰に薄くすると、半導体装置５００をオンしたときのオン抵抗が大きくなってしまう。   In the conventional semiconductor device 500, in order to connect the depletion layers extending from the left and right group III nitride semiconductor regions 16 with certainty, the width of the gap 16a is narrowed more than necessary, or the impurities in the group III nitride semiconductor region 2 The concentration should be made thinner than necessary. However, if the width of the gap 16a is excessively narrowed or the impurity concentration of the group III nitride semiconductor region 2 is excessively thin, the on-resistance when the semiconductor device 500 is turned on increases.

本発明は、上記の問題を解決することを目的とする。すなわち、間隙１６ａの幅やIII族窒化物半導体領域２の不純物濃度を高精度に制御する必要がなく、それでいてゲート絶縁膜に過大な電圧が作用し、ゲート絶縁膜が破壊されることを確実に防止できる半導体装置を提供する。また、半導体装置のオン抵抗を大きくすることなく、ゲート絶縁膜に過大な電圧が作用し、ゲート絶縁膜が破壊されることを確実に防止できる半導体装置を提供する。   The present invention aims to solve the above problems. That is, it is not necessary to control the width of the gap 16a and the impurity concentration of the group III nitride semiconductor region 2 with high precision, and it is ensured that an excessive voltage acts on the gate insulating film and the gate insulating film is destroyed. A semiconductor device capable of preventing the problem is provided. Further, it is possible to provide a semiconductor device capable of reliably preventing an excessive voltage from acting on the gate insulating film and destroying the gate insulating film without increasing the on-resistance of the semiconductor device.

本発明の半導体装置は、ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域と、第１のIII族窒化物半導体領域の表面において間隙を残して不連続に形成されているとともに、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、第２のIII族窒化物半導体領域の前記間隙において第１のIII族窒化物半導体領域の表面に形成されており、前記間隙を充填しているとともに、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、第２のIII族窒化物半導体領域と第３のIII族窒化物半導体領域に跨る範囲の前記領域の表面に形成されているとともに、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域と、第２のIII族窒化物半導体領域の一部には対向するけれども第３のIII族窒化物半導体領域には対向しない位置において、第４のIII族窒化物半導体領域にゲート絶縁膜を介して対向しているゲート電極を備えている。   The semiconductor device of the present invention is formed discontinuously leaving a gap on the surface of the first group III nitride semiconductor region containing n-type impurities and the first group III nitride semiconductor region. , Formed on the surface of the first group III nitride semiconductor region in the gap between the second group III nitride semiconductor region containing the p-type impurity and the second group III nitride semiconductor region, A third group III nitride semiconductor region that fills the gap and contains an n-type impurity, and a range that spans the second group III nitride semiconductor region and the third group III nitride semiconductor region The fourth group III nitride semiconductor region containing the n-type impurity and a part of the second group III nitride semiconductor region are opposed to the third group nitride region, but are formed on the surface of the region. In a position not facing the group III nitride semiconductor region of the fourth I A gate electrode is provided opposite to the group II nitride semiconductor region via a gate insulating film.

上記の半導体装置によると、ゲート絶縁膜は、第３のIII族窒化物半導体領域からみて、第２のIII族窒化物半導体領域と第４のIII族窒化物半導体領域が対向している位置よりも遠方に形成されている。半導体装置がオフされている場合、第２のIII族窒化物半導体領域と第４のIII族窒化物半導体領域が対向している位置では、第４のIII族窒化物半導体領域が空乏化されている。このために、左右に離れて存在する第２のIII族窒化物半導体領域から第３のIII族窒化物半導体領域に向けて伸びる空乏層がつながらなくても、ゲート絶縁膜に高い電圧が作用することを防止できる。左右に離れて存在する第２のIII族窒化物半導体領域の距離（間隙の幅）や、第３のIII族窒化物半導体領域の不純物濃度を高精度に制御しなくても、半導体装置をオフしたときにゲート絶縁膜に高い電圧がかかることを抑制できる。半導体装置のオン抵抗を大きくすることなく、ゲート絶縁膜に過剰な電圧がかかることを防止できる。   According to the semiconductor device described above, the gate insulating film is seen from the position where the second group III nitride semiconductor region and the fourth group III nitride semiconductor region face each other when viewed from the third group III nitride semiconductor region. Is also formed far away. When the semiconductor device is turned off, the fourth group III nitride semiconductor region is depleted at the position where the second group III nitride semiconductor region and the fourth group III nitride semiconductor region face each other. Yes. Therefore, a high voltage acts on the gate insulating film even if a depletion layer extending from the second group III nitride semiconductor region that exists apart from the left and right to the third group III nitride semiconductor region is not connected. Can be prevented. The semiconductor device can be turned off without accurately controlling the distance (gap width) of the second group III nitride semiconductor region and the impurity concentration of the third group III nitride semiconductor region that are separated from each other on the left and right. In this case, it is possible to prevent a high voltage from being applied to the gate insulating film. It is possible to prevent an excessive voltage from being applied to the gate insulating film without increasing the on-resistance of the semiconductor device.

本発明の半導体装置では、半導体装置の断面を観察したときに、第４のIII族窒化物半導体領域の厚みが、第３のIII族窒化物半導体領域に近い部分では厚く、第３のIII族窒化物半導体領域から遠い部分では薄く形成されていることが好ましい。   In the semiconductor device of the present invention, when the cross section of the semiconductor device is observed, the thickness of the fourth group III nitride semiconductor region is thicker in the portion close to the third group III nitride semiconductor region, and the third group III group It is preferable that a thin portion is formed in a portion far from the nitride semiconductor region.

表面にゲート電極が形成されていない領域（例えば、第２のIII族窒化物半導体領域と第３のIII族窒化物半導体領域の境界近傍に形成されている第４のIII族窒化物半導体領域）では、ｐ型領域とｎ型領域のビルトイン電圧によって生じた空乏層が、半導体装置をオンしても消失しにくい。空乏層が消失しにくいと、半導体装置のオン抵抗が大きくなってしまう。しかしながら、上記の半導体装置によると、半導体装置をオンしたときに、第４のIII族窒化物半導体領域の厚みが厚い部分をキャリアが走行しやすい。半導体装置を上記のように構成することによって、半導体装置のオン抵抗を小さくすることができる。   Region in which no gate electrode is formed on the surface (for example, a fourth group III nitride semiconductor region formed near the boundary between the second group III nitride semiconductor region and the third group III nitride semiconductor region) Then, the depletion layer generated by the built-in voltage in the p-type region and the n-type region is not easily lost even when the semiconductor device is turned on. If the depletion layer is difficult to disappear, the on-resistance of the semiconductor device increases. However, according to the semiconductor device described above, when the semiconductor device is turned on, the carrier easily travels through the thick portion of the fourth group III nitride semiconductor region. By configuring the semiconductor device as described above, the on-resistance of the semiconductor device can be reduced.

本発明の半導体装置では、半導体装置の断面を観察したときに、第２のIII族窒化物半導体領域の厚みが、第３のIII族窒化物半導体領域に近い部分では薄く、第３のIII族窒化物半導体領域から遠い部分では厚く形成することもできる。   In the semiconductor device of the present invention, when the cross section of the semiconductor device is observed, the thickness of the second group III nitride semiconductor region is thin at a portion close to the third group III nitride semiconductor region, and the third group III nitride semiconductor region is thin. It can also be formed thicker at a portion far from the nitride semiconductor region.

上記の半導体装置によると、第４のIII族窒化物半導体領域の表面を平坦に形成しても、第４のIII族窒化物半導体領域の厚みが、第３のIII族窒化物半導体領域に近い部分では厚く、第３のIII族窒化物半導体領域に遠い部分では薄く形成することができる。半導体装置をオンしたときにキャリアが走行できるチャネルを確保することができる。また、第４のIII族窒化物半導体領域の表面を平坦に形成すると、半導体装置の表面の構造を単純化することができる。   According to the above semiconductor device, even if the surface of the fourth group III nitride semiconductor region is formed flat, the thickness of the fourth group III nitride semiconductor region is close to that of the third group III nitride semiconductor region. It can be formed thick in the portion and thin in the portion far from the third group III nitride semiconductor region. When the semiconductor device is turned on, a channel on which the carrier can travel can be secured. Further, when the surface of the fourth group III nitride semiconductor region is formed flat, the surface structure of the semiconductor device can be simplified.

本発明の半導体装置では、ゲート絶縁膜が、第４のIII族窒化物半導体領域が厚く形成されている部分と、第４のIII族窒化物半導体領域が薄く形成されている部分に跨る範囲に形成されていることが好ましい。
上記の半導体装置によると、半導体装置をオンしたときに、第４のIII族窒化物半導体領域が厚く形成されている部分の空乏層も消失させることができる。半導体装置のオン抵抗をより小さくすることができる。 In the semiconductor device of the present invention, the gate insulating film is in a range extending over the portion where the fourth group III nitride semiconductor region is formed thick and the portion where the fourth group III nitride semiconductor region is formed thin. Preferably it is formed.
According to the semiconductor device described above, when the semiconductor device is turned on, the depletion layer in the portion where the fourth group III nitride semiconductor region is formed thick can be eliminated. The on-resistance of the semiconductor device can be further reduced.

本発明では上記した半導体装置とは異なる形態の半導体装置も提供する。その半導体装置は、ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域と、第１のIII族窒化物半導体領域の表面において間隙を残して不連続に形成されているとともに、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、第２のIII族窒化物半導体領域の間隙において第１のIII族窒化物半導体領域の表面に形成されており、その間隙を充填しているとともに、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、第２のIII族窒化物半導体領域と第３のIII族窒化物半導体領域に跨る範囲の両領域の表面に形成されているとともに、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域と、第４のIII族窒化物半導体領域の表面にゲート絶縁膜を介して対向するゲート電極を備えており、そのゲート絶縁膜が、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域に近い範囲と第３のIII族窒化物半導体領域に対向する範囲では厚く、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域から遠い範囲に対向する範囲では薄く形成されている。   The present invention also provides a semiconductor device having a different form from the semiconductor device described above. The semiconductor device is formed discontinuously leaving a gap on the surface of the first group III nitride semiconductor region containing the n-type impurity and the first group III nitride semiconductor region, and p Is formed on the surface of the first group III nitride semiconductor region in the gap between the second group III nitride semiconductor region containing the impurity of the type and the second group III nitride semiconductor region. A third group III nitride semiconductor region which is filled and contains an n-type impurity, and both regions in a range extending over the second group III nitride semiconductor region and the third group III nitride semiconductor region A fourth group III nitride semiconductor region containing an n-type impurity, and a gate electrode facing the surface of the fourth group III nitride semiconductor region with a gate insulating film interposed therebetween And the gate insulating film is a second group III nitride. The conductor region is thicker in the range close to the third group III nitride semiconductor region and in the range opposite to the third group III nitride semiconductor region, and the third III of the second group III nitride semiconductor region. The thin film is formed in a range facing a range far from the group nitride semiconductor region.

上記の半導体装置によると、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域に近い範囲と第３のIII族窒化物半導体領域に対向する範囲では、ゲート絶縁膜の厚みが厚いため、半導体装置をオフしたときにゲート絶縁膜に高い電圧がかかっても、ゲート絶縁膜が破壊されることを防止できる。第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域から遠い範囲に対向する範囲では、ゲート絶縁膜の厚みが薄くても、半導体装置をオフしたときに、第４のIII族窒化物半導体領域が空乏化されるため、ゲート絶縁膜に高い電圧がかかることを防止できる。左右に離れて存在する第２のIII族窒化物半導体領域の距離（間隙の幅）や、第３のIII族窒化物半導体領域の不純物濃度を高精度に制御しなくても、半導体装置をオフしたときにゲート絶縁膜が破壊されることを防止できる。半導体装置のオン抵抗を大きくすることなく、ゲート絶縁膜が破壊されることを防止できる。   According to the semiconductor device described above, in the range close to the third group III nitride semiconductor region and the range facing the third group III nitride semiconductor region in the second group III nitride semiconductor region, the gate insulating film Therefore, even when a high voltage is applied to the gate insulating film when the semiconductor device is turned off, the gate insulating film can be prevented from being broken. In the second group III nitride semiconductor region, in the range facing the range far from the third group III nitride semiconductor region, even when the gate insulating film is thin, when the semiconductor device is turned off, Since the group III nitride semiconductor region is depleted, it is possible to prevent a high voltage from being applied to the gate insulating film. The semiconductor device can be turned off without accurately controlling the distance (gap width) of the second group III nitride semiconductor region and the impurity concentration of the third group III nitride semiconductor region that are separated from each other on the left and right. In this case, the gate insulating film can be prevented from being broken. The gate insulating film can be prevented from being destroyed without increasing the on-resistance of the semiconductor device.

本発明の半導体装置では、第４のIII族窒化物半導体領域の誘電率εとし、第４のIII族窒化物半導体領域の不純物濃度をＮとし、第２のIII族窒化物半導体領域と第４のIII族窒化物半導体領域のビルトイン電圧をＶとし、電荷素量をｑとしたときに、第４のIII族窒化物半導体領域の最も薄い部分の厚みＬが、下記式（１）を満足することが好ましい。
Ｌ≦（２×ε×Ｖ／ｑ）０．５×（１／Ｎ）０．５ （１） In the semiconductor device of the present invention, the dielectric constant ε of the fourth group III nitride semiconductor region is set to N, the impurity concentration of the fourth group III nitride semiconductor region is set to N, and the second group III nitride semiconductor region and the fourth group III nitride semiconductor region are The thickness L of the thinnest portion of the fourth group III nitride semiconductor region satisfies the following formula (1) when the built-in voltage of the group III nitride semiconductor region is V and the elementary charge is q: It is preferable.
L ≦ (2 × ε × V / q) 0.5 × (1 / N) 0.5 (1)

上記の半導体装置によると、半導体装置に電圧が印加されていない状態でも、第４のIII族窒化物半導体領域の最も薄い部分が空乏化される。半導体装置をオフしたときに、より確実にキャリアの移動を禁止することができる。なお、「ビルトイン電圧」とは、導電型の異なる半導体同士を接合したときに、両者の間に発生する電圧のことをいう。また、電荷素量は定数であり、その値は、およそ１．６×１０−１９Ｃ（クーロン）である。 According to the semiconductor device, the thinnest portion of the fourth group III nitride semiconductor region is depleted even when no voltage is applied to the semiconductor device. When the semiconductor device is turned off, carrier movement can be more reliably prohibited. The “built-in voltage” refers to a voltage generated between semiconductors having different conductivity types when they are joined together. The elementary charge is a constant, and its value is approximately 1.6 × 10 −19 C (Coulomb).

本発明の半導体装置では、第４のIII族窒化物半導体領域が、バンドギャップの狭いIII族窒化物半導体層と、バンドギャップの広いIII族窒化物半導体層の積層で構成することもできる。
上記の半導体装置によると、バンドギャップの狭いIII族窒化物半導体層とバンドギャップの広いIII族窒化物半導体層によってヘテロ接合が形成される。バンドギャップの狭いIII族窒化物半導体層とバンドギャップの広いIII族窒化物半導体層の間に、２次元電子ガス領域が形成され、その２次元電子ガス領域を電子が移動できる。電子の移動抵抗が小さくなり、半導体装置のオン抵抗を小さくすることができる。 In the semiconductor device of the present invention, the fourth group III nitride semiconductor region may be formed of a stack of a group III nitride semiconductor layer having a narrow band gap and a group III nitride semiconductor layer having a wide band gap.
According to the above semiconductor device, a heterojunction is formed by the group III nitride semiconductor layer having a narrow band gap and the group III nitride semiconductor layer having a wide band gap. A two-dimensional electron gas region is formed between the group III nitride semiconductor layer having a narrow band gap and the group III nitride semiconductor layer having a wide band gap, and electrons can move through the two-dimensional electron gas region. Electron transfer resistance is reduced, and the on-resistance of the semiconductor device can be reduced.

本発明では半導体装置の製造方法をも提供する。その方法は、ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域の表面に、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域の各々のIII族窒化物半導体領域が、第１のIII族窒化物半導体領域の表面に接する状態で順に配置されている積層構造を形成する工程と、一方の第２のIII族窒化物半導体領域から第３のIII族窒化物半導体領域を経て他方の第２のIII族窒化物半導体領域に跨る範囲の表面に、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域を結晶成長させる工程と、第２のIII族窒化物半導体領域の一部には対向するけれども第３のIII族窒化物半導体領域には対向しない位置において、第４のIII族窒化物半導体領域にゲート絶縁膜を介して対向しているゲート電極を形成する工程を有している。   The present invention also provides a method for manufacturing a semiconductor device. The method includes a second group III nitride semiconductor region containing a p-type impurity on the surface of the first group III nitride semiconductor region containing an n-type impurity, and an n-type impurity. Each of the group III nitride semiconductor regions of the third group III nitride semiconductor region and the second group III nitride semiconductor region containing the p-type impurity is a first group III nitride semiconductor region. Forming a laminated structure sequentially arranged in contact with the surface of the semiconductor layer, and passing through the third group III nitride semiconductor region from one second group III nitride semiconductor region to the other second group III nitride A step of crystal-growing a fourth group III nitride semiconductor region containing an n-type impurity on the surface of the region extending over the semiconductor layer, and a portion of the second group III nitride semiconductor region. However, in a position not facing the third group III nitride semiconductor region, the fourth group III nitride And a step of forming a gate electrode are opposed to each other via the gate insulating film on a semiconductor region.

上記の方法によると、隣接する第２のIII族窒化物半導体領域の距離や、第３のIII族窒化物半導体領域の不純物濃度を高精度に制御することなく、ゲート絶縁膜に高い電圧がかかることを防止できる半導体装置を製造することができる。また、半導体装置のオン抵抗を大きくすることなく、ゲート絶縁膜に過剰の電圧がかかることを防止できる半導体装置を製造することができる。また、第４のIII族窒化物半導体領域を結晶成長させるため、第４のIII族窒化物半導体領域の厚みや不純物濃度等を制御しやすい。特性の安定した半導体装置を製造することができる。   According to the above method, a high voltage is applied to the gate insulating film without accurately controlling the distance between the adjacent second group III nitride semiconductor regions and the impurity concentration of the third group III nitride semiconductor region. A semiconductor device that can prevent this can be manufactured. Further, it is possible to manufacture a semiconductor device that can prevent an excessive voltage from being applied to the gate insulating film without increasing the on-resistance of the semiconductor device. Further, since the fourth group III nitride semiconductor region is crystal-grown, the thickness, impurity concentration, etc. of the fourth group III nitride semiconductor region can be easily controlled. A semiconductor device with stable characteristics can be manufactured.

本発明では半導体装置の他の製造方法をも提供することができる。その製造方法は、ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域の表面に、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域の各々のIII族窒化物半導体領域が、第１のIII族窒化物半導体領域の表面に接する状態で順に配置されている積層構造を形成する工程と、一方の第２のIII族窒化物半導体領域から第３のIII族窒化物半導体領域を経て他方の第２のIII族窒化物半導体領域に跨る範囲の表面に、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域を結晶成長させる工程と、第４のIII族窒化物半導体領域の表面にゲート絶縁膜を形成する工程と、ゲート絶縁膜の表面にゲート電極を形成する工程を有している。ゲート絶縁膜の形成工程では、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域から近い範囲と第３のIII族窒化物半導体領域に対向する範囲では厚く形成し、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域から遠い範囲に対向する範囲では薄く形成する。   The present invention can also provide another method for manufacturing a semiconductor device. In the manufacturing method, a second group III nitride semiconductor region containing a p-type impurity and an n-type impurity are formed on the surface of the first group III nitride semiconductor region containing an n-type impurity. Each of the group III nitride semiconductor regions of the third group III nitride semiconductor region including the second group III nitride semiconductor region including the p-type impurity is a first group III nitride semiconductor. A step of forming a stacked structure sequentially arranged in contact with the surface of the region, and from the second group III nitride semiconductor region through the third group III nitride semiconductor region to the other second group III A step of crystal-growing a fourth group III nitride semiconductor region containing an n-type impurity on a surface in a range extending over the nitride semiconductor region, and a gate insulating film on the surface of the fourth group III nitride semiconductor region And a step of forming a gate electrode on the surface of the gate insulating film. That. In the gate insulating film formation step, the second group III nitride semiconductor region is formed thicker in the range close to the third group III nitride semiconductor region and in the range facing the third group III nitride semiconductor region. The second group III nitride semiconductor region is thinly formed in a range facing a range far from the third group III nitride semiconductor region.

上記の方法によると、隣接する第２のIII族窒化物半導体領域の距離や、第３のIII族窒化物半導体領域の不純物濃度を高精度に制御することなく、ゲート絶縁膜が破壊されることを防止できる半導体装置を製造することができる。また、半導体装置のオン抵抗を大きくすることなく、ゲート絶縁膜が破壊されることを防止できる半導体装置を製造することができる。   According to the above method, the gate insulating film is destroyed without accurately controlling the distance between the adjacent second group III nitride semiconductor regions and the impurity concentration of the third group III nitride semiconductor region. Can be manufactured. Further, it is possible to manufacture a semiconductor device that can prevent the gate insulating film from being destroyed without increasing the on-resistance of the semiconductor device.

本発明の半導体装置によると、複数の半導体領域を形成する際に、それらのサイズや、含まれる不純物濃度を高精度に制御する必要がなく、半導体装置をオフしたときに半導体装置が破壊されることを防止できる半導体装置を実現する。また、オン抵抗の小さい半導体装置を実現することができる。   According to the semiconductor device of the present invention, when forming a plurality of semiconductor regions, it is not necessary to control the size and concentration of contained impurities with high precision, and the semiconductor device is destroyed when the semiconductor device is turned off. A semiconductor device that can prevent this is realized. In addition, a semiconductor device with low on-resistance can be realized.

実施例の主要な特徴を列記する。
（特徴１） 第２のIII族窒化物半導体領域の表面に、ｎ型の不純物を高濃度に含んでいる第５のIII族窒化物半導体領域が形成されている。ゲート電極は、第４のIII族窒化物半導体領域と第５のIII族窒化物半導体領域に跨る範囲に、ゲート絶縁膜を介して対向している。
（特徴２） 第１のIII族窒化物半導体領域の裏面に、ｎ型の不純物を高濃度に含んでいる第６のIII族窒化物半導体領域が形成されている。
（特徴３） 第５のIII族窒化物半導体領域に一方の主電極（ソース電極）が接続されており、第６のIII族窒化物半導体領域に他方の主電極（ドレイン電極）が接続されている。
（特徴４） ゲート電極とソース電極の間を電気的に分離している電極絶縁膜が形成されている。 The main features of the examples are listed.
(Feature 1) A fifth group III nitride semiconductor region containing an n-type impurity at a high concentration is formed on the surface of the second group III nitride semiconductor region. The gate electrode is opposed to the range spanning the fourth group III nitride semiconductor region and the fifth group III nitride semiconductor region via the gate insulating film.
(Feature 2) A sixth group III nitride semiconductor region containing an n-type impurity at a high concentration is formed on the back surface of the first group III nitride semiconductor region.
(Feature 3) One main electrode (source electrode) is connected to the fifth group III nitride semiconductor region, and the other main electrode (drain electrode) is connected to the sixth group III nitride semiconductor region. Yes.
(Feature 4) An electrode insulating film that electrically separates the gate electrode and the source electrode is formed.

図面を参照して以下に実施例を詳細に説明する。
（第１実施例）
図１に、縦型のIII族窒化物半導体装置１００の断面図を示す。図１の断面図は半導体装置１００の単位構造を示し、この単位構造が紙面左右方向に繰り返し形成されている。なお、各部の構成は、実際のサイズの縮尺を正確に表すものではない。図面の明瞭化のために、図面の縮尺を適宜変更している。また、一部の構成についてはハッチングを省略している。
半導体装置１００の裏面に、ドレイン電極（他方の主電極）２４が形成されている。ドレイン電極２４上に、窒化ガリウム（ＧａＮ）を主材料とするｎ＋型のドレイン領域（第６のIII族窒化物半導体領域）２２が形成されている。ドレイン領域２２上に、窒化ガリウムを主材料とするｎ型のドリフト領域（第１のIII族窒化物半導体領域）２０が形成されている。
ドリフト領域２０の表面に、窒化ガリウムを主材料とするｐ型のボディ領域（第２のIII族窒化物半導体領域）１６が間隙１６ａを残して不連続に形成されている。複数個のボディ領域１６がドリフト領域２０の表面に形成されており、隣接するボディ領域１６，１６の間は、窒化ガリウムを主材料とするｎ型のアパーチャ領域（第３のIII族窒化物半導体領域）２が充填されている。すなわち、アパーチャ領域２は、ドリフト領域２０の表面に形成されており、ボディ領域１６に残されている間隙１６ａを充填している。半導体装置１００を平面視したときに、各々のボディ領域１６とアパーチャ領域２は紙面奥行き方向に長く伸びており、複数個のボディ領域１６とアパーチャ領域２がストライプ状に配置されている。なお、本実施例の半導体装置１００では、ボディ領域１６の不純物濃度がおよそ５×１０１９ｃｍ−３に調節されている。 Embodiments will be described in detail below with reference to the drawings.
(First embodiment)
FIG. 1 shows a cross-sectional view of a vertical group III nitride semiconductor device 100. The cross-sectional view of FIG. 1 shows a unit structure of the semiconductor device 100, and this unit structure is repeatedly formed in the left-right direction on the paper. Note that the configuration of each part does not accurately represent the actual size scale. In order to clarify the drawing, the scale of the drawing is appropriately changed. Further, hatching is omitted for some configurations.
A drain electrode (the other main electrode) 24 is formed on the back surface of the semiconductor device 100. On the drain electrode 24, an n + -type drain region (sixth group III nitride semiconductor region) 22 containing gallium nitride (GaN) as a main material is formed. An n-type drift region (first group III nitride semiconductor region) 20 mainly composed of gallium nitride is formed on the drain region 22.
On the surface of the drift region 20, a p-type body region (second group III nitride semiconductor region) 16 containing gallium nitride as a main material is formed discontinuously leaving a gap 16a. A plurality of body regions 16 are formed on the surface of the drift region 20, and an n-type aperture region (third group III nitride semiconductor) mainly composed of gallium nitride is formed between adjacent body regions 16 and 16. Region 2) is filled. That is, the aperture region 2 is formed on the surface of the drift region 20 and fills the gap 16 a remaining in the body region 16. When the semiconductor device 100 is viewed in plan, each body region 16 and the aperture region 2 extend long in the depth direction of the drawing, and the plurality of body regions 16 and the aperture regions 2 are arranged in a stripe shape. In the semiconductor device 100 of this example, the impurity concentration of the body region 16 is adjusted to about 5 × 10 19 cm −3 .

ボディ領域１６とアパーチャ領域２に跨る範囲の表面に、窒化ガリウムを主材料とするｎ型の半導体領域（第４のIII族窒化物半導体領域）１２が形成されている。半導体領域１２の不純物にはシリコンが用いられており、不純物濃度はおよそ１×１０１６ｃｍ−３に調節されている。半導体領域１２の紙面左右方向の両端部に、ｎ型の不純物を高濃度に含んでいるソース領域（第５のIII族窒化物半導体領域）１４が形成されている。ソース領域１４にソース電極（一方の主電極）１０が接続されている。なお、ソース領域１４は、半導体装置１００を平面視したときに、アパーチャ領域２と半導体領域１２が接する範囲の半導体領域１２には接していない。
半導体領域１２とソース領域１４に跨る範囲に、ゲート絶縁膜４が形成されている。ゲート絶縁膜４は、ボディ領域１６の一部には対向するけれどもアパーチャ領域２には対向しない位置に形成されている。ゲート絶縁膜の表面にゲート電極６が形成されている。すなわち、ゲート電極６は、ボディ領域１６の一部には対向するけれどもアパーチャ領域２には対向しない位置において、半導体領域１２にゲート絶縁膜４を介して対向している。ソース電極１４とゲート電極６は、電極絶縁膜８によって電気的に分離されている。 An n-type semiconductor region (fourth group III nitride semiconductor region) 12 containing gallium nitride as a main material is formed on the surface in a range extending between the body region 16 and the aperture region 2. Silicon is used as an impurity in the semiconductor region 12, and the impurity concentration is adjusted to about 1 × 10 16 cm −3 . A source region (fifth group III nitride semiconductor region) 14 containing an n-type impurity at a high concentration is formed at both ends of the semiconductor region 12 in the horizontal direction of the drawing. A source electrode (one main electrode) 10 is connected to the source region 14. The source region 14 is not in contact with the semiconductor region 12 in a range where the aperture region 2 and the semiconductor region 12 are in contact when the semiconductor device 100 is viewed in plan.
A gate insulating film 4 is formed in a range straddling the semiconductor region 12 and the source region 14. The gate insulating film 4 is formed at a position facing the part of the body region 16 but not facing the aperture region 2. A gate electrode 6 is formed on the surface of the gate insulating film. That is, the gate electrode 6 faces the semiconductor region 12 via the gate insulating film 4 at a position facing the part of the body region 16 but not facing the aperture region 2. The source electrode 14 and the gate electrode 6 are electrically separated by the electrode insulating film 8.

半導体装置１００の動作を説明する。
ｐ型のボディ領域１６の表面にｎ型の半導体領域１２が形成されている。ゲート電極６に電圧を印加していない状態では、半導体領域１２に空乏層が形成され、半導体領域１２内を電子が走行することができない。すなわち、半導体装置１００はオフしている。なお、本実施例の半導体装置１００は、半導体領域１２の厚みＬが、下記式（１）を満足している。
Ｌ≦（２×ε×Ｖ／ｑ）０．５×（１／Ｎ）０．５ （１）
上記式において、εは半導体領域１２の誘電率を示し、Ｖは半導体領域１２とボディ領域１６のビルトイン電圧を示し、ｑは電荷素量を示し、Ｎは半導体領域１２の不純物濃度を示している。
上述したように半導体装置１００では、ボディ領域１６の不純物濃度がおよそ５×１０１９ｃｍ−３に調節されており、半導体領域１２の不純物濃度がおよそ１×１０１６ｃｍ−３に調節されている。ボディ領域１６の不純物濃度が充分に大きいため、半導体領域１２とボディ領域１６の間のビルトイン電圧によって生じる空乏層は、ほとんど半導体領域１２内に形成される。ボディ領域１６と半導体領域１２の界面から半導体領域１２に向けて伸びる空乏層の厚みＷは、半導体領域１２の不純物濃度で決定し、下記式（２）で示すことができる。
Ｗ＝（２×ε×Ｖ／ｑ）０．５×（１／Ｎ）０．５ （２）
式（１），式（２）から明らかなように、半導体領域１２の厚みＬは、半導体領域１２とボディ領域１６の間のビルトイン電圧によって生じる空乏層の厚みＷ以下である。すなわち、半導体装置１００をオフしたときに、電子の移動を確実に禁止することができる。 The operation of the semiconductor device 100 will be described.
An n-type semiconductor region 12 is formed on the surface of the p-type body region 16. When no voltage is applied to the gate electrode 6, a depletion layer is formed in the semiconductor region 12, and electrons cannot travel in the semiconductor region 12. That is, the semiconductor device 100 is off. In the semiconductor device 100 of this example, the thickness L of the semiconductor region 12 satisfies the following formula (1).
L ≦ (2 × ε × V / q) 0.5 × (1 / N) 0.5 (1)
In the above formula, ε represents the dielectric constant of the semiconductor region 12, V represents the built-in voltage between the semiconductor region 12 and the body region 16, q represents the elementary charge amount, and N represents the impurity concentration of the semiconductor region 12. .
As described above, in the semiconductor device 100, the impurity concentration of the body region 16 is adjusted to about 5 × 10 19 cm −3 , and the impurity concentration of the semiconductor region 12 is adjusted to about 1 × 10 16 cm −3 . . Since the impurity concentration of the body region 16 is sufficiently high, a depletion layer generated by the built-in voltage between the semiconductor region 12 and the body region 16 is almost formed in the semiconductor region 12. The thickness W of the depletion layer extending from the interface between the body region 16 and the semiconductor region 12 toward the semiconductor region 12 is determined by the impurity concentration of the semiconductor region 12 and can be expressed by the following formula (2).
W = (2 × ε × V / q) 0.5 × (1 / N) 0.5 (2)
As is clear from the equations (1) and (2), the thickness L of the semiconductor region 12 is equal to or less than the thickness W of the depletion layer generated by the built-in voltage between the semiconductor region 12 and the body region 16. That is, the movement of electrons can be reliably prohibited when the semiconductor device 100 is turned off.

ゲート電極６に電圧を印加していない状態では、ソース電極１０とドレイン電極２４の間に電位差が生じる。また、ボディ領域１６と半導体領域１２の界面から空乏層が伸びる他に、ボディ領域１６とアパーチャ領域２の界面ならびに、ボディ領域１６とドリフト領域２０の界面からも空乏層が伸びる。各々の界面から伸びる空乏層１８ａ，１８ｂがつながると、アパーチャ領域２は空乏化され、アパーチャ領域２よりも紙面上側の構造に電界がかかることを防止できる。空乏層１８ａ，１８ｂがつながらないと、アパーチャ領域２よりも紙面上側の構造に電界がかかってしまう。
半導体装置１００をオフしたときに、ゲート絶縁膜４に高い電圧がかかってしまうと、ゲート絶縁膜４が破壊され、半導体装置１００が破壊されることがある。しかしながら、半導体装置１００では、アパーチャ領域１６に対向する位置にゲート絶縁膜４が形成されていない。空乏層１８ａ，１８ｂがつながらなくても、ゲート絶縁膜４に高い電圧がかかり、ゲート絶縁膜４が破壊されることを防止できる。 In the state where no voltage is applied to the gate electrode 6, a potential difference is generated between the source electrode 10 and the drain electrode 24. In addition to the depletion layer extending from the interface between the body region 16 and the semiconductor region 12, the depletion layer also extends from the interface between the body region 16 and the aperture region 2 and the interface between the body region 16 and the drift region 20. When the depletion layers 18 a and 18 b extending from the respective interfaces are connected, the aperture region 2 is depleted, and an electric field can be prevented from being applied to the structure above the aperture region 2 in the drawing. If the depletion layers 18a and 18b are not connected, an electric field is applied to the structure on the upper side of the drawing than the aperture region 2.
If a high voltage is applied to the gate insulating film 4 when the semiconductor device 100 is turned off, the gate insulating film 4 may be destroyed and the semiconductor device 100 may be destroyed. However, in the semiconductor device 100, the gate insulating film 4 is not formed at a position facing the aperture region 16. Even if the depletion layers 18a and 18b are not connected, a high voltage is applied to the gate insulating film 4 and the gate insulating film 4 can be prevented from being destroyed.

ゲート電極６に正の電圧が印加されている状態では、半導体領域１２に形成されていた空乏層が縮小し、半導体領域１２内を電子が移動できるようになる。すなわち、半導体装置１００がオンする。
ソース領域１４から半導体領域１２を横方向に走行してきた電子は、アパーチャ領域２を流れ、ドリフト領域２０，ドレイン領域２２を経由してドレイン電極２４に流れる。ソース電極１０とドレイン電極２４の間が導通する。すなわち、半導体装置１００は、ノーマリーオフの動作をする縦型のIII族窒化物半導体装置である。 In a state where a positive voltage is applied to the gate electrode 6, the depletion layer formed in the semiconductor region 12 is reduced, and electrons can move in the semiconductor region 12. That is, the semiconductor device 100 is turned on.
Electrons that have traveled laterally from the source region 14 to the semiconductor region 12 flow through the aperture region 2, and flow to the drain electrode 24 through the drift region 20 and the drain region 22. The source electrode 10 and the drain electrode 24 are electrically connected. That is, the semiconductor device 100 is a vertical group III nitride semiconductor device that operates normally off.

上述したように、半導体装置１００では、空乏層１８ａ，１８ｂがつながらなくてもゲート絶縁膜４に高い電圧がかかることを防止できる。すなわち、アパーチャ領域２の幅や、アパーチャ領域２の不純物濃度を高精度に制御しなくても、半導体装置１００をオフしたときにゲート絶縁膜４に高い電圧がかかることを防止できる。空乏層１８ａ，１８ｂを確実につなげるために、アパーチャ領域２の幅を必要以上に狭くしたり、アパーチャ領域２の不純物濃度を必要以上に薄くする必要がない。また、半導体装置１００のオン抵抗を小さくするために、アパーチャ領域２の不純物濃度を積極的に高く設定することもできる。   As described above, in the semiconductor device 100, it is possible to prevent a high voltage from being applied to the gate insulating film 4 even if the depletion layers 18a and 18b are not connected. That is, it is possible to prevent a high voltage from being applied to the gate insulating film 4 when the semiconductor device 100 is turned off without controlling the width of the aperture region 2 and the impurity concentration of the aperture region 2 with high accuracy. In order to securely connect the depletion layers 18a and 18b, it is not necessary to make the width of the aperture region 2 narrower than necessary or make the impurity concentration of the aperture region 2 thinner than necessary. Further, in order to reduce the on-resistance of the semiconductor device 100, the impurity concentration of the aperture region 2 can be positively set high.

（半導体装置１００の製造方法）
次に半導体装置１００の製造方法を説明する。
まず図５に示しているように、窒化ガリウムを主材料とするｎ＋型の半導体基板２２（図１のドレイン領域２２）を用意し、その表面にＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法を利用して、窒化ガリウムを主材料とするｎ型のIII族窒化物半導体層２０（図１のドリフト領域２０）をエピタキシャル成長させる。次いでIII族窒化物半導体層２０の表面にＭＯＣＶＤ法を利用して、窒化ガリウムを主材料とするｐ型のIII族窒化物半導体層１６をエピタキシャル成長させる。
次に、図６に示しているように、III族窒化物半導体層１６の表面にマスク層３０を形成し、マスク層の一部をエッチングして開口を形成する。次に、マスク層３０の開口からIII族窒化物半導体層１６をエッチングし、III族窒化物半導体領層２０に達するトレンチ３２を形成する。III族窒化物半導体層２０をエッチングするために、例えばＲＩＥ（Reactive Ion Etching）等のドライエッチングを利用することができる。この段階で、ボディ領域１６（図１も参照）が完成する。 (Method for Manufacturing Semiconductor Device 100)
Next, a method for manufacturing the semiconductor device 100 will be described.
First, as shown in FIG. 5, an n.sup. + Type semiconductor substrate 22 (drain region 22 in FIG. 1) containing gallium nitride as a main material is prepared, and MOCVD (Metal Organic Chemical Vapor Deposition) method is used on the surface. Then, the n-type group III nitride semiconductor layer 20 (the drift region 20 in FIG. 1) containing gallium nitride as a main material is epitaxially grown. Next, a p-type group III nitride semiconductor layer 16 mainly composed of gallium nitride is epitaxially grown on the surface of the group III nitride semiconductor layer 20 by using MOCVD.
Next, as shown in FIG. 6, a mask layer 30 is formed on the surface of the group III nitride semiconductor layer 16, and a part of the mask layer is etched to form an opening. Next, the group III nitride semiconductor layer 16 is etched from the opening of the mask layer 30 to form a trench 32 reaching the group III nitride semiconductor region 20. In order to etch the group III nitride semiconductor layer 20, for example, dry etching such as RIE (Reactive Ion Etching) can be used. At this stage, the body region 16 (see also FIG. 1) is completed.

次に、図７に示しているように、トレンチ３２（図６を参照）の底面において露出しているIII族窒化物半導体領域２０から、間隙１６ａ（図１を参照）が充填されるまでｎ型の窒化ガリウムを結晶成長させる。すなわち、アパーチャ領域２を完成させる。この段階で、III族窒化物半導体領域２０の表面に、ｐ型のIII族窒化物半導体領域１６（図１のボディ領域１６）と、ｎ型のIII族窒化物半導体領域２（図１のアパーチャ領域２）と、ｐ型のIII族窒化物半導体領域１６の各々のIII族窒化物半導体領域２０，１６，２０が、III族窒化物半導体領域２０の表面に接する状態で順に配置されている積層構造を形成することができる。
その後、一方のIII族窒化物半導体領域１６からIII族窒化物半導体領域２を経て他方のIII族窒化物半導体領域１６に跨る範囲の表面に、ｎ型の窒化ガリウムを結晶成長させる。この段階で、III族窒化物半導体領域１６とIII族窒化物半導体領域２に跨る範囲の表面に形成されているIII族窒化物半導体領域１２（図１のIII族窒化物半導体領域１２）が完成する。本実施例では、トレンチ３２の底面において露出しているIII族窒化物半導体領域２０から、III族窒化物半導体領域１６とIII族窒化物半導体領域２に跨る範囲の表面を覆うまで、連続して窒化ガリウムを結晶成長させる。
III族窒化物半導体領域１６の間隙１６ａを充填しているIII族窒化物半導体領域２と、III族窒化物半導体領域２０から結晶成長する窒化ガリウムの不純物濃度は、III族窒化物半導体領域２０と同一量に調整されている。すなわち、III族窒化物半導体領域２０，２，１２は連続した一つの領域と評価することもできる。しかしながら、図１に示す半導体装置１００と整合させるために、以下の説明では、III族窒化物半導体領域１６，１６の間に結晶成長した窒化ガリウムをIII族窒化物半導体領域２とし、III族窒化物半導体領域１６とIII族窒化物半導体領域２の表面に結晶成長した窒化ガリウムをIII族窒化物半導体領域１２として説明する。 Next, as shown in FIG. 7, from the group III nitride semiconductor region 20 exposed on the bottom surface of the trench 32 (see FIG. 6), n is filled until the gap 16a (see FIG. 1) is filled. Crystal growth of a type of gallium nitride. That is, the aperture area 2 is completed. At this stage, the p-type group III nitride semiconductor region 16 (the body region 16 in FIG. 1) and the n-type group III nitride semiconductor region 2 (the aperture in FIG. 1) are formed on the surface of the group III nitride semiconductor region 20. Layer 2) and each of group III nitride semiconductor regions 20, 16, 20 of p-type group III nitride semiconductor region 16 are sequentially arranged in contact with the surface of group III nitride semiconductor region 20 A structure can be formed.
Thereafter, n-type gallium nitride is crystal-grown on the surface in a range extending from one group III nitride semiconductor region 16 to the other group III nitride semiconductor region 16 through the group III nitride semiconductor region 2. At this stage, the group III nitride semiconductor region 12 (the group III nitride semiconductor region 12 in FIG. 1) formed on the surface of the range spanning the group III nitride semiconductor region 16 and the group III nitride semiconductor region 2 is completed. To do. In the present embodiment, the group III nitride semiconductor region 20 exposed on the bottom surface of the trench 32 is continuously covered until the surface of the range spanning the group III nitride semiconductor region 16 and the group III nitride semiconductor region 2 is covered. Crystal growth of gallium nitride is performed.
The impurity concentration of the group III nitride semiconductor region 2 filling the gap 16 a of the group III nitride semiconductor region 16 and the gallium nitride crystal grown from the group III nitride semiconductor region 20 is the same as that of the group III nitride semiconductor region 20. It is adjusted to the same amount. That is, the group III nitride semiconductor regions 20, 2, and 12 can be evaluated as one continuous region. However, in order to align with the semiconductor device 100 shown in FIG. 1, in the following description, the gallium nitride crystal-grown between the group III nitride semiconductor regions 16 and 16 will be referred to as a group III nitride semiconductor region 2 and group III nitride will be used. The gallium nitride crystal-grown on the surface of the nitride semiconductor region 16 and the group III nitride semiconductor region 2 will be described as a group III nitride semiconductor region 12.

本実施例では、III族窒化物半導体領域２０からｎ型の窒化ガリウムを結晶成長させ、図１に示しているIII族窒化物半導体領域２，１２を完成させている。しかしながら、III族窒化物半導体領域１２の厚み精度を高くするために、III族窒化物半導体領域１６の表面にｎ型の窒化ガリウムを厚く結晶成長させた後、所望する厚さまでエッチングして、III族窒化物半導体領域１２を完成させることもできる。また、III族窒化物半導体領域１６の表面を覆うまでｎ型の窒化ガリウムを結晶成長させた後、III族窒化物半導体領域２，１６の表面が露出するまでｎの窒化ガリウムをエッチングし、その後III族窒化物半導体領域２，１６の表面にｎ型の窒化ガリウムを所望する厚さまで結晶成長させることもできる。
また、ｎ＋型のIII族窒化物半導体領域２２の表面に、ｎ型の窒化ガリウムを厚く形成し、その後、III族窒化物半導体領域１６に対応する部分をエッチングし、エッチングされたｎ型の窒化ガリウムの表面からｐ型のIII族窒化物半導体領域１６を結晶成長させてもよい。 In this embodiment, n-type gallium nitride is crystal-grown from the group III nitride semiconductor region 20 to complete the group III nitride semiconductor regions 2 and 12 shown in FIG. However, in order to increase the thickness accuracy of the group III nitride semiconductor region 12, an n-type gallium nitride is grown on the surface of the group III nitride semiconductor region 16 and then etched to a desired thickness. The group nitride semiconductor region 12 can also be completed. Further, after crystal growth of n-type gallium nitride until the surface of the group III nitride semiconductor region 16 is covered, the n gallium nitride is etched until the surfaces of the group III nitride semiconductor regions 2 and 16 are exposed, and thereafter Crystals of n-type gallium nitride can be grown on the surfaces of the group III nitride semiconductor regions 2 and 16 to a desired thickness.
Further, a thick n-type gallium nitride is formed on the surface of the n + -type group III nitride semiconductor region 22, and then a portion corresponding to the group III nitride semiconductor region 16 is etched to etch the etched n-type n-type. The p-type group III nitride semiconductor region 16 may be crystal-grown from the surface of gallium nitride.

次に、図８に示しているように、III族窒化物半導体領域１２の所定部分にイオン注入を実施してｎ＋のIII族窒化物半導体領域１４を形成する。III族窒化物半導体領域１４は、図７に示しているIII族窒化物半導体領域１２の表面の全域にマスク層（図示省略）を形成し、そのマスク層の所定領域をエッチングしてIII族窒化物半導体領域１２の一部を露出させ、露出したIII族窒化物半導体領域１２にシリコンをイオン注入することによって形成する。その後III族窒化物半導体領域１２の表面に形成したマスク層は除去する。次に、III族窒化物半導体領域１２，１４の表面に絶縁膜４を形成した後、絶縁膜４の表面に電極６を形成する。 Next, as shown in FIG. 8, ion implantation is performed on a predetermined portion of the group III nitride semiconductor region 12 to form an n + group III nitride semiconductor region 14. In the group III nitride semiconductor region 14, a mask layer (not shown) is formed over the entire surface of the group III nitride semiconductor region 12 shown in FIG. 7, and a predetermined region of the mask layer is etched to form a group III nitride. A part of the physical semiconductor region 12 is exposed, and silicon is ion-implanted into the exposed group III nitride semiconductor region 12. Thereafter, the mask layer formed on the surface of group III nitride semiconductor region 12 is removed. Next, after the insulating film 4 is formed on the surfaces of the group III nitride semiconductor regions 12 and 14, the electrode 6 is formed on the surface of the insulating film 4.

次に、図９に示しているように、電極６の表面の所定部分にマスク層（図示省略）を形成し、電極６と絶縁膜１４の一部を除去する。この段階で、III族窒化物半導体領域１６の一部には対向するけれどもIII族窒化物半導体領域２には対向しない位置において、III族窒化物半導体領域１４にゲート絶縁膜１４を介して対向するゲート電極６が完成する。
次に、図１０に示しているように、ゲート絶縁膜４とゲート電極６を覆う電極絶縁膜８を形成し、ソース電極１０（図１を参照）を形成する部分の電極絶縁膜８をエッチングして除去する。その後、ソース電極１０とドレイン電極２４を形成することによって、図１に示している半導体装置１０を得ることができる。 Next, as shown in FIG. 9, a mask layer (not shown) is formed on a predetermined portion of the surface of the electrode 6, and a part of the electrode 6 and the insulating film 14 is removed. At this stage, the group III nitride semiconductor region 14 is opposed to the group III nitride semiconductor region 14 via the gate insulating film 14 at a position facing a part of the group III nitride semiconductor region 16 but not facing the group III nitride semiconductor region 2. The gate electrode 6 is completed.
Next, as shown in FIG. 10, an electrode insulating film 8 covering the gate insulating film 4 and the gate electrode 6 is formed, and the portion of the electrode insulating film 8 where the source electrode 10 (see FIG. 1) is formed is etched. And remove. Thereafter, by forming the source electrode 10 and the drain electrode 24, the semiconductor device 10 shown in FIG. 1 can be obtained.

本実施例では、ｐ型の不純物を含んでいるIII族窒化物半導体領域１６とｎ型の不純物を含んでいるIII族窒化物半導体領域２に跨る範囲の表面に、ｎ型の不純物を含んでいるIII族窒化物半導体領域１２が形成されている。III族窒化物半導体領域１２は、バンドギャップの狭いｎ型又はｉ型のIII族窒化物半導体層と、バンドギャップの広いｎ型又はｉ型のIII族窒化物半導体層の積層で構成することもできる。
その場合、バンドギャップの狭いIII族窒化物半導体層とバンドギャップの広いIII族窒化物半導体層の間に形成される２次元電子ガス領域を電子が移動することができるため、半導体装置のオン抵抗をより小さくすることができる。 In the present embodiment, the surface of the range spanning the group III nitride semiconductor region 16 containing the p-type impurity and the group III nitride semiconductor region 2 containing the n-type impurity contains the n-type impurity. A group III nitride semiconductor region 12 is formed. The group III nitride semiconductor region 12 may be formed of a stack of an n-type or i-type group III nitride semiconductor layer having a narrow band gap and an n-type or i-type group III nitride semiconductor layer having a wide band gap. it can.
In that case, since electrons can move in a two-dimensional electron gas region formed between the group III nitride semiconductor layer with a narrow band gap and the group III nitride semiconductor layer with a wide band gap, the on-resistance of the semiconductor device Can be made smaller.

（第２実施例）
図２を参照して半導体装置２００について説明する。半導体装置２００は、半導体装置１００の変形例であり、半導体装置１００と同じ構成については、半導体装置１００と同じ参照番号を付すことによって説明を省略する。
第４のIII族窒化物半導体領域２１２の厚みが、第３のIII族窒化物半導体領域２に近い部分（領域２１２ｂ）では厚く、III族窒化物半導体領域２から遠い部分（領域２１２ａ）では薄く形成されている。本実施例では、III族窒化物半導体領域２の表面に形成されているIII族窒化物半導体領域２１２の厚みも厚く形成されている。
ゲート絶縁膜２０４は、III族窒化物半導体領域２１２の領域２１２ｂの部分と、III族窒化物半導体領域２１２の領域２１２ａの部分に跨る範囲に形成されている。また、ゲート絶縁膜２０４は、III族窒化物半導体領域２１２とIII族窒化物半導体領域１４に跨る範囲に形成されている。ゲート絶縁膜２０４の表面にゲート電極２０６が形成されており、ゲート電極２０６とソース電極２１０は、電極絶縁膜２０８によって電気的に分離されている。 (Second embodiment)
The semiconductor device 200 will be described with reference to FIG. The semiconductor device 200 is a modification of the semiconductor device 100, and the same components as those of the semiconductor device 100 are denoted by the same reference numerals as those of the semiconductor device 100, and the description thereof is omitted.
The thickness of the fourth group III nitride semiconductor region 212 is thick in the portion close to the third group III nitride semiconductor region 2 (region 212b), and thin in the portion far from the group III nitride semiconductor region 2 (region 212a). Is formed. In this embodiment, the thickness of the group III nitride semiconductor region 212 formed on the surface of the group III nitride semiconductor region 2 is also increased.
The gate insulating film 204 is formed in a range spanning the region 212 b of the group III nitride semiconductor region 212 and the region 212 a of the group III nitride semiconductor region 212. Further, the gate insulating film 204 is formed in a range straddling the group III nitride semiconductor region 212 and the group III nitride semiconductor region 14. A gate electrode 206 is formed on the surface of the gate insulating film 204, and the gate electrode 206 and the source electrode 210 are electrically separated by the electrode insulating film 208.

半導体装置２００によって解決される課題について説明する。
図１に示している半導体装置１００では、半導体領域１２において、裏面にボディ領域１６が形成され、表面にゲート絶縁膜４が形成されていない領域（図１のＡの範囲）や、ボディ領域１６とアパーチャ領域２の境界近傍に形成されている半導体領域１２では、ゲート電極６に電圧を印加しても空乏層が消失しにくい。すなわち、半導体装置１００のオン抵抗が大きくなってしまうという問題がある。半導体装置１００のオン抵抗を小さくする必要がある。 A problem solved by the semiconductor device 200 will be described.
In the semiconductor device 100 shown in FIG. 1, in the semiconductor region 12, the body region 16 is formed on the back surface and the gate insulating film 4 is not formed on the front surface (range A in FIG. 1). In the semiconductor region 12 formed in the vicinity of the boundary between the aperture region 2 and the gate electrode 6, a depletion layer is unlikely to disappear even when a voltage is applied to the gate electrode 6. That is, there is a problem that the on-resistance of the semiconductor device 100 is increased. It is necessary to reduce the on-resistance of the semiconductor device 100.

半導体装置２００では、半導体領域１２の最も薄い部分の厚みＬが、上記式（１）を満足するように調節されている。すなわち、ゲート電極２０６に電圧を印加していない状態では領域２１２ａに空乏層が形成され、半導体装置２００を確実にオフすることができる。また、半導体装置２００がオフすると、ソース電極２１０とドレイン電極２４の間の電位差に応じて、ボディ領域１６から半導体領域２１２の領域２１２ｂに向けても空乏層が伸びる。
半導体装置２００をオンすると、ゲート電極２０６に対向する範囲の半導体領域２１２に形成されていた空乏層が消失する。しかしながら、ボディ領域１６とアパーチャ領域２の境界近傍の半導体領域２１２の厚みが厚いため、半導体装置２００をオンしたときに空乏層が完全に消失しなくても、半導体領域２１２の領域２１２ｂの表層部分を電子が走行することができる。そのため、半導体装置２００のオン抵抗を小さくすることができる。 In the semiconductor device 200, the thickness L of the thinnest portion of the semiconductor region 12 is adjusted so as to satisfy the above formula (1). That is, when no voltage is applied to the gate electrode 206, a depletion layer is formed in the region 212a, and the semiconductor device 200 can be reliably turned off. In addition, when the semiconductor device 200 is turned off, a depletion layer extends from the body region 16 toward the region 212b of the semiconductor region 212 in accordance with the potential difference between the source electrode 210 and the drain electrode 24.
When the semiconductor device 200 is turned on, the depletion layer formed in the semiconductor region 212 in the range facing the gate electrode 206 disappears. However, since the semiconductor region 212 near the boundary between the body region 16 and the aperture region 2 is thick, even if the depletion layer does not completely disappear when the semiconductor device 200 is turned on, the surface layer portion of the region 212b of the semiconductor region 212 The electron can travel. Therefore, the on-resistance of the semiconductor device 200 can be reduced.

半導体装置２００の製造方法について説明する。なお、図５から図６の工程までの工程は、半導体装置１００の製造方法と同じため説明を省略する。
図１１に示しているように、トレンチ３２の底面において露出しているIII族窒化物半導体領域２０から、III族窒化物半導体領域１６の表面を覆うまでｎ型の窒化ガリウムを結晶成長させる。III族窒化物半導体領域１６の表面に成長させるIII族窒化物半導体領域２１２の厚みは、領域２１２ｂの厚さ（図２を参照）と等しい。
次に、図１２に示しているように、領域２１２ｂに対応する部分にマスク層３８を形成した後、半導体領域２１２を所定深さまでエッチングして、領域２１２ａと領域２１２ｂを形成する。その後の工程は、図８から図１０までの工程と実質的に同じため、説明を省略する。
なお、本実施例では、III族窒化物半導体領域１６の表面に成長させるIII族窒化物半導体領域２１２の厚みは、領域２１２ｂの厚さと等しい。しかしながら、ｎ型の窒化ガリウムを領域２１２ｂの厚さよりも厚く結晶成長させた後、領域２１２ｂの厚さまでエッチングしてもよい。あるいは、III族窒化物半導体領域１６の表面を覆うまでｎ型の窒化ガリウムを結晶成長させた後、半導体領域１６の表面が露出するまでｎ型の窒化ガリウムをエッチングし、その後III族窒化物半導体領域２，１６の表面に、ｎ型の窒化ガリウムを所望する厚さ（領域２１２ｂの厚さ）まで結晶成長させることもできる。 A method for manufacturing the semiconductor device 200 will be described. 5 to 6 are the same as the manufacturing method of the semiconductor device 100, and thus description thereof is omitted.
As shown in FIG. 11, n-type gallium nitride is grown from the group III nitride semiconductor region 20 exposed at the bottom surface of the trench 32 until the surface of the group III nitride semiconductor region 16 is covered. The thickness of the group III nitride semiconductor region 212 grown on the surface of the group III nitride semiconductor region 16 is equal to the thickness of the region 212b (see FIG. 2).
Next, as shown in FIG. 12, after the mask layer 38 is formed in a portion corresponding to the region 212b, the semiconductor region 212 is etched to a predetermined depth to form a region 212a and a region 212b. The subsequent steps are substantially the same as the steps from FIG. 8 to FIG.
In this embodiment, the thickness of the group III nitride semiconductor region 212 grown on the surface of the group III nitride semiconductor region 16 is equal to the thickness of the region 212b. However, the n-type gallium nitride may be grown to a thickness larger than the thickness of the region 212b and then etched to the thickness of the region 212b. Alternatively, after crystal growth of n-type gallium nitride until the surface of the group III nitride semiconductor region 16 is covered, the n-type gallium nitride is etched until the surface of the semiconductor region 16 is exposed, and then the group III nitride semiconductor Crystals of n-type gallium nitride can be grown on the surfaces of the regions 2 and 16 to a desired thickness (the thickness of the region 212b).

（第３実施例）
図３を参照して半導体装置３００について説明する。半導体装置３００は、半導体装置１００の変形例であり、半導体装置１００と同じ構成については、半導体装置１００と同じ参照番号を付すことによって説明を省略する。
第２のIII族窒化物半導体領域３１６の厚みが、第３のIII族窒化物半導体領域３０２に近い部分（領域３１６ｂ）では薄く、第３のIII族窒化物半導体領域３０２に遠い部分（領域３１６ａ）では厚く形成されている。第４のIII族窒化物半導体領域３１２の表面は平坦になっている。結果として、III族窒化物半導体領域３１２の厚みが、III族窒化物半導体領域３０２に近い部分（領域３１２ｂ）では厚く、III族窒化物半導体領域３０２に遠い部分（領域３１２ａ）では薄く形成されている。
半導体装置３００でも、半導体装置３００をオンしたときに、III族窒化物半導体領域３０２とIII族窒化物半導体領域３１２の境界近傍に形成されているIII族窒化物半導体領域３１２の空乏層が完全に消失しなくても、半導体領域３１２の領域３１２ｂの表層部分を電子が走行することができる。半導体装置３００のオン抵抗を小さくすることができる。また、半導体領域３１２の表面が平坦になっているため、平坦な表面にゲート絶縁膜４，ゲート電極６を形成することができる。半導体装置２００と比較して、ゲート絶縁膜４，ゲート電極６の製造工程を簡単化することができる。
なお、本実施例では、半導体領域３１２の表面が平坦になっているが、半導体装置２００のように、III族窒化物半導体領域３０２に近い部分では、III族窒化物半導体領域３１２を上に凸に形成することもできる。半導体装置３００のオン抵抗をより小さくすることができる。 (Third embodiment)
The semiconductor device 300 will be described with reference to FIG. The semiconductor device 300 is a modification of the semiconductor device 100, and the same components as those of the semiconductor device 100 are denoted by the same reference numerals as those of the semiconductor device 100, and the description thereof is omitted.
The thickness of the second group III nitride semiconductor region 316 is thin at the portion close to the third group III nitride semiconductor region 302 (region 316b), and the portion far from the third group III nitride semiconductor region 302 (region 316a). ) Is formed thick. The surface of the fourth group III nitride semiconductor region 312 is flat. As a result, the thickness of the group III nitride semiconductor region 312 is thick in the portion close to the group III nitride semiconductor region 302 (region 312b) and thin in the portion far from the group III nitride semiconductor region 302 (region 312a). Yes.
Also in the semiconductor device 300, when the semiconductor device 300 is turned on, the depletion layer of the group III nitride semiconductor region 312 formed near the boundary between the group III nitride semiconductor region 302 and the group III nitride semiconductor region 312 is completely removed. Even if it does not disappear, electrons can travel on the surface layer portion of the region 312 b of the semiconductor region 312. The on-resistance of the semiconductor device 300 can be reduced. Further, since the surface of the semiconductor region 312 is flat, the gate insulating film 4 and the gate electrode 6 can be formed on the flat surface. Compared with the semiconductor device 200, the manufacturing process of the gate insulating film 4 and the gate electrode 6 can be simplified.
In this embodiment, the surface of the semiconductor region 312 is flat, but the group III nitride semiconductor region 312 protrudes upward in a portion close to the group III nitride semiconductor region 302 as in the semiconductor device 200. It can also be formed. The on-resistance of the semiconductor device 300 can be further reduced.

半導体装置３００の製造方法について説明する。図５の工程は、半導体装置１００の製造方法と同じため説明を省略する。
図１３に示しているように、半導体領域３１６にトレンチ３４を形成する。トレンチ３４を形成する範囲は、III族窒化物半導体領域３０２と、III族窒化物半導体領域３１６の領域３１６ｂに対応する範囲（図３を参照）とし、トレンチ３４の深さは、III族窒化物半導体領域１６の残部が領域３１６ａになるようにする。次いで、トレンチ３４の底部から半導体領域２０に達するトレンチ３６を形成する。トレンチ３６を形成する範囲は、半導体領域３０２（図３を参照）に対応する範囲とする。
なお、トレンチ３４とトレンチ３６を形成する順番は、どちらが先でもよい。その後の工程は、図７から図１０で説明した工程と実質的に同じため説明を省略する。 A method for manufacturing the semiconductor device 300 will be described. Since the process of FIG. 5 is the same as the manufacturing method of the semiconductor device 100, description thereof is omitted.
As shown in FIG. 13, a trench 34 is formed in the semiconductor region 316. The range in which the trench 34 is formed is a range corresponding to the group III nitride semiconductor region 302 and the region 316b of the group III nitride semiconductor region 316 (see FIG. 3), and the depth of the trench 34 is the group III nitride. The remainder of the semiconductor region 16 is made to be a region 316a. Next, a trench 36 reaching the semiconductor region 20 from the bottom of the trench 34 is formed. The range in which the trench 36 is formed is a range corresponding to the semiconductor region 302 (see FIG. 3).
Note that the order of forming the trench 34 and the trench 36 may be either. Subsequent steps are substantially the same as those described with reference to FIGS.

（第４実施例）
図４を参照して半導体装置４００について説明する。半導体装置４００は半導体装置１００の変形例であり、半導体装置１００と同じ構成については、半導体装置１００と同じ参照番号を付すことによって説明を省略する。
半導体装置４００では、第４のIII族窒化物半導体領域１２の表面の全域にゲート絶縁膜４０４が形成されている。すなわち、ゲート電極４０６は、III族窒化物半導体領域１２の全域にゲート絶縁膜４０４を介して対向している。ゲート絶縁膜４０４は、III族窒化物半導体領域１６のうちのIII族窒化物半導体領域２に近い範囲とIII族窒化物半導体領域２に対向する範囲（領域４０４ｂ）では厚く、III族窒化物半導体領域１６のうちのIII族窒化物半導体領域２から遠い範囲に対向する範囲（領域４０４ａ）では薄く形成されている。ゲート絶縁膜４０４の表面にゲート電極４０６が形成されており、ゲート電極４０６とソース電極４１０は、電極絶縁膜４０８によって電気的に分離されている。
半導体装置４００では、半導体装置４００をオフしたときに、半導体領域１６，１６から半導体領域２に向けて伸びる空乏層がつながらない場合、ゲート絶縁膜４０４の領域４０４ｂに電界がかかる。しかしながら、領域４０４ｂが厚く形成されているため、ゲート絶縁膜４０４の領域４０４ｂに高い電圧がかかってもゲート絶縁膜４０４が破壊されることを防止できる。半導体装置４００でも、隣接するIII族窒化物半導体領域１６の距離（間隙の幅）や、III族窒化物半導体領域２の不純物濃度を高精度に制御しなくても、半導体装置４００をオフしたときに、ゲート絶縁膜４０４が破壊されることを防止できる。半導体装置４００のオン抵抗を大きくすることなく、ゲート絶縁膜４０４が破壊されることを防止できる。
本実施例の半導体装置４００では、第４のIII族窒化物半導体領域１２の厚みが、その全域に亘って等しい。しかしながら、半導体装置２００，３００のように、第４のIII族窒化物半導体領域１２の厚みが、第３のIII族窒化物半導体領域２に近い部分では厚く、第３のIII族窒化物半導体領域に遠い部分では薄くすることもできる。その場合の作用効果については、上記した内容と同じため省略する。 (Fourth embodiment)
The semiconductor device 400 will be described with reference to FIG. The semiconductor device 400 is a modification of the semiconductor device 100, and the same components as those of the semiconductor device 100 are denoted by the same reference numerals as those of the semiconductor device 100, and the description thereof is omitted.
In the semiconductor device 400, a gate insulating film 404 is formed over the entire surface of the fourth group III nitride semiconductor region 12. In other words, the gate electrode 406 faces the entire group III nitride semiconductor region 12 with the gate insulating film 404 interposed therebetween. The gate insulating film 404 is thick in the range close to the group III nitride semiconductor region 2 in the group III nitride semiconductor region 16 and in the range facing the group III nitride semiconductor region 2 (region 404b), and the group III nitride semiconductor. In the region 16, the region (region 404 a) facing the region far from the group III nitride semiconductor region 2 is thin. A gate electrode 406 is formed on the surface of the gate insulating film 404, and the gate electrode 406 and the source electrode 410 are electrically separated by the electrode insulating film 408.
In the semiconductor device 400, when the depletion layer extending from the semiconductor regions 16 and 16 toward the semiconductor region 2 is not connected when the semiconductor device 400 is turned off, an electric field is applied to the region 404 b of the gate insulating film 404. However, since the region 404b is formed thick, the gate insulating film 404 can be prevented from being broken even when a high voltage is applied to the region 404b of the gate insulating film 404. Even in the semiconductor device 400, when the distance between the adjacent group III nitride semiconductor regions 16 (gap width) and the impurity concentration of the group III nitride semiconductor region 2 are not accurately controlled, the semiconductor device 400 is turned off. In addition, the gate insulating film 404 can be prevented from being broken. The gate insulating film 404 can be prevented from being destroyed without increasing the on-resistance of the semiconductor device 400.
In the semiconductor device 400 of this example, the thickness of the fourth group III nitride semiconductor region 12 is the same over the entire area. However, like the semiconductor devices 200 and 300, the thickness of the fourth group III nitride semiconductor region 12 is thicker in the portion close to the third group III nitride semiconductor region 2, and the third group III nitride semiconductor region. It is also possible to make it thinner in areas farther away. Since the effect in that case is the same as described above, the description thereof is omitted.

半導体装置４００の製造方法について説明する。図５から図７までの工程は、半導体装置１００と同じため説明を省略する。
半導体領域１２の所定部分にイオン注入をしてｎ＋型のIII族窒化物半導体領域１４を形成した後、III族窒化物半導体領域１２とIII族窒化物半導体領域１４の表面に絶縁膜を形成する。その後、その絶縁膜のゲート絶縁膜４０４ａに対応する部分をエッチングする。次いで、その絶縁膜の表面に電極４０６を形成（図示省略）し、その後、その絶縁膜と電極４０６とエッチングしてゲート絶縁膜４０４とゲート電極４０６を完成させる。その後の工程は、実施例１の図１０以降と同じため説明を省略する。 A method for manufacturing the semiconductor device 400 will be described. The steps from FIG. 5 to FIG.
After ion implantation is performed on a predetermined portion of the semiconductor region 12 to form an n + -type group III nitride semiconductor region 14, an insulating film is formed on the surfaces of the group III nitride semiconductor region 12 and the group III nitride semiconductor region 14. To do. Thereafter, a portion of the insulating film corresponding to the gate insulating film 404a is etched. Next, an electrode 406 is formed on the surface of the insulating film (not shown), and then the insulating film and the electrode 406 are etched to complete the gate insulating film 404 and the gate electrode 406. Subsequent steps are the same as those in FIG.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時の請求項に記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数の目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

第１実施例の半導体装置の断面図を示す。Sectional drawing of the semiconductor device of 1st Example is shown. 第２実施例の半導体装置の断面図を示す。Sectional drawing of the semiconductor device of 2nd Example is shown. 第３実施例の半導体装置の断面図を示す。Sectional drawing of the semiconductor device of 3rd Example is shown. 第４実施例の半導体装置の断面図を示す。Sectional drawing of the semiconductor device of 4th Example is shown. 第１実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 1st Example is shown. 第１実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 1st Example is shown. 第１実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 1st Example is shown. 第１実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 1st Example is shown. 第１実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 1st Example is shown. 第１実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 1st Example is shown. 第２実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 2nd Example is shown. 第２実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 2nd Example is shown. 第３実施例の半導体装置の製造過程を示す。The manufacturing process of the semiconductor device of 3rd Example is shown. 従来の半導体装置の断面図を示す。Sectional drawing of the conventional semiconductor device is shown.

符号の説明Explanation of symbols

２，３０２：第２のIII族窒化物半導体領域（アパーチャ領域）
４，２０４，４０４：ゲート絶縁膜
６，２０６，４０６：ゲート電極
１０，２１０，４１０：ソース電極
１２，２１２，３１２：第４のIII族窒化物半導体領域
１４：第５のIII族窒化物半導体領域（ソース領域）
１６，３１６：第２のIII族窒化物半導体領域（アパーチャ領域）
２０：第１のIII族窒化物半導体領域（ドリフト領域）
２４：ドレイン電極
１００，２００，３００，４００：半導体装置 2,302: Second group III nitride semiconductor region (aperture region)
4, 204, 404: gate insulating films 6, 206, 406: gate electrodes 10, 210, 410: source electrodes 12, 212, 312: fourth group III nitride semiconductor region 14: fifth group III nitride semiconductor Area (source area)
16, 316: Second group III nitride semiconductor region (aperture region)
20: First group III nitride semiconductor region (drift region)
24: Drain electrode 100, 200, 300, 400: Semiconductor device

Claims (9)

ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域と、
第１のIII族窒化物半導体領域の表面において間隙を残して不連続に形成されているとともに、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、
第２のIII族窒化物半導体領域の前記間隙において第１のIII族窒化物半導体領域の表面に形成されており、前記間隙を充填しているとともに、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、
第２のIII族窒化物半導体領域と第３のIII族窒化物半導体領域に跨る範囲の前記両領域の表面に形成されているとともに、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域と、
第２のIII族窒化物半導体領域の一部には対向するけれども第３のIII族窒化物半導体領域には対向しない位置において、第４のIII族窒化物半導体領域にゲート絶縁膜を介して対向しているゲート電極と、
を備えていることを特徴とする半導体装置。 a first group III nitride semiconductor region containing an n-type impurity;
A second group III nitride semiconductor region which is formed discontinuously on the surface of the first group III nitride semiconductor region leaving a gap, and which contains a p-type impurity;
A third group III nitride semiconductor region is formed on the surface of the first group III nitride semiconductor region in the gap of the second group III nitride semiconductor region, fills the gap, and contains an n-type impurity. A group III nitride semiconductor region;
A fourth group III nitride formed on the surfaces of both the regions of the second group III nitride semiconductor region and the third group III nitride semiconductor region and containing an n-type impurity A semiconductor region;
Opposing to the fourth group III nitride semiconductor region via the gate insulating film at a position facing a part of the second group III nitride semiconductor region but not facing the third group III nitride semiconductor region A gate electrode,
A semiconductor device comprising: 半導体装置の断面を観察したときに、
第４のIII族窒化物半導体領域の厚みが、第３のIII族窒化物半導体領域に近い部分では厚く、第３のIII族窒化物半導体領域から遠い部分では薄く形成されていることを特徴とする請求項１の半導体装置。 When observing a cross section of a semiconductor device,
The thickness of the fourth group III nitride semiconductor region is formed thicker at a portion close to the third group III nitride semiconductor region, and thinner at a portion far from the third group III nitride semiconductor region. The semiconductor device according to claim 1. 半導体装置の断面を観察したときに、
第２のIII族窒化物半導体領域の厚みが、第３のIII族窒化物半導体領域に近い部分では薄く、第３のIII族窒化物半導体領域から遠い部分では厚く形成されていることを特徴とする請求項２の半導体装置。 When observing a cross section of a semiconductor device,
The thickness of the second group III nitride semiconductor region is thin at a portion close to the third group III nitride semiconductor region and thick at a portion far from the third group III nitride semiconductor region. The semiconductor device according to claim 2. ゲート絶縁膜が、第４のIII族窒化物半導体領域が厚く形成されている部分と、第４のIII族窒化物半導体領域が薄く形成されている部分に跨る範囲に形成されていることを特徴とする請求項２又は３の半導体装置。   The gate insulating film is formed in a range straddling a portion where the fourth group III nitride semiconductor region is formed thick and a portion where the fourth group III nitride semiconductor region is formed thin. A semiconductor device according to claim 2 or 3. ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域と、
第１のIII族窒化物半導体領域の表面において間隙を残して不連続に形成されているとともに、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、
第２のIII族窒化物半導体領域の前記間隙において第１のIII族窒化物半導体領域の表面に形成されており、前記間隙を充填しているとともに、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、
第２のIII族窒化物半導体領域と第３のIII族窒化物半導体領域に跨る範囲の前記両領域の表面に形成されているとともに、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域と、
第４のIII族窒化物半導体領域にゲート絶縁膜を介して対向するゲート電極を備えており、
そのゲート絶縁膜が、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域に近い範囲と第３のIII族窒化物半導体領域に対向する範囲では厚く、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域から遠い範囲に対向する範囲では薄く形成されていることを特徴とする半導体装置。 a first group III nitride semiconductor region containing an n-type impurity;
A second group III nitride semiconductor region which is formed discontinuously on the surface of the first group III nitride semiconductor region leaving a gap, and which contains a p-type impurity;
A third group III nitride semiconductor region is formed on the surface of the first group III nitride semiconductor region in the gap of the second group III nitride semiconductor region, fills the gap, and contains an n-type impurity. A group III nitride semiconductor region;
A fourth group III nitride formed on the surfaces of both the regions of the second group III nitride semiconductor region and the third group III nitride semiconductor region and containing an n-type impurity A semiconductor region;
A gate electrode facing the fourth group III nitride semiconductor region via a gate insulating film;
The gate insulating film is thick in a range close to the third group III nitride semiconductor region in the second group III nitride semiconductor region and in a range facing the third group III nitride semiconductor region, A semiconductor device characterized in that the semiconductor device is thinly formed in a range facing a range far from a third group III nitride semiconductor region in the group III nitride semiconductor region. 第４のIII族窒化物半導体領域の誘電率εとし、第４のIII族窒化物半導体領域の不純物濃度をＮとし、第２のIII族窒化物半導体領域と第４のIII族窒化物半導体領域のビルトイン電圧をＶとし、電荷素量をｑとしたときに、第４のIII族窒化物半導体領域の最も薄い部分の厚みＬが、下記式（１）、
Ｌ≦（２×ε×Ｖ／ｑ）０．５×（１／Ｎ）０．５ （１）
を満足することを特徴とする請求項１から５のいずれかの半導体装置。 Let the dielectric constant ε of the fourth group III nitride semiconductor region be N, the impurity concentration of the fourth group III nitride semiconductor region be N, the second group III nitride semiconductor region, and the fourth group III nitride semiconductor region When the built-in voltage of V is V and the elementary charge is q, the thickness L of the thinnest portion of the fourth group III nitride semiconductor region is expressed by the following formula (1),
L ≦ (2 × ε × V / q) 0.5 × (1 / N) 0.5 (1)
The semiconductor device according to claim 1, wherein: 第４のIII族窒化物半導体領域が、バンドギャップの狭いIII族窒化物半導体層と、バンドギャップの広いIII族窒化物半導体層の積層で構成されていることを特徴とする請求項１から５のいずれかの半導体装置。   6. The fourth group III nitride semiconductor region is composed of a stack of a group III nitride semiconductor layer having a narrow band gap and a group III nitride semiconductor layer having a wide band gap. Any of the semiconductor devices. ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域の表面に、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域の各々のIII族窒化物半導体領域が、第１のIII族窒化物半導体領域の表面に接する状態で順に配置されている積層構造を形成する工程と、
一方の第２のIII族窒化物半導体領域から第３のIII族窒化物半導体領域を経て他方の第２のIII族窒化物半導体領域に跨る範囲の表面に、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域を結晶成長させる工程と、
第２のIII族窒化物半導体領域の一部には対向するけれども第３のIII族窒化物半導体領域には対向しない位置において、第４のIII族窒化物半導体領域にゲート絶縁膜を介して対向しているゲート電極を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 A second group III nitride semiconductor region containing p-type impurities and a third group containing n-type impurities on the surface of the first group III nitride semiconductor region containing n-type impurities. Each of the group III nitride semiconductor regions of the group III nitride semiconductor region and the second group III nitride semiconductor region containing the p-type impurity is in contact with the surface of the first group III nitride semiconductor region. Forming a laminated structure sequentially arranged in a state;
The n-type impurity is included in the surface in a range extending from one second group III nitride semiconductor region through the third group III nitride semiconductor region to the other second group III nitride semiconductor region. Crystal growth of group III nitride semiconductor region 4;
Opposing to the fourth group III nitride semiconductor region via the gate insulating film at a position facing a part of the second group III nitride semiconductor region but not facing the third group III nitride semiconductor region Forming a gate electrode, and
A method for manufacturing a semiconductor device, comprising: ｎ型の不純物を含んでいる第１のIII族窒化物半導体領域の表面に、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域と、ｎ型の不純物を含んでいる第３のIII族窒化物半導体領域と、ｐ型の不純物を含んでいる第２のIII族窒化物半導体領域の各々のIII族窒化物半導体領域が、第１のIII族窒化物半導体領域の表面に接する状態で順に配置されている積層構造を形成する工程と、
一方の第２のIII族窒化物半導体領域から第３のIII族窒化物半導体領域を経て他方の第２のIII族窒化物半導体領域に跨る範囲の表面に、ｎ型の不純物を含んでいる第４のIII族窒化物半導体領域を結晶成長させる工程と、
第４のIII族窒化物半導体領域の表面にゲート絶縁膜を形成する工程と、
ゲート絶縁膜の表面にゲート電極を形成する工程を有しており、
ゲート絶縁膜の形成工程では、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域から近い範囲と第３のIII族窒化物半導体領域に対向する範囲では厚く形成し、第２のIII族窒化物半導体領域のうちの第３のIII族窒化物半導体領域から遠い範囲に対向する範囲では薄く形成することを特徴とする半導体装置の製造方法。 A second group III nitride semiconductor region containing p-type impurities and a third group containing n-type impurities on the surface of the first group III nitride semiconductor region containing n-type impurities. Each of the group III nitride semiconductor regions of the group III nitride semiconductor region and the second group III nitride semiconductor region containing the p-type impurity is in contact with the surface of the first group III nitride semiconductor region. Forming a laminated structure sequentially arranged in a state;
The n-type impurity is included in the surface in a range extending from one second group III nitride semiconductor region through the third group III nitride semiconductor region to the other second group III nitride semiconductor region. Crystal growth of group III nitride semiconductor region 4;
Forming a gate insulating film on the surface of the fourth group III nitride semiconductor region;
A step of forming a gate electrode on the surface of the gate insulating film;
In the gate insulating film formation step, the second group III nitride semiconductor region is formed thicker in the range close to the third group III nitride semiconductor region and in the range facing the third group III nitride semiconductor region. A method of manufacturing a semiconductor device, comprising: forming a thin film in a range opposite to a range far from the third group III nitride semiconductor region of the second group III nitride semiconductor region.
JP2007103053A 2007-04-10 2007-04-10 Group iii nitride semiconductor device, and manufacturing method thereof Pending JP2008262982A (en)

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