JP2009038200A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relax electric field concentration on a corner part of a body region. <P>SOLUTION: A vertical semiconductor device 100 has an n-type semiconductor region 5, a body region 8, a channel region 14, a first connection region 26, a second connection region 12, a gate electrode 18, and trench electrodes 22 and 24. The n-type semiconductor region 5 is electrically connected to one polarity of a supply voltage. The body region 8 is provided on the n-type semiconductor region 5 while leaving a gap L. The channel region 14 is provided on the body region. The first connection region 26 electrically connects the n-type semiconductor region 5 and channel region 14 to each other. The second connection region 12 electrically connects the channel region 14 and the other polarity of the supply voltage to each other. The gate electrode 18 is opposed to the body region 8 with the channel region 14 interposed therebetween. The trench electrodes 22 and 24 are provided in the gap L, and has an insulating film 24 and a conductor 22 covered with the insulating film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a vertical semiconductor device using a group III nitride semiconductor.

  FIG. 20 is a cross-sectional view of a semiconductor device 500 using gallium nitride disclosed in Patent Document 1. The semiconductor device 500 includes an n-type semiconductor region 505, a p-type body region 508 provided on the n-type semiconductor region 505 leaving a gap L, and an n-type channel region provided on the body region 508. 514, an n-type aperture region 526 (an example of a first connection region) provided in the gap L and electrically connecting the n-type semiconductor region 505 and the channel region 514, and the channel region 514 In addition, an n-type source region 512 (an example of a second connection region) facing the aperture region 526 and a gate electrode 518 facing the body region 508 with a channel region 514 interposed therebetween are provided. The n-type semiconductor region 505 has a drain region 504 and a drift region 506 and is electrically connected to the drain electrode 502. The source region 512 and the body region 508 are electrically connected to the source electrode 510.

  In the semiconductor device 500, when a positive voltage is not applied to the gate electrode 518, the depletion layer extending from the body region 508 reaches the gate insulating film 516 beyond the channel region 514, and the channel region 514 is depleted. Thereby, the semiconductor device 500 is turned off. When a positive voltage is applied to the gate electrode 518, the depletion layer formed in the channel region 514 is reduced, and a channel is formed in the channel region 514. Electrons supplied from the source region 512 flow to the drain electrode 502 through the channel region 514, the aperture region 526, and the n-type semiconductor region 505. Thereby, the semiconductor device 500 is turned on.

JP 2004-260140 A

FIG. 21 shows a simulation result of equipotential line distribution near the body region 508 when the semiconductor device 500 is off. As shown in FIG. 21, it can be seen that when the semiconductor device 500 is off, the electric field is concentrated on the corner portion 508 a of the body region 508. When the semiconductor device 500 is off, the potentials of the body region 508 and the gate electrode 518 are equal. Therefore, as shown in FIG. 21, equipotential lines are greatly bent at the corner portion 508a of the body region 508, and the electric field is concentrated at the corner portion 508a.
An object of the present invention is to provide a technique for alleviating electric field concentration in a corner portion of a body region.

  The semiconductor device disclosed in this specification is characterized in that a trench electrode is provided in a gap between adjacent body regions. The trench electrode has an insulating film and a conductor covered with the insulating film. A predetermined voltage is applied to the conductor of the trench electrode so that the equipotential lines are not greatly bent at the corners of the body region. For example, when the semiconductor device is turned off, a voltage is applied to the conductor of the trench electrode such that the conductor of the trench electrode and the body region have substantially the same potential. When the potential of the conductor of the trench electrode is fixed to such a potential when the semiconductor device is turned off, the equipotential line is prevented from being greatly bent at the corner portion of the body region. Electric field concentration at the corner is alleviated.

In other words, the semiconductor device disclosed in this specification is a vertical semiconductor device that is electrically connected to one polarity of a power supply voltage and includes an n-type impurity. A channel region provided on the body region, a body region of a group III nitride semiconductor provided with a gap on the n-type semiconductor region and containing a p-type impurity, a channel region provided on the body region, A first connection region provided in the gap and electrically connecting the n-type semiconductor region and the channel region, and facing the first connection region via the channel region, the channel region and the power supply voltage A second connection region for electrically connecting the other polarity of the gate electrode, a gate electrode facing the body region via the channel region, and provided between the first connection region and the second connection region, Provided in the gap, Enmaku and is characterized by comprising a trench electrode and a having the coated conductor with an insulating film.
Here, the gate electrode may be in direct contact with the channel region or indirectly in contact with the channel region through a gate insulating film.

In the semiconductor device disclosed in this specification, the conductors of the gate electrode and the trench electrode are preferably electrically connected.
When the conductors of the gate electrode and the trench electrode are electrically connected, a voltage that varies in the same cycle as the gate electrode is applied to the conductor of the trench electrode. When an off voltage is applied to the gate electrode, the off voltage is also applied to the conductor of the trench electrode, and when an on voltage is applied to the gate electrode, the on voltage is also applied to the conductor of the trench electrode.
At the timing when the semiconductor device is turned off, an off voltage is applied to the conductor of the trench electrode. Since the conductor of the trench electrode to which the off-voltage is applied is fixed at substantially the same potential as the potential of the body region, it is possible to prevent the equipotential lines from being greatly bent at the corners of the body region. The electric field concentration at the corners is reduced.
Furthermore, according to the semiconductor device described above, an on-voltage is applied to the conductor of the trench electrode at the timing when the semiconductor device is turned on. When an ON voltage is applied to the conductor of the trench electrode, the depletion layer extending from the body region into the first connection region can be reduced. Therefore, when the semiconductor device is on, a wide current path can be secured in the first connection region, and the electrical resistance of the first connection region can be reduced. Thereby, the on-resistance of the semiconductor device can be reduced.

In the semiconductor device disclosed in this specification, the conductors of the gate electrode and the trench electrode are preferably configured integrally.
According to the above semiconductor device, the structure of the semiconductor device can be simplified as compared with the case where the gate electrode and the trench electrode are provided separately.

In the semiconductor device disclosed in this specification, the trench electrode preferably reaches the n-type semiconductor region beyond the gap.
In the semiconductor device described above, the trench electrode is provided at a position deeper than the corner portion of the body region. For this reason, the electric field concentration at the corner of the body region can be remarkably suppressed.

The semiconductor device disclosed in the present specification further includes a p-type semiconductor region of a group III nitride semiconductor that faces the insulating film on the bottom surface of the trench electrode and contains p-type impurities. preferable.
According to the semiconductor device described above, the depletion layer can be extended from the p-type semiconductor region to the periphery when the semiconductor device is off. For this reason, the electric field concentration in the insulating film on the bottom surface of the trench electrode can be reduced.

In the semiconductor device disclosed in this specification, the p-type semiconductor region is preferably in contact with the insulating film on the bottom surface of the trench electrode.
According to the above semiconductor device, electric field concentration in the insulating film on the bottom surface of the trench electrode can be remarkably reduced.

In the semiconductor device disclosed in this specification, the channel region may have a heterojunction of a group III nitride semiconductor. The heterojunction extends in a direction connecting the first connection region and the second connection region.
In the semiconductor device disclosed in this specification, the first connection region may also include a group III nitride semiconductor heterojunction. The heterojunction is characterized by extending along the direction connecting the n-type semiconductor region and the channel region.
Since the heterojunction induces a two-dimensional electron gas layer, it is effective in reducing the on-resistance. When a heterojunction is provided in the channel region, a channel resistance can be reduced and a semiconductor device with low on-resistance can be realized. When the heterojunction is provided in the first connection region, the resistance in the first connection region can be reduced and a semiconductor device with low on-resistance can be realized.

  According to the technique disclosed in this specification, the electric field concentration at the corner portion of the body region can be reduced when the semiconductor device is turned off. Therefore, when the technology disclosed in this specification is used, a semiconductor device with high breakdown voltage can be realized.

The main features of the examples are listed.
(Feature 1) The n-type semiconductor region has a region where n-type impurities are contained at a low concentration and a region where n-type impurities are contained at a high concentration. Is electrically connected to one polarity of the power supply voltage.
(Feature 2) In the semiconductor device 300, an impurity diffusion preventing film is formed between the body region and the channel region.
(Feature 3) In the semiconductor device 300, a contact electrode having a resistance lower than that of the source electrode is formed between the body region and the source electrode.

(First embodiment)
FIG. 1 schematically shows a vertical sectional view of a vertical group III nitride semiconductor device 100. The cross-sectional view of FIG. 1 shows a unit structure of the semiconductor device 100, and this unit structure is repeatedly formed in the left-right direction on the paper. In addition, the scale of the structure of each part is changed suitably for clarification of drawing.
The semiconductor device 100 includes a drain electrode 2, an n ⁺ -type drain region 4 provided on the drain electrode 2, and an n-type drift region 6 provided on the drain region 4. The drain region 4 and the drift region 6 are formed of a semiconductor whose main material is gallium nitride (GaN). The drain electrode 2 is electrically connected to the drain region 4. The drain electrode 2 is connected to a high voltage (one polarity of power supply voltage) side terminal D. In the semiconductor device 100 of this embodiment, the impurity concentration of the drain region 4 is adjusted to about 3 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the drift region 6 is adjusted to about 1 × 10 ¹⁶ cm ⁻³ . . In this embodiment, the drain region 4 and the drift region 6 may be collectively referred to as an n-type semiconductor region 5.
The semiconductor device 100 further includes a p ⁺ type body region 8 provided with a gap L left on the surface of the drift region 6. The body region 8 is formed of a semiconductor whose main material is gallium nitride. The body region 8 is divided into a plurality by the gap L. In other words, a plurality of body regions 8 are formed on the surface of the drift region 6, and the adjacent body regions 8 are separated by an aperture region 26 (an example of a first connection region) described later. When the semiconductor device 100 is viewed in plan, each body region 8 extends in the depth direction of the drawing and is formed in a stripe shape. In the semiconductor device 100 of the present embodiment, the impurity concentration of the body region 8 is adjusted to approximately 1 × 10 ¹⁹ cm ⁻³ .

The semiconductor device 100 further includes an n-type aperture region 26 (an example of a first connection region) provided in the gap L. The aperture region 26 is formed of a semiconductor whose main material is gallium nitride. A channel region 14 and an n-type semiconductor region 5 described later are electrically connected by the aperture region 26. In the semiconductor device 100 of the present embodiment, the impurity concentration of the aperture region is adjusted to approximately 1 × 10 ¹⁶ cm ⁻³ .

The semiconductor device 100 further includes an n-type channel region 14 provided on the body region 8 and an n ⁺ -type source region 12 (an example of a second connection region). In the present embodiment, the source region 12 is provided on the body region 8. The channel region 14 and the source region 12 are formed of a semiconductor whose main material is gallium nitride. The source region 12 is formed at a position facing the aperture region 26 via the channel region 14 and is in contact with the end of the channel region 14. In the semiconductor device 100 of this embodiment, the impurity concentration of the channel region 14 is adjusted to approximately 1 × 10 ¹⁶ cm ⁻³ , and the impurity concentration of the source region 12 is adjusted to approximately 1 × 10 ²⁰ cm ⁻³ . .
The source electrode 10 is connected to the source region 12. Further, a low voltage (the other polarity of the power supply voltage) side terminal S is connected to the source electrode 10. The source electrode 10 is also electrically connected to the body region 8.
As described above, the channel region 14, the aperture region 26, and the drift region 6 are n ⁻ -type semiconductors mainly composed of gallium nitride, and their impurities are adjusted to the same amount. That is, the channel region 14, the aperture region 26, and the drift region 6 can be regarded as one continuous region.

The semiconductor device 100 further includes a gate electrode 18 whose main material is nickel (Ni). The gate electrode 18 faces the body region 8 with the channel region 14 in between. More precisely, the gate electrode 18 faces the body region 8 through a part of the source region 12 and the channel region 14. Further, the gate electrode 18 is not in direct contact with the channel region 14. The gate electrode 18 faces the channel region 14 through the gate insulating film 16. In the semiconductor device 100 of this embodiment, the gate electrode 18 faces the body region 8 with a part of the source region 12 and the channel region 14 interposed therebetween. However, the gate electrode 18 only needs to face the body electrode 8 between the aperture region 26 and the source region 12. Further, the gate electrode 18 and the source electrode 10 are electrically insulated.
The semiconductor device 100 further includes a trench electrode 22 (an example of a conductor of the trench electrode) mainly made of polycrystalline silicon. The trench electrode 22 is provided in the gap L. The trench electrode 22 is opposed to the aperture region 26 through an insulating film 24 (an example of an insulating film of the trench electrode). The trench electrode 22 and the gate electrode 18 are integrally formed and are electrically connected. The insulating film 24 and the gate insulating film 16 are integrally formed. A voltage that varies in the same cycle as the gate electrode 18 is applied to the trench electrode 22. That is, the trench electrode 22 can be regarded as a part of the gate electrode 18, and the insulating film 24 can be regarded as a part of the gate insulating film 16. In the semiconductor device 100 of the present embodiment, the trench electrode 22 is provided in the gap L. However, the trench electrode 22 may reach the drift region 6 beyond the gap L as in the semiconductor device 200 shown in FIG.

The operation of the semiconductor device 100 will be described.
An n-type channel region 14 is formed on the surface of the p-type body region 8. When no voltage is applied to the gate electrode 18, the depletion layer extending from the body region 8 reaches the gate insulating film 16 beyond the channel region 14, and the channel region 14 is depleted. Since the channel region 14 is depleted, electrons cannot travel in the channel region 14. That is, the semiconductor device 100 is off. When no voltage is applied to the gate electrode 18, a potential difference is generated between the source electrode 10 and the drain electrode 2, and an electric field is generated in the semiconductor device 100.

FIG. 3 shows a simulation result of equipotential line distribution in the vicinity of the body region 8 when the semiconductor device 100 is off.
As described above, in the semiconductor device 100, the trench electrode 22 is provided in the gap L. Therefore, even if the semiconductor device 100 is turned off, the equipotential lines are not greatly bent at the corner portion 8a of the body region 8 as shown in FIG. When the semiconductor device 100 is off, the electric field is prevented from concentrating on the corner portion 8a. This phenomenon is remarkable when compared with the equipotential distribution (see FIG. 21) of the electric field generated in the semiconductor device 500 when the conventional semiconductor device 500 is turned off.
In the semiconductor device 100, when the semiconductor device 100 is turned off, it is possible to prevent the electric field from concentrating on a portion where the electric field tends to concentrate (the corner portion 8a of the body region 8). In the semiconductor device 100, by providing the trench electrode 22 in the gap L, a semiconductor device having a high breakdown voltage is realized.

In a state where a positive voltage is applied to the gate electrode 18, the depletion layer formed in the channel region 14 is reduced, and electrons can move in the channel region 14. That is, the semiconductor device 100 is turned on.
Electrons that have traveled laterally in the channel region 14 from the source region 12 flow through the aperture region 26, pass through the drift region 6 and the drain region 4, and flow to the drain electrode 2. The source electrode 10 and the drain electrode 2 are electrically connected. The semiconductor device 100 is a vertical semiconductor device that operates normally off.

  As described above, a depletion layer extending from the body region 8 is formed in the channel region 14 when no voltage is applied to the gate electrode 18. The depletion layer does not only extend from the body region 8 toward the channel region 14. The depletion layer is formed to extend from the body region 8 toward the aperture region 26 and the drift region 6. In the semiconductor device 100 of the present embodiment, the trench electrode 22 is provided in the gap L. As described above, the trench electrode 22 and the gate electrode 18 are electrically connected. When a positive voltage is applied to the gate electrode 18, a positive voltage is also applied to the trench electrode 22, and the depletion layer formed in the aperture region 26 is reduced. Therefore, when the semiconductor device 100 is turned on, a region where the depletion layer is not formed in the aperture region 26 can be widened. That is, a region where electrons can pass in the aperture region 26 can be widened. As a result, the movement resistance of electrons in the aperture region 26 can be reduced. In the semiconductor device 100, the gate electrode 18 and the trench electrode 22 are electrically connected to realize a semiconductor device having a smaller on-resistance.

(Method for Manufacturing Semiconductor Device 100)
A method for manufacturing the semiconductor device 100 will be described with reference to FIGS.
First, as shown in FIG. 4, an n ⁺ -type semiconductor substrate 4 containing gallium nitride as a main material is prepared. The thickness of the semiconductor substrate 4 is approximately 200 μm. Next, as shown in FIG. 5, an n-type semiconductor region 6 containing gallium nitride as a main material is epitaxially grown on the surface of the semiconductor substrate 4 using MOCVD (Metal Organic Chemical Vapor Deposition). The thickness of the semiconductor region 6 is approximately 10 μm. At this stage, the n-type semiconductor region 5 is completed.
Next, as shown in FIG. 6, a p ⁺ type semiconductor layer 8 containing gallium nitride as a main material is epitaxially grown using MOCVD. Here, magnesium (Mg) is used as an impurity of the semiconductor layer 8. The thickness of the semiconductor layer 8 is approximately 0.5 μm. Next, a mask layer 28 having an opening 28 a is formed on the surface of the semiconductor layer 8. Thereafter, the semiconductor layer 8 is etched from the opening 28 a of the mask layer 28 until the drift region 6 is exposed, thereby forming the trench 21. At this stage, a plurality of body regions 8 are formed, and gaps L are formed between adjacent body regions 8. Note that silicon oxide (SiO ₂ ) or the like can be used as the mask layer 28. The semiconductor layer 8 can be etched using dry etching such as ICP (Inductive Coupled Plasma).
In FIG. 6, the semiconductor layer 8 is etched until the surface of the drift region 6 is exposed. However, the semiconductor layer 8 may be etched through the semiconductor layer 8. In the step of forming the trench electrode 22 described later, the trench electrode 22 can be formed up to the drift region 6. The semiconductor device 200 can be manufactured. Alternatively, the drift region 6 may be etched deeper than a desired depth through the semiconductor layer 8, and then an n-type semiconductor mainly composed of gallium nitride may be selectively grown to a desired depth. Adjacent body regions 8 can be reliably separated. Further, the length of the trench electrode 22 can be formed with high accuracy.

Next, as shown in FIG. 7, after removing the mask layer 28, the n-type semiconductor regions 26 and 14 containing gallium nitride as a main material are grown using the MOCVD method. The thickness of the semiconductor regions 26 and 14 is approximately 125 nm. Here, a semiconductor formed in the gap L between adjacent body regions 8 is referred to as a semiconductor region (aperture region) 26, and a semiconductor formed on the body region 8 is referred to as a semiconductor region 14.
Next, as shown in FIG. 8, a silicon oxide mask layer 30 is formed on the surfaces of the semiconductor regions 26 and 14. Next, a part of the mask layer 30 formed on the semiconductor region 14 is removed, and an opening 30a is formed. Thereafter, silicon is ion-implanted from the exposed surface of the semiconductor region 14. An n ⁺ type semiconductor region 12a is formed. Here, silicon is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 65 eV. The arrows in the figure indicate the range in which silicon is ion-implanted. Thereafter, the mask layer 30 is removed by etching, a mask layer (not shown) is formed again on the surfaces of the semiconductor regions 14 and 12a, and annealed at 1100 ° C. for 20 minutes in an inert gas (for example, nitrogen gas) atmosphere. . By annealing in an inert gas atmosphere, impurities (silicon) in the semiconductor region 12a are activated. At this stage, the channel region 14 (see FIG. 1) is completed.
In advance of the silicon semiconductor region 14 to the ion implantation, a dose of nitrogen in the semiconductor layer 14 1 × ¹⁰ 15 ^{cm -2,} it may be implanted at an acceleration voltage 35 eV. Nitrogen released from the crystal structure of the semiconductor region 14 when part of the mask layer 30 is removed by etching can be compensated for in the semiconductor region 14.

Next, as shown in FIG. 9, a mask layer 32 having openings 32a is formed. Thereafter, the exposed semiconductor region 12a (see FIG. 8) is removed using an ICP method. At this stage, the source region 12 (see FIG. 1) is completed.
Next, as shown in FIG. 10, after the mask layer 32 (see FIG. 9) is removed, insulating films 16 and 24 of silicon oxide are formed using a CVD method. The thickness of the insulating films 16 and 24 is 100 nm. The insulating films 16 and 24 are HTO (High Temperature Oxide) films. Next, the insulating film 24 is filled with polycrystalline silicon, and nickel is formed on the surface of the polycrystalline silicon and the insulating film 16. Although not shown, the trench electrode 22 and the gate electrode 18 are completed. Polycrystalline silicon may also be formed on the surface of the insulating film 16, and nickel may be formed on the surface of the polycrystalline silicon. Thereafter, a part of the insulating film 16 is removed by etching, and a part of the source region 12 and a part of the body region 8 are exposed. The gate insulating film 16 is completed. Thereafter, the source electrode 10 connected to both the source region 12 and the body region 8 is vapor-deposited, and the drain electrode 2 is vapor-deposited on the back surface of the drain region 4. The source electrode 10 is laminated with titanium (Ti) and aluminum (Al). The drain electrode 22 is also laminated with titanium and aluminum. Thereafter, annealing is performed at 500 ° C. for 2 minutes in an inert gas atmosphere. By annealing, the contact resistance of the source electrode 10, the source region 12, and the body region 8 can be reduced. The contact resistance between the drain electrode 2 and the drain region 4 can be reduced. Thereby, the semiconductor device 100 shown in FIG. 1 is completed.

In the above manufacturing method, the selective growth method is not used in the process of forming the semiconductor regions 14 and 26 (see FIG. 7). Therefore, the manufacturing process of the semiconductor device 100 can be simplified.
Note that another manufacturing method may be provided for the semiconductor device 100. After the step shown in FIG. 6, instead of the step of FIG. 7, as shown in FIG. 11, a semiconductor region 34 mainly composed of n-type gallium nitride is grown from the exposed drift region 6. . Here, crystal growth is continued until the semiconductor layer 34 covers the surface of the body region 8. The thickness of the semiconductor region 34 on the body region 8 is adjusted to be the same (125 nm) as the thickness of the channel region 14 shown in FIG.
Next, as shown in FIG. 12, a mask layer 36 having an opening 36a is formed on the surface of the semiconductor region 34 (see FIG. 11). The exposed semiconductor region 34 is etched from the surface to form a trench 38. Here, the semiconductor region 34 remaining in the gap L is the semiconductor region 26, and the semiconductor region 34 on the body region 8 is the semiconductor region 14. Subsequent steps are the same as those shown in FIG.

Still another manufacturing method can be provided for the semiconductor device 100. After the step shown in FIG. 4, as shown in FIG. 13, an n-type semiconductor region 40 containing gallium nitride as a main material is epitaxially grown on the surface of the n ⁺ -type semiconductor substrate 4. The thickness of the semiconductor region 40 is approximately 10.5 μm.
Next, as shown in FIG. 14, a mask layer 42 having an opening 42 a is formed on the surface of the semiconductor region 40. Thereafter, the semiconductor layer 40 is etched from the exposed surface of the semiconductor region 40 to form a trench 44.
Next, as shown in FIG. 15, a p-type body region 8 containing gallium nitride as a main material is formed in the trench 44. Thereafter, an n-type semiconductor layer 44 mainly composed of gallium nitride is formed on the surface of the protruding portion 40 a of the semiconductor region 40 and the surface of the body region 8. The structure of the protrusion 40a and the semiconductor layer 44 is the same as that of the semiconductor layer 34 in FIG. Moreover, the structure except the protrusion part 40 of the semiconductor region 40 is equal to the drift region 6 in FIG. Subsequent steps are the same as the steps after FIG.

(Second embodiment)
FIG. 16 schematically shows a longitudinal sectional view of the group III nitride semiconductor device 300. The semiconductor device 300 is a modification of the semiconductor device 100. The description of the substantially same configuration as that of the semiconductor device 100 may be omitted by giving the same reference number or the same reference number to the last two digits.
In the semiconductor device 300, a channel region 314 and a source region 312 are formed on the body region 8 via the impurity diffusion prevention film 46. The main material of the impurity diffusion preventing film 46 is aluminum nitride (AlN), and its thickness is adjusted to 10 nm. The impurity diffusion preventing film 46 suppresses diffusion of impurities (magnesium) contained in the body region 8 into the channel region 314 and the source region 312.

The channel region 314 includes an n-type semiconductor region 45 of the gallium nitride as the main material, the n-type semiconductor region 47 of gallium aluminum nitride _(Al 0.3 _{Ga 0.7} N) as the main material . The band gap of the semiconductor region 47 is larger than the band gap of the semiconductor region 45. That is, the semiconductor region 45 and the semiconductor region 47 form a heterojunction. The impurity concentration of both the semiconductor region 45 and the semiconductor region 47 is adjusted to approximately 1 × 10 ¹⁶ cm ⁻³ . The thickness of the semiconductor region 45 is 100 nm, and the thickness of the semiconductor region 47 is 25 nm.

In the semiconductor device 300, the aperture region 326 includes an n-type semiconductor region 49 whose main material is gallium nitride and an n-type semiconductor region 48 whose main material is gallium nitride / aluminum. The band gap of the semiconductor region 48 is larger than the band gap of the semiconductor region 49. The semiconductor region 49 and the semiconductor region 48 form a heterojunction. The impurity concentration of both the semiconductor region 49 and the semiconductor region 48 is adjusted to approximately 1 × 10 ¹⁶ cm ⁻³ . The thickness of the semiconductor region 49 is 100 nm, and the thickness of the semiconductor region 48 is 25 nm. The semiconductor region 45, the semiconductor region 49, and the semiconductor region (drift region) 6 can also be regarded as one continuous region. In addition, the semiconductor region 47 and the semiconductor region 48 can be regarded as one continuous region.

  In the semiconductor device 300, a contact electrode 41 mainly made of nickel is formed between the body region 8 and the source electrode 310. The resistance of the contact electrode 41 is smaller than the resistance of the source electrode (laminated body of titanium and aluminum) 310. The contact electrode 41 can reduce the contact resistance between the source electrode 310 and the body region 8. The potential of the body region 8 can be further stabilized. The thickness of the depletion layer extending from the body region 8 toward the channel region 314 and the aperture region 326 can be further stabilized.

An operation of the semiconductor device 300 will be described.
In a state where no voltage is applied to the gate electrode 18, a depletion layer is formed from the body region 8 toward the channel region 314 and the aperture region 326. The depletion layer extends to the heterojunction surface of the semiconductor region 45 and the semiconductor region 47 and the heterojunction surface of the semiconductor region 49 and the semiconductor region 48. The energy level of the conduction band of the heterojunction surface exists above the Fermi level, and the two-dimensional electron gas layer cannot exist on the heterojunction surface. For this reason, in a state where no voltage is applied to the gate electrode 18, the traveling of electrons is stopped, and the semiconductor device 300 is turned off.
In a state where a positive voltage is applied to the gate electrode 18, the depletion layer extending from the body region 8 toward the channel region 314 is reduced. Since the gate electrode 18 and the trench electrode 22 are electrically connected, the depletion layer extending from the body region 8 toward the aperture region 326 is reduced when a positive voltage is applied to the gate electrode 18. . A two-dimensional electron gas layer is formed on the heterojunction surface of the semiconductor region 45 and the semiconductor region 47 and on the heterojunction surface of the semiconductor region 49 and the semiconductor region 48. The energy level of the conduction band of the two-dimensional electron gas layer exists below the Fermi level, and a state is created in which the two-dimensional electron gas layer exists in the potential well of the heterojunction surface. As a result, electrons run in the two-dimensional electron gas layer, and the semiconductor device 300 is turned on.

As described above, in the semiconductor device 300, electrons move in the two-dimensional electron gas layer formed on the heterojunction surface. The mobility of electrons in the two-dimensional electron gas layer is approximately 1000 to 1500 cm ² / Vs. The mobility of electrons in the channel region 14 of the semiconductor device 100 is approximately 200 to 500 cm ² / Vs. That is, since the semiconductor device 300 has the above characteristics, a semiconductor device having a channel resistance smaller than that of the semiconductor device 100 (about 1/3 to 1/5) can be realized.

A method for manufacturing the semiconductor device 300 will be described. Here, only a configuration different from that of the semiconductor device 100 will be described.
After the step shown in FIG. 5, the p ⁺ type semiconductor layer 8 containing gallium nitride as a main material is epitaxially grown using MOCVD. Thereafter, an impurity diffusion preventing film 46 can be formed by growing a layer mainly composed of aluminum nitride on the surface of the semiconductor layer 8 using MOCVD.
After the step shown in FIG. 6, the mask layer 28 is removed, and gallium nitride is grown on the exposed surface of the drift region 6, the side wall of the body region 8, and the surface of the body region 8 using the MOCVD method. Region 49 and semiconductor region 45 can be formed. Thereafter, the semiconductor region 48 and the semiconductor region 47 can be formed by growing gallium aluminum nitride on the surfaces of the semiconductor regions 49 and 45 using the MOCVD method.
After the step shown in FIG. 9, the contact electrode 41 can be formed by forming a nickel film on a part of the body region 8 using a lift-off method.

(Third embodiment)
FIG. 17 schematically shows a longitudinal sectional view of the group III nitride semiconductor device 400. The semiconductor device 400 is a modification of the semiconductor device 100. About the structure substantially the same as the semiconductor device 100, description may be abbreviate | omitted by attaching | subjecting the same reference number.
In the semiconductor device 400, a p-type semiconductor region 50 facing the insulating film 24 on the bottom surface of the trench electrode 22 is formed. The p-type semiconductor region 50 is in contact with the insulating film 24. The p-type semiconductor region 50 is a p ⁺ -type semiconductor region mainly composed of gallium nitride.
In the semiconductor device 400 of this example, the p-type semiconductor region 50 is formed in the gap L. However, the p-type semiconductor region 50 may be formed in the drift region 6. Further, the p-type semiconductor region 50 may not be in contact with the insulating film 24. In that case, the p-type semiconductor region 50 faces the insulating film 24 on the bottom surface of the trench electrode 22 through a part of the aperture region 26.

A problem solved by the semiconductor device 400 will be described.
In the semiconductor device 100 shown in FIG. 1, a depletion layer is formed from the body region 8 toward the aperture region 26 when no voltage is applied to the gate electrode 18. At this time, the semiconductor device 100 is off, and a voltage is also applied to the insulating film 24. When a high voltage is applied to the insulating film 24, the insulating film 24 may be broken. When the width of the gap L is reduced, a depletion layer extending from the adjacent body regions 8 and 8 toward the aperture region 26 is easily connected. However, when the width of the gap L is reduced, the current path in the aperture region 26 is narrowed, and the on-resistance of the semiconductor device 100 is increased. A semiconductor device having a structure in which a high voltage is hardly applied to the insulating film 24 regardless of the width of the gap L is required.

Here, the relationship between the width of the gap L in the semiconductor device 100 and the voltage applied to the bottom of the insulating film 24 will be described. FIG. 18 shows the relationship between the voltage applied between the source electrode 10 and the drain electrode 2 (hereinafter referred to as source-drain voltage) and the voltage applied to the bottom of the insulating film 24 when the semiconductor device 100 is turned off. The horizontal axis of the graph represents the source-drain voltage (unit: V), and the vertical axis of the graph represents the voltage applied to the bottom of the insulating film 24 (unit: V). A curve 52 indicates a voltage when the width of the gap L is 1 μm, a curve 54 indicates a voltage when the width of the gap L is 2 μm, and a curve 56 indicates a voltage when the width of the gap L is 4 μm. The curve 58 shows the voltage when the width of the gap L is 20 μm.
As is apparent from FIG. 18, when the width of the gap L is reduced, the voltage applied to the insulating film 24 is reduced. Conversely, when the width of the gap L is increased, the voltage applied to the insulating film 24 increases.
As shown by the curve 58, when the width of the gap L is 20 μm, when the source-drain voltage reaches 2000 V, a voltage of about 100 V is applied to the bottom of the insulating film 24. The electric field strength applied to the bottom of the insulating film 24 reaches approximately 10 MV / cm, and the insulating film 24 may be destroyed. As indicated by the curve 52, when the width of the gap L is 1 μm, when the source-drain voltage reaches 2000 V, a voltage of about 60 V is applied to the bottom of the insulating film 24. The electric field strength applied to the bottom of the insulating film 24 reaches approximately 6 MV / cm. Also in this case, the insulating film 24 may be destroyed.

  In the semiconductor device 300, the p-type semiconductor region 50 is formed at the bottom of the trench electrode 22. When the semiconductor device 300 is turned off, not only a depletion layer is formed from the body region 8 toward the surrounding n-type semiconductor regions (channel region 14, aperture region 26, drift region 6), but also from the p-type semiconductor region 50. Also, a depletion layer is formed toward the surrounding n-type semiconductor region. Even if the width of the gap L is increased, it is possible to prevent a high voltage from being applied to the gate insulating film 24.

FIG. 19 shows the relationship between the source-drain voltage when the semiconductor device 300 is turned off and the voltage applied to the bottom of the insulating film 24. The horizontal axis of the graph represents the source-drain voltage (unit: V), and the vertical axis of the graph represents the voltage applied to the insulating film 24 (unit: V). A curve 60 indicates a voltage when the width of the gap L is 1 μm, a curve 62 indicates a voltage when the width of the gap L is 2 μm, and a curve 64 indicates a voltage when the width of the gap L is 4 μm. The curve 66 shows the voltage when the width of the gap L is 20 μm.
As apparent from FIG. 19, in the semiconductor device 300, the voltage applied to the insulating film 24 is substantially equal regardless of the width of the gap L. As indicated by curve 66, when the width of the gap L is 20 μm, when the source-drain voltage reaches 2000 V, a voltage of about 30 V is applied to the bottom of the insulating film 24. Even if the width of the gap L of the semiconductor device 100 is 1 μm, the voltage applied to the insulating film 24 is suppressed to about one half. At this time, the electric field strength applied to the bottom of the insulating film 24 is approximately 3 MV / cm, and the insulating film 24 can be prevented from being broken.
Since the semiconductor device 300 includes the p-type semiconductor region 50, the insulating film 24 can be prevented from being destroyed when the semiconductor device 300 is turned off. That is, by having the p-type semiconductor region 50, the semiconductor device 300 having a high breakdown voltage is realized without reducing the on-resistance.

  A method for manufacturing the semiconductor device 300 will be described. As described above, the semiconductor device 300 is obtained by adding the p-type semiconductor region 50 to the structure of the semiconductor device 100. Here, only a method for forming the p-type semiconductor region 50 will be described. First, after the step of FIG. 7, the semiconductor region 26 where the p-type semiconductor region 50 is to be formed is removed by etching. Thereafter, a p-type semiconductor layer containing gallium nitride as a main material is formed in the etched portion. Subsequent steps are the same as those shown in FIG. A p-type semiconductor region 50 opposed to the bottom of the trench electrode 22 through the insulating film 24 can be formed.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, there are four characteristics of the semiconductor device of the second embodiment, that is, that the channel region forms a heterojunction, the aperture region forms a heterojunction, and between the body region and the channel region. The formation of the impurity diffusion preventing film and the formation of the contact electrode between the body region and the source electrode can be independently employed. Any of the above features can be independently added to the semiconductor device of the first embodiment.
Any or all of the four features of the semiconductor device of the second embodiment may be added to the semiconductor device of the third embodiment.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

Sectional drawing of the semiconductor device of 1st Example is shown. Sectional drawing of the modification of the semiconductor device of 1st Example is shown. The equipotential part which arises in the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the semiconductor device of 1st Example is shown. The manufacturing process of the other manufacturing method of the semiconductor device of 1st Example is shown. The manufacturing process of the other manufacturing method of the semiconductor device of 1st Example is shown. The manufacturing process of the other manufacturing method of the semiconductor device of 1st Example is shown. The manufacturing process of the other manufacturing method of the semiconductor device of 1st Example is shown. The manufacturing process of the other manufacturing method of the semiconductor device of 1st Example is shown. Sectional drawing of the semiconductor device of 2nd Example is shown. Sectional drawing of the semiconductor device of 3rd Example is shown. The relationship between the source-drain voltage of the semiconductor device of 1st Example and the voltage concerning an insulating film is shown. The relationship between the source-drain voltage of the semiconductor device of 3rd Example and the voltage concerning an insulating film is shown. Sectional drawing of the conventional semiconductor device is shown. 2 shows an equipotential portion generated in a conventional semiconductor device.

Explanation of symbols

2, 502: drain electrode 4, 504: drain region 6, 506: drift region 8, 508: body region 10, 310, 510: source electrode 12, 312, 512: source region 14, 314, 514: channel region 18, 518: gate electrode 22: trench electrode 26, 326, 526: aperture region 50: p-type semiconductor region 100, 200, 300, 400, 500: semiconductor device

Claims (8)

A vertical semiconductor device,
An n-type semiconductor region of a group III nitride semiconductor electrically connected to one polarity of the power supply voltage and containing an n-type impurity;
a body region of a group III nitride semiconductor provided with a gap on the n-type semiconductor region and containing a p-type impurity;
A channel region provided on the body region;
A first connection region provided in the gap and electrically connecting the n-type semiconductor region and the channel region;
A second connection region facing the first connection region via the channel region and electrically connecting the other polarity of the channel region and the power supply voltage;
A gate electrode facing the body region via the channel region and provided between the first connection region and the second connection region;
A semiconductor device comprising: a trench electrode provided in the gap and having an insulating film and a conductor covered with the insulating film.   2. The semiconductor device according to claim 1, wherein the conductors of the gate electrode and the trench electrode are electrically connected.   The semiconductor device according to claim 2, wherein the conductors of the gate electrode and the trench electrode are integrally formed.   The semiconductor device according to claim 1, wherein the trench electrode reaches the n-type semiconductor region beyond the gap.   5. The semiconductor device according to claim 1, further comprising a p-type semiconductor region of a group III nitride semiconductor facing the insulating film on the bottom surface of the trench electrode and containing a p-type impurity. 2. A semiconductor device according to item 1.   The semiconductor device according to claim 5, wherein the p-type semiconductor region is in contact with an insulating film on a bottom surface of the trench electrode. The channel region has a heterojunction of a group III nitride semiconductor;
The semiconductor device according to claim 1, wherein the heterojunction extends along a direction connecting the first connection region and the second connection region. The first connection region has a heterojunction of a group III nitride semiconductor;
The semiconductor device according to claim 1, wherein the heterojunction extends along a direction connecting the n-type semiconductor region and the channel region.

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