JP2009267029A - Nitride semiconductor element, and method for manufacturing nitride semiconductor element - Google Patents

Nitride semiconductor element, and method for manufacturing nitride semiconductor element Download PDF

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JP2009267029A
JP2009267029A JP2008113956A JP2008113956A JP2009267029A JP 2009267029 A JP2009267029 A JP 2009267029A JP 2008113956 A JP2008113956 A JP 2008113956A JP 2008113956 A JP2008113956 A JP 2008113956A JP 2009267029 A JP2009267029 A JP 2009267029A
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nitride semiconductor
formed
type gan
insulating film
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Hirotaka Otake
Yoshinori Tanaka
浩隆 大嶽
良宜 田中
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Rohm Co Ltd
ローム株式会社
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<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor element capable of reducing resistance by bringing out the characteristics of a group III nitride semiconductor independently of a sort of a gate insulating film and to provide a method for manufacturing the nitride semiconductor element. <P>SOLUTION: In the nitride semiconductor element, there is formed a nitride semiconductor laminate structure 1 including an n<SP>-</SP>type GaN drift layer 6, a p-type GaN channel layer 3 and an n<SP>+</SP>type GaN source layer 4 and having a trench 7 formed across these layers 6, 3, 4. A gate insulating film 11 is formed on an inside wall 8 and an inner bottom wall 9 of the nitride semiconductor laminate structure 1, facing the trench 7. A gate electrode 12 opposed at least to the n<SP>-</SP>type GaN drift layer 6 and the p-type GaN channel layer 3 through the gate insulating film 11 is formed on the gate insulating film 11. A p-type GaN layer 10 opposed to the gate electrode 12 through the gate insulating film 11 is formed on the inner bottom wall 9 of the n<SP>-</SP>type GaN drift layer 6. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a nitride semiconductor device using a group III nitride semiconductor and a method for manufacturing the same.

Conventionally, power devices using silicon semiconductors have been used for power amplifier circuits, power supply circuits, motor drive circuits, and the like.
However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of nitride semiconductor devices having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and low on-resistance has been studied.

In the case of manufacturing a transistor using a silicon semiconductor, it is necessary to increase the thickness of the drift layer electrically connected to the drain electrode in order to ensure a necessary breakdown voltage. For example, in order to design a high breakdown voltage transistor having a breakdown voltage of 600 V, it is necessary that the impurity concentration of the drift layer is about 7.5 × 10 14 cm −3 and the thickness of the drift layer is about 26 μm. However, in this case, the resistance value of the drift layer is extremely large.

On the other hand, when a group III nitride semiconductor is used, the drift layer thickness is reduced by setting the impurity concentration of the drift layer to about 8.5 × 10 16 cm −3 and the thickness of the drift layer to about 1.9 μm. While being able to make it small, the impurity concentration can be made large. As a result, the resistance value of the drift layer can be reduced.
JP 2003-163354 A

By constructing a drift layer using a group III nitride semiconductor, the drift layer thickness is reduced and the impurity concentration is increased to lower the resistance of the drift layer. Can be realized.
However, in the drift layer with reduced resistance, for example, when the transistor is turned off, a high operating voltage (for example, about 600 V) applied to the gate insulating film and the drift layer sandwiched between the gate electrode and the drain electrode is It cannot be lowered sufficiently in the drift layer. Therefore, a voltage exceeding the dielectric strength is applied to the gate insulating film, and the gate insulating film may break down. Therefore, the drift layer is designed with a thickness and impurity concentration that match the characteristics (dielectric strength, etc.) of the gate insulating film, and is not designed to maximize the characteristics of the group III nitride semiconductor.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device and a method for manufacturing the same that can reduce the resistance by maximizing the characteristics of a group III nitride semiconductor regardless of the type of gate insulating film.

  In order to achieve the above object, an invention according to claim 1 comprises a first layer made of an n-type group III nitride semiconductor, and a group III nitride semiconductor provided on the first layer and containing a p-type impurity. A nitride semiconductor comprising a second layer and a third layer formed on the second layer and made of an n-type group III nitride semiconductor, and having a trench extending over the first, second and third layers A gate insulating film formed across the first, second and third layers on the inner wall of the nitride semiconductor structure facing the trench and the structure; and at least the gate insulating film A gate electrode formed to face the first and second layers, a source electrode formed to be electrically connected to the third layer, and electrically connected to the first layer And the drain electrode formed on the first layer. The portion opposed to the gate electrode across the gate insulating film, a fourth layer made of a Group III nitride semiconductor containing p-type impurities is formed, a nitride semiconductor device.

According to this configuration, a nitride having a vertical npn structure is formed by an n-type first layer (drift layer), a second layer (channel layer) containing a p-type impurity, and an n-type third layer (source layer). A semiconductor element is configured.
The on-resistance of the transistor is mainly determined by the resistance value of the drift layer. The resistance value of the drift layer can be reduced by designing the drift layer to suppress the thickness and increase the n-type impurity concentration. However, in this case, for example, when the maximum voltage is applied to the gate insulating film and the drift layer sandwiched between the gate electrode and the drain electrode, such as when the transistor is turned off, a sufficient voltage drop cannot be caused in the drift layer. The gate insulating film breaks down. Note that the maximum voltage is, for example, the operating voltage of the element, and specifically the magnitude of the potential of the drain electrode with respect to the potential of the source electrode (reference potential) during the operation of the element.

  According to the present invention, the fourth layer containing the p-type impurity is formed in a portion of the first layer (drift layer) facing the gate electrode with the gate insulating film interposed therebetween. Therefore, the depletion layer extending between the first layer and the fourth layer can cause a sufficient voltage drop to suppress the breakdown of the gate insulating film. As a result, even when a large voltage is applied to the drain electrode, breakdown of the gate insulating film can be suppressed. Therefore, the thickness and the n-type impurity concentration of the first layer (drift layer) can be designed regardless of the type of the gate insulating film, so that the characteristics of the group III nitride semiconductor can be maximized and the first layer ( Drift layer) can be formed, thereby providing a nitride semiconductor device with low resistance.

The invention according to claim 2 is the nitride semiconductor device according to claim 1, wherein the fourth layer is formed by thermal diffusion of p-type impurities. If the fourth layer is formed by thermal diffusion, a nitride semiconductor device that can easily form the fourth layer can be provided.
The p-type impurity contained in the fourth layer is preferably Mg as described in claim 3. If the p-type impurity is Mg, a high acceptor concentration can be realized with respect to the acceptor concentration of the fourth layer.

According to a fourth aspect of the present invention, in the trench, the inner wall straddling the first, second and third layers on the inner wall of the nitride semiconductor structure portion is formed between the first layer and the second layer. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is formed to be parallel to the stacking direction.
In the npn structure including the first layer, the second layer, and the third layer, the channel is formed on the inner sidewall parallel to the stacking direction of the first layer and the second layer. Therefore, for example, if acceptor atoms (which are p-type impurities contained in the fourth layer) for forming the fourth layer are introduced into the trench by a method having anisotropy, a channel is formed. Contact between the inner wall and the acceptor atom can be suppressed. As a result, deterioration of transistor characteristics (for example, increase in resistance) can be suppressed.

  According to a fifth aspect of the present invention, there is provided a first layer forming step of forming a first layer made of an n-type group III nitride semiconductor, and a group III nitride containing a p-type impurity on the first layer. A second layer forming step of forming a second layer made of a semiconductor; a third layer forming step of forming a third layer made of an n-type group III nitride semiconductor on the second layer; A trench forming step of forming a trench that penetrates the second layer from the third layer and reaches the first layer in the nitride semiconductor structure including the second and third layers, and is exposed by the trench forming step. A fourth layer forming step of forming a fourth layer made of a group III nitride semiconductor containing a p-type impurity in the first layer; and an inner wall of the nitride semiconductor structure portion facing the trench; A gate insulating film forming step of forming a gate insulating film so as to straddle the third and fourth layers; A gate electrode forming step of forming a gate electrode so as to face at least the second and fourth layers with the gate insulating film interposed therebetween, and a source of forming a source electrode so as to be electrically connected to the third layer A method for manufacturing a nitride semiconductor device, comprising: an electrode forming step; and a drain electrode forming step of forming a drain electrode so as to be electrically connected to the first layer.

  By manufacturing the nitride semiconductor device in this manner, a fourth layer containing a p-type impurity can be formed in a portion of the first layer (drift layer) facing the gate electrode with the gate insulating film interposed therebetween. Further, in the nitride semiconductor device obtained by this manufacturing method, even if the maximum voltage is applied to the gate insulating film and the first layer (drift layer), as in the nitride semiconductor device according to claim 1, Can be sufficiently lowered by a depletion layer extending between the first layer and the fourth layer. As a result, dielectric breakdown of the gate insulating film can be suppressed. Therefore, the thickness and the n-type impurity concentration of the first layer (drift layer) can be designed regardless of the type of the gate insulating film, so that the characteristics of the group III nitride semiconductor can be maximized and the first layer ( Drift layer) can be formed, thereby providing a nitride semiconductor device with reduced resistance.

  According to a sixth aspect of the present invention, in the fourth layer forming step, an acceptor atom is deposited on the first layer exposed by the trench forming step, and the deposited acceptor atom is used as a p-type impurity. The method for manufacturing a nitride semiconductor device according to claim 5, further comprising a thermal diffusion step of thermally diffusing the first layer. In this method, acceptor atoms can be selectively introduced as p-type impurities into the first layer exposed by trench formation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to the first embodiment of the present invention.
This nitride semiconductor device includes a nitride semiconductor multilayer structure 1.
The nitride semiconductor multilayer structure portion 1 is made of a group III nitride semiconductor, and includes an n-type layer 2 (first layer), a p-type GaN channel layer 3 (second layer) laminated on the n-type layer 2, and p And an n + -type GaN source layer 4 (third layer) stacked on the type GaN channel layer 3.

The n-type layer 2 includes a lower n + -type GaN drain layer 5 and an n -type GaN drift layer 6 stacked on the n + -type GaN drain layer 5.
The n + -type GaN drain layer 5 has an n-type impurity concentration (donor concentration) higher than that of the n -type GaN drift layer 6, and the n-type impurity concentration is, for example, 3 × 10 18 cm −3 . On the other hand, the n-type impurity concentration of the n -type GaN drift layer 6 is, for example, 1 × 10 17 cm −3 . The thickness of the n + -type GaN drain layer 5 is, for example, 300 μm, and the thickness of the n -type GaN drift layer 6 is, for example, 3 μm.

The p-type GaN channel layer 3 has a p-type impurity concentration of, for example, 4 × 10 19 cm −3 . The thickness of the p-type GaN channel layer 3 is, for example, 0.5 μm.
The n + -type GaN source layer 4 has an n-type impurity concentration of 3 × 10 18 cm −3 , for example. The thickness of the n + -type GaN source layer 4 is, for example, 0.5 μm.
The nitride semiconductor multilayer structure portion 1 is formed in a strip shape in the longitudinal direction extending in a direction perpendicular to the paper surface of FIG. Although not shown in FIG. 1, a plurality of nitride semiconductor multilayer structures 1 are formed at regular intervals in the width direction. In the nitride semiconductor multilayer structure portion 1, in the lateral direction along the multilayer interface orthogonal to the longitudinal direction (hereinafter, this direction may be referred to as “width direction”), the n + -type GaN source layer 4 is p-type. Depth reaching the middle of the stacking direction of the nitride semiconductor multilayer structure portion 1 in the n -type GaN drift layer 6 (hereinafter, this direction may be referred to as “stacking direction”) through the n-type GaN channel layer 3 The trench 7 is formed.

The trench 7 is formed to have a substantially rectangular cross section along the longitudinal direction of the nitride semiconductor multilayer structure portion 1. The pair of side walls facing the trench 7 facing in the width direction are the inner side walls of the nitride semiconductor multilayer structure portion 1 straddling the n -type GaN drift layer 6, the p-type GaN channel layer 3 and the n + -type GaN source layer 4. 8 and the inner wall 8 is formed to be parallel to the stacking direction, that is, to be perpendicular to the stack interface. Further, the bottom wall facing the trench 7 forms an inner bottom wall 9 of the n -type GaN drift layer 6, in which the lower ends in the stacking direction of the pair of inner walls 8 are connected. Although not shown in FIG. 1, the trench 7 is formed in each nitride semiconductor multilayer structure portion 1 formed in a plurality at a constant interval in the width direction.

At the bottom of the trench 7, a p-type GaN layer 10 having a substantially elliptical cross section is formed on the inner wall 8 and the inner wall 9 of the n -type GaN drift layer 6. Specifically, the p-type GaN layer 10 is formed such that the width direction is the major axis direction and the stacking direction is the minor axis direction, and the upper portion in the minor axis direction is the stack of the inner walls 8. It is formed so as to cover the lower end of the direction.
The impurity concentration of the p-type GaN layer 10 is, for example, 4 × 10 19 cm −3 . Here, it is assumed that the acceptor concentration by the p-type impurity is 5 × 10 17 cm −3 .

In addition, the major axis d1 of the p-type GaN layer 10 is larger than the interval W1 in the width direction of the pair of inner side walls 8, and the difference between both sides of the trench is, for example, 0.1 μm. Further, the minor axis d2 of the p-type GaN layer 10 (in FIG. 1, the length in the minor axis direction from the bottom surface of the inner bottom wall 9 facing the trench 7 to the outer periphery of the p-type GaN layer 10 is defined as the minor axis d2. ) Varies depending on the breakdown voltage performance of the element and the impurity concentration of the n -type GaN drift layer 6, but is 0.5 μm, for example.

A gate insulating film 11 is formed so as to cover the entire inner wall of the nitride semiconductor multilayer structure portion 1 including the inner wall 8 and the inner bottom wall 9 and the upper surface 14 of the n + -type GaN source layer 4.
The gate insulating film 11 can be configured using, for example, an oxide or a nitride, or a combination thereof. More specifically, silicon oxide (SiO 2 ), gallium oxide (Ga 2 O 3 ), magnesium oxide (MgO), scandium oxide (Sc 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO) 2 ), silicon nitride (SiN), aluminum nitride (AlN), or a combination thereof. By configuring the gate insulating film 11 using the above-described oxide or nitride, or a combination thereof, the breakdown voltage of the nitride semiconductor element can be improved and the surface leakage current can be reduced.

  Further, the gate insulating film 11 is formed with a thickness of a portion on the pair of inner side walls 8 such that the portion is opposed to the trench 7 with the trench 7 interposed therebetween, for example, a thickness of 0.1 μm. . The gate insulating film 11 is in contact with the p-type GaN layer 10 formed on the inner bottom wall 9, and the thickness of the portion on the inner bottom wall 9 is larger than the thickness of the portion on the inner wall 8. For example, it is formed with a thickness of 0.2 μm.

On the gate insulating film 11, a gate electrode 12 has an inner wall (that is, the n -type GaN drift layer 6, the p-type GaN channel layer 3, and the n + -type) of the nitride semiconductor multilayer structure portion 1 with the gate insulating film 11 interposed therebetween. Opposite to the GaN source layer 4), the trench 7 is filled up.
In the gate electrode 12, the upper surface 13 parallel to the stacked interface (hereinafter sometimes referred to as “stacked interface”) of the nitride semiconductor multilayer structure 1 is flush with the upper surface 14 of the n + -type GaN source layer 4. It is formed as follows. The gate electrode 12 is made of, for example, a Ni / Au alloy, a Pd / Au alloy, a Pd / Ti / Au alloy, a Pd / Pt / Au alloy, Pt, Al, Ni, and Au laminated on the Ni. It can be formed using a conductive material such as polysilicon.

An insulating film 17 is formed on the upper surface 14 of the n + -type GaN source layer 4 and the upper surface 13 of the gate electrode 12.
The insulating film 17 is formed as an interlayer insulating film so that the gate electrode 12 does not short-circuit to other electrodes. The insulating film 17 can be formed using, for example, an insulating material similar to that of the gate insulating film 11.

A region in the p-type GaN channel layer 3 in the vicinity of the inner wall 8 facing the trench 7 is a channel region 15 facing the gate electrode 12. In the channel region 15, an inversion layer (channel) that conducts between the n-type layer 2 and the n + -type GaN source layer 4 is formed by applying an appropriate bias to the gate electrode 12.
A contact hole 18 reaching the upper surface 14 of the n + -type GaN source layer 4 is formed in the insulating film 17 and the gate insulating film 11. A source electrode 16 is formed on the contact hole 18 and the insulating film 17.

The source electrode 16 can be formed using, for example, Ti and a metal such as a Ti / Al alloy made of Al laminated on the Ti, and is electrically connected to the n + -type GaN source layer 4. . By forming the source electrode 16 with a metal containing Al, good ohmic characteristics can be obtained at the junction between the source electrode 16 and the n + -type GaN source layer 4. In addition, the source electrode 16 may be formed using Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide). The source electrode 16 is insulated from the gate electrode 12 by the insulating film 17.

A drain electrode 19 is formed in contact with the back surface (the lower surface in the stacking direction) of the n + -type GaN drain layer 5. The drain electrode 19 can be formed using, for example, the same kind of metal as the source electrode 16, that is, Ti and a metal such as a Ti / Al alloy made of Al stacked on the Ti, and an n + -type GaN drain. It is electrically connected to layer 5. In addition, the drain electrode 19 may be formed using Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

Next, the operation of the nitride semiconductor device will be described.
An operating voltage (for example, 600 V) at which the drain electrode 19 side is positive is applied between the source electrode 16 and the drain electrode 19. As a result, a reverse voltage is applied to the pn junction at the interface between the n -type GaN drift layer 6 and the p-type GaN channel layer 3. As a result, between the n + -type GaN source layer 4 and the n-type layer 2, that is, between the source electrode 16 and the drain electrode 19 (between the source and drain) is in a cut-off state (reverse bias state).

In this state, when a bias equal to or higher than the gate threshold voltage that is positive with the source electrode 16 as a reference potential is applied to the gate electrode 12, electrons are induced in the vicinity of the interface with the gate insulating film 11 in the channel region 15. Thus, an inversion layer (channel) is formed. The n-type layer 2 and the n + -type GaN source layer 4 are electrically connected via the inversion layer. Thus, conduction between the source and the drain is established. That is, when a predetermined bias is applied to the gate electrode 12, the source and the drain become conductive, and when no bias is applied to the gate electrode 12, the source and the drain are cut off. In this way, normally-off transistor operation is realized.

2A to 2G are schematic cross-sectional views for explaining a method for manufacturing the nitride semiconductor device of FIG.
When manufacturing the nitride semiconductor device of FIG. 1, first, each layer of the nitride semiconductor multilayer structure portion 1 is crystal-grown by, for example, MOCVD (Metal Organic Chemical Vapor Deposition).

Specifically, first, by growing GaN under the growth conditions of growth temperature: 1050 ° C. and growth time: 150 minutes, as shown in FIG. 2A, n + -type GaN drain layer 5 and n -type GaN drift layer 6 is formed (first layer forming step). For example, Si can be used as an n-type impurity doped in the grown GaN. When the n + -type GaN drain layer 5 is grown, the flow rate of Si source gas (for example, silane) is relatively increased, and when the n -type GaN drift layer 6 is grown, the flow rate of Si source gas is relatively decreased.

the n - Following -type GaN drift layer 6 formed of, n - type on the GaN drift layer 6, for example, growth temperature: 1000 ° C., growth time: by growing GaN in the growth conditions of 35 minutes, 2A As shown in FIG. 2, the p-type GaN channel layer 3 is formed (second layer forming step). For example, Mg can be used as a p-type impurity for doping the grown GaN.

After the formation of the p-type GaN channel layer 3, for example, by growing GaN under the growth conditions of growth temperature: 1050 ° C. and growth time: 25 minutes, as shown in FIG. 2A, the n + -type GaN source layer 4 becomes It is formed (third layer forming step). Note that, for example, Si can be used as an n-type impurity to be doped in the grown GaN. In this manner, the nitride semiconductor multilayer structure 1 including the n + -type GaN drain layer 5, the n -type GaN drift layer 6, the p-type GaN channel layer 3 and the n + -type GaN source layer 4 is formed on one side of the substrate 20. Is done.

After the nitride semiconductor multilayer structure portion 1 is thus formed, the nitride semiconductor multilayer structure portion 1 is etched in a stripe shape. That is, a mask (for example, SiO 2 ) 29 having an opening corresponding to the trench 7 is formed on the nitride semiconductor multilayer structure portion 1, and the n + -type GaN source layer 4 is used to form a p-type using this mask 29. Striped trenches 7 having a substantially rectangular cross section extending through the GaN channel layer 3 and reaching the middle part of the thickness of the n -type GaN drift layer 6 are formed by etching. Thereby, the nitride semiconductor multilayer structure portion 1 is shaped into a stripe shape (a stripe shape extending in a direction perpendicular to the paper surface of FIG. 2B and the like).

The trench 7 is formed by the inner wall 8 of the nitride semiconductor multilayer structure portion 1 that is exposed by the formation of the trench 7 and straddles the n -type GaN drift layer 6, the p-type GaN channel layer 3, and the n + -type GaN source layer 4. For example, dry etching (isotropic) using a chlorine-based gas so as to be parallel to the stacking direction of the nitride semiconductor multilayer structure 1 (that is, perpendicular to the stack interface of the nitride semiconductor multilayer structure 1) Etching). In addition, after the dry etching, if necessary, wet etching for improving the inner wall 8 of the nitride semiconductor multilayer structure portion 1 and the inner bottom wall 9 of the nitride semiconductor multilayer structure portion 1 damaged by the dry etching. Processing may be performed.

  For wet etching, it is preferable to use KOH (potassium hydroxide), NaOH (sodium hydroxide), TMAH (tetramethylammonium hydroxide), or the like. Thereby, the damaged inner wall 8 and inner bottom wall 9 can be improved, and the inner wall 8 and inner bottom wall 9 with less damage can be obtained. Further, Si-based oxides, Ga oxides, and the like can also be removed by wet etching using HF (hydrofluoric acid), HCl (hydrochloric acid), or the like. Thereby, the inner wall 8 and the inner bottom wall 9 can be leveled, and the inner wall 8 and the inner bottom wall 9 with little damage can be obtained. By reducing the damage on the inner side wall 8, the crystal state of the channel region 15 (see FIG. 1) can be kept good. Further, the interface between the inner wall 8 and the gate insulating film 11 can be a good interface.

As a result, the interface state can be reduced. Thereby, the channel resistance can be reduced and the leakage current can be suppressed. Note that a low-damage dry etching process can be applied instead of the wet etching process.
Subsequently, acceptor atoms (for example, Mg) are deposited on the inner bottom wall 9 of the trench 7 by, for example, vapor deposition while leaving the mask 29 used for dry etching. Thereby, as shown in FIG. 2C, a deposit 30 made of acceptor atoms is formed on the inner bottom wall 9. If necessary, another metal (for example, Mo or Pt) that prevents evaporation of Mg may be formed on the deposited body 30, or for the purpose of removing unnecessary Mg formed on the inner wall 8, Wet etching with nitric acid or the like may be performed.

Thereafter, for example, annealing is performed in a nitrogen atmosphere or an ammonia atmosphere under annealing conditions of annealing temperature: 900 ° C. and annealing time: 60 minutes. By this annealing treatment, a part of Mg in the deposit 30 is diffused into the n -type GaN drift layer 6. Thereby, the p-type GaN layer 10 is formed as shown in FIG. 2C. Note that Mg remaining on the inner bottom wall 9 is removed by nitric acid, for example.

After the p-type GaN layer 10 is formed, the n - type GaN drift layer 6, the p-type GaN channel layer 3, and the inner bottom wall 9 of the nitride semiconductor multilayer structure 1 where the p-type GaN layer 10 is formed are covered. n + -type GaN source layer 4 gate insulating film 11 covering the inner wall 8 and the n + -type GaN upper surface 14 of the source layer 4 of the nitride semiconductor laminated structure 1 that spans is formed (step of forming a gate insulating film). For the formation of the gate insulating film 11, an ECR (Electron Cyclotron Resonance) sputtering method, a plasma CVD method, or a thermal CVD method is applied. Further, annealing may be performed in an arbitrary atmosphere for the purpose of reducing the interface state between the gate insulating film and the inner wall 8.

  Next, a metal used as a material for the gate electrode 12 is sputtered by a sputtering method through a photoresist (not shown) having an opening in a region where the gate electrode 12 is to be formed by a known photolithography technique. Thereafter, the photoresist is removed, and unnecessary portions of metal (portions other than the gate electrode 12) are lifted off together with the photoresist. By these steps, as shown in FIG. 2E, the gate electrode 12 is formed on the portion of the gate insulating film 11 in the trench 7 (gate electrode forming step).

After the gate electrode 12 is formed, as shown in FIG. 2E, an insulating film 17 is formed on the surface of the gate insulating film 11 and the upper surface 13 of the gate electrode 12 by, for example, ECR sputtering.
After the insulating film 17 is formed, a photomask having an opening facing a portion where the contact hole 18 is to be formed is applied by a known photolithography technique, and the gate insulating film 11 and the insulating film 17 are dry-etched. The Thereby, the excess gate insulating film 11 and insulating film 17 are removed, and a contact hole 18 exposing the upper surface 14 of the n + -type GaN source layer 4 is formed as shown in FIG. 2F.

Subsequently, a metal used as a material for the source electrode 16 is formed on the entire upper surface of the nitride semiconductor multilayer structure portion 1 by, for example, a sputtering method. Thereby, the source electrode 16 is formed in the contact hole 18 and on the insulating film 17.
Thereafter, the drain electrode 19 is formed on the back surface of the n + -type GaN drain layer 5 by the same method as that for the source electrode 16 (drain electrode forming step).

Thus, the nitride semiconductor device of FIG. 1 can be obtained as shown in FIG. 2G.
Each of the plurality of nitride semiconductor multilayer structures 1 forms a unit cell. The source electrode 16 and the drain electrode 19 are common electrodes for all cells.
As described above, according to the nitride semiconductor device of this embodiment, the inner wall 8 and the inner wall 9 of the n -type GaN drift layer 6 are formed on the bottom of the trench 7 with the p-type GaN having a substantially elliptical cross section. Layer 10 is formed. The impurity concentration of the p-type GaN layer 10 is, for example, 4 × 10 19 cm −3 or less, and the acceptor concentration is, for example, 5 × 10 17 cm −3 .

Therefore, when the element is turned off, that is, when the potential of the gate electrode 12 becomes the same reference potential as the potential of the source electrode 16, a portion sandwiched between the gate electrode 12 and the drain electrode 19 along the stacking direction (that is, Even when a maximum (operating) voltage is applied to a portion of the gate insulating film 11 on the inner bottom wall 9, a stacked structure including the p-type GaN layer 10, the n -type GaN drift layer 6 and the n + -type GaN drain layer 5. In the depletion layer extending between the n -type GaN drift layer 6 and the p-type GaN layer 10, the voltage can be sufficiently lowered.

For example, when the operating voltage of the element is 600 V, a potential difference of 600 V is generated between the gate electrode 12 and the drain electrode 19 when the element is turned off. When the voltage dropped in the n + -type GaN drain layer 5 and the n -type GaN drift layer 6 is 200 V, if the p-type GaN layer 10 is not formed, a high voltage of 400 V is applied to the gate insulating film 11. As a result, the gate insulating film 11 may break down.

In contrast, in the nitride semiconductor device of this embodiment, since the p-type GaN layer 10 is formed, the resistance value of the depletion layer spreading between the n -type GaN drift layer 6 and the p-type GaN layer 10 is small. For example, when it is 150% of the n -type GaN drift layer 6, a voltage drop of 300 V is generated in the depletion layer, and the voltage applied to the gate insulating film 11 can be reduced to 100 V. As a result, the dielectric breakdown of the gate insulating film 11 can be suppressed.

Therefore, the thickness of the n -type GaN drift layer 6 and the n-type impurity concentration can be designed regardless of the type of the gate insulating film 11, so that the characteristics of the group III nitride semiconductor can be maximized to obtain the n -type. The GaN drift layer 6 can be formed, thereby providing a nitride semiconductor device with reduced resistance.
Further, the p-type GaN layer 10 has a pair of inner side walls 8 of the nitride semiconductor multilayer structure portion 1 parallel to the stacking direction (that is, the nitride semiconductor multilayer structure portion 1 in the nitride semiconductor device manufacturing process). The trench 7 is formed so as to be perpendicular to the stack interface, and the acceptor atoms in the deposit 30 deposited on the inner bottom wall 9 exposed in the trench 7 are formed by thermal diffusion.

In the thermal diffusion, the diffusion of the acceptor atoms into the GaN as a p-type impurity from the contact surface where the acceptor atoms are in contact with each other as a result of deposition spreads. For this reason, it is desirable that the acceptor atom is not brought into contact with a portion where the acceptor atom is not desired to be diffused.
If the pair of inner side walls 8 desired for the trench 7 are parallel to the stacking direction as in this nitride semiconductor element, contact between the inner side walls 8 and the acceptor atoms can be suppressed. Therefore, it is possible to suppress the diffusion of acceptor atoms to the inner wall 8 where the channel is formed. As a result, deterioration of transistor characteristics (for example, increase in resistance) can be suppressed.

FIG. 3 is a schematic cross-sectional view for explaining the structure of the nitride semiconductor device according to the second embodiment of the present invention. In FIG. 3, portions corresponding to the respective portions shown in FIG. 1 are denoted by the same reference numerals as those respective portions. Further, in the following, detailed description of the parts denoted by the same reference numerals is omitted.
In FIG. 3, the nitride semiconductor multilayer structure portion 1 includes an n-type layer 2 (first layer) and a p-type layer 23 (second layer) made of GaN containing p-type impurities provided on the n-type layer 2. And.

In FIG. 3, the trench 7 extends from the outermost surface 24 parallel to the stacking interface of the nitride semiconductor stacked structure portion 1 in the p-type layer 23 (hereinafter, this interface may be simply referred to as “stacking interface”). At a depth that penetrates the p-type layer 23 and reaches the middle part of the nitride semiconductor multilayer structure portion 1 in the n -type GaN drift layer 6 (hereinafter, this direction may be referred to as “stacking direction”). Is formed.

In the p-type layer 23, the peripheral region of the trench 7 extending in the width direction from the upper part of the inner wall 8 of the trench 7 is an n + -type GaN source region 25 containing n-type impurities at a higher concentration than p-type impurities. is there. On the other hand, in the p-type layer 23, a region other than the n + -type GaN source region 25 is a p-type GaN channel region 26 containing a p-type impurity at a higher concentration than the n-type impurity.
A region in the p-type GaN channel region 26 in the vicinity of the inner wall 8 facing the trench 7 is a channel region 15 facing the gate electrode 12.

Further, in FIG. 3, the contact hole 18 is formed across the outermost surface 27 of the n + -type GaN source region 25 and the outermost surface 28 of the p-type GaN channel region 26 in the outermost surface 24 of the p-type layer 23. Thereby, the source electrode 16 is in ohmic contact with the n + -type GaN source region 25 and is in Schottky contact with the p-type GaN channel region 26. Other configurations are the same as those of the first embodiment described above, and the same operations and effects as those of the first embodiment can be exhibited.

The nitride semiconductor device of this embodiment can be manufactured by a method similar to the method described with reference to FIGS. 2A to 2G.
That is, after the p-type GaN channel layer 3 is formed, a mask having an opening is formed in a region where the n + -type GaN source region 25 is to be formed by a known photolithography technique, and the p-type GaN channel region exposed from the mask is formed. An ion of an n-type impurity (for example, Si) may be implanted toward 26. The acceleration energy at the time of ion implantation is, for example, 60 keV, and the dose amount of ions implanted by this acceleration energy is, for example, 1 × 10 20 cm −2 . Thereafter, for example, annealing is performed under annealing conditions of an annealing temperature of 1000 ° C. and an annealing time of 30 minutes, so that the implanted n-type impurity is coordinated to each site of the GaN crystal structure to form an n + -type GaN source. Region 25 can be formed.

As mentioned above, although two embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above-described embodiment, an example in which GaN is used as the group III nitride semiconductor has been described. However, a nitride semiconductor element may be configured using another group III nitride semiconductor such as AlGaN. In this case, it is not necessary to use a single group III nitride semiconductor. For example, the nitride semiconductor multilayer structure 1 may be formed by combining a GaN layer and an AlGaN layer.

Further, in the above-described embodiment, the trench 7 is formed in a substantially rectangular cross section so that the inner wall 8 is parallel to the stacking direction. Other shapes such as a trapezoid, a U-shaped section, a V-shaped section, and a trapezoidal section may be used.
In addition, various design changes can be made within the scope of matters described in the claims.

1 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to a first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view for illustrating the method for manufacturing the nitride semiconductor device of FIG. 1. It is a figure which shows the next process of FIG. 2A. It is a figure which shows the next process of FIG. 2B. It is a figure which shows the next process of FIG. 2C. It is a figure which shows the next process of FIG. 2D. It is a figure which shows the next process of FIG. 2E. It is a figure which shows the next process of FIG. 2F. It is a schematic sectional drawing for demonstrating the structure of the nitride semiconductor element which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nitride semiconductor laminated structure part 2 n-type layer 3 p-type GaN channel layer 4 n + type GaN source layer 5 n + type GaN drain layer 6 n - type GaN drift layer 7 trench 8 inner wall 9 inner bottom wall 10 p type GaN layer 11 Gate insulating film 12 Gate electrode 16 Source electrode 19 Drain electrode 23 p-type layer 25 n + -type GaN source region 26 p-type GaN channel region

Claims (6)

  1. a first layer formed of an n-type group III nitride semiconductor, a second layer formed on the first layer and formed of a group III nitride semiconductor containing a p-type impurity, and formed on the second layer; A nitride semiconductor structure having a third layer made of a group III nitride semiconductor of a type and having a trench formed across the first, second and third layers;
    A gate insulating film formed on the inner wall of the nitride semiconductor structure facing the trench so as to straddle the first, second and third layers;
    A gate electrode formed to face at least the first and second layers with the gate insulating film interposed therebetween;
    A source electrode formed to be electrically connected to the third layer;
    A drain electrode formed to be electrically connected to the first layer,
    A nitride semiconductor device, wherein a fourth layer made of a group III nitride semiconductor containing a p-type impurity is formed in a portion of the first layer facing the gate electrode with the gate insulating film interposed therebetween.
  2.   The nitride semiconductor device according to claim 1, wherein the fourth layer is formed by thermal diffusion of p-type impurities.
  3.   The nitride semiconductor device according to claim 1, wherein the p-type impurity contained in the fourth layer is Mg.
  4.   The trench is formed such that an inner wall of the inner wall of the nitride semiconductor structure portion extending over the first, second, and third layers is parallel to a stacking direction of the first layer and the second layer. The nitride semiconductor device according to any one of claims 1 to 3.
  5. a first layer forming step of forming a first layer made of an n-type group III nitride semiconductor;
    A second layer forming step of forming a second layer made of a group III nitride semiconductor containing a p-type impurity on the first layer;
    A third layer forming step of forming a third layer made of an n-type group III nitride semiconductor on the second layer;
    Forming a trench penetrating the second layer from the third layer and reaching the first layer in the nitride semiconductor structure including the first, second and third layers;
    A fourth layer forming step of forming a fourth layer made of a group III nitride semiconductor containing a p-type impurity in the first layer exposed by the trench forming step;
    Forming a gate insulating film on the inner wall of the nitride semiconductor structure facing the trench so as to straddle the second, third and fourth layers;
    Forming a gate electrode so as to face at least the second and fourth layers across the gate insulating film; and
    Forming a source electrode so as to be electrically connected to the third layer;
    And a drain electrode forming step of forming a drain electrode so as to be electrically connected to the first layer.
  6.   The fourth layer forming step includes a depositing step of depositing acceptor atoms on the first layer exposed by the trench forming step, and a thermal diffusion step of thermally diffusing the deposited acceptor atoms as p-type impurities into the first layer. The manufacturing method of the nitride semiconductor element of Claim 5 containing these.
JP2008113956A 2008-04-24 2008-04-24 Nitride semiconductor element, and method for manufacturing nitride semiconductor element Pending JP2009267029A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184956A (en) * 2011-04-15 2011-09-14 中山大学 Longitudinal conduction GaN enhancement type MISFET (Metal Integrated Semiconductor Field Effect Transistor) device and manufacturing method thereof
JP2014192174A (en) * 2013-03-26 2014-10-06 Toyoda Gosei Co Ltd Semiconductor device and manufacturing method of the same
US9349856B2 (en) 2013-03-26 2016-05-24 Toyoda Gosei Co., Ltd. Semiconductor device including first interface and second interface as an upper surface of a convex protruded from first interface and manufacturing device thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116822A (en) * 2003-10-08 2005-04-28 Denso Corp Insulated-gate semiconductor device and its manufacturing method
JP2007103451A (en) * 2005-09-30 2007-04-19 Toshiba Corp Semiconductor device and its manufacturing method
JP2007242852A (en) * 2006-03-08 2007-09-20 Toyota Motor Corp Insulated gate semiconductor device and method of manufacturing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116822A (en) * 2003-10-08 2005-04-28 Denso Corp Insulated-gate semiconductor device and its manufacturing method
JP2007103451A (en) * 2005-09-30 2007-04-19 Toshiba Corp Semiconductor device and its manufacturing method
JP2007242852A (en) * 2006-03-08 2007-09-20 Toyota Motor Corp Insulated gate semiconductor device and method of manufacturing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184956A (en) * 2011-04-15 2011-09-14 中山大学 Longitudinal conduction GaN enhancement type MISFET (Metal Integrated Semiconductor Field Effect Transistor) device and manufacturing method thereof
JP2014192174A (en) * 2013-03-26 2014-10-06 Toyoda Gosei Co Ltd Semiconductor device and manufacturing method of the same
US9349856B2 (en) 2013-03-26 2016-05-24 Toyoda Gosei Co., Ltd. Semiconductor device including first interface and second interface as an upper surface of a convex protruded from first interface and manufacturing device thereof

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