JP3471823B2 - Insulated gate semiconductor device and method of manufacturing the same - Google Patents
Insulated gate semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP3471823B2 JP3471823B2 JP10658992A JP10658992A JP3471823B2 JP 3471823 B2 JP3471823 B2 JP 3471823B2 JP 10658992 A JP10658992 A JP 10658992A JP 10658992 A JP10658992 A JP 10658992A JP 3471823 B2 JP3471823 B2 JP 3471823B2
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 40
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims 2
- 108091006146 Channels Proteins 0.000 description 32
- 239000000370 acceptor Substances 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 241001122767 Theaceae Species 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、シリコンカーバイド
（ＳｉＣ）を主たる半導体材料として用いた絶縁ゲート
型の半導体装置に関し、特に、パワーデバイスに用いら
れる半導体装置の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate type semiconductor device using silicon carbide (SiC) as a main semiconductor material, and more particularly to the structure of a semiconductor device used for a power device.
【０００２】[0002]
【従来の技術】パワーデバイスとして用いられる半導体
装置の主たる半導体材料は、従来シリコン（Ｓｉ）が採
用されている。しかし、抵抗値の低減、冷却の問題など
材料に起因する限界から、種々の新しい材料が検討され
ている。その中で、シリコンカーバイト（ＳｉＣ）は、
最大電界強度（Ｅｍ）がシリコンと比べて１桁以上大き
いことから、次世代のパワーデバイスの主たる材料とし
て注目を集めている。すなわち、最大電界強度（Ｅｍ）
と、導通時の抵抗Ｒｏｎ、またスイッチング速度ｔf は
以下の関係にあるため、最大電界強度（Ｅｍ）が１桁以
上大きくなることにより、性能の大幅な向上が図られる
のである。2. Description of the Related Art Conventionally, silicon (Si) has been adopted as a main semiconductor material of a semiconductor device used as a power device. However, various new materials have been investigated due to limitations caused by the materials such as reduction of resistance value and cooling problem. Among them, Silicon Carbide (SiC)
Since the maximum electric field strength (Em) is larger than that of silicon by one digit or more, it has been attracting attention as a main material for next-generation power devices. That is, the maximum electric field strength (Em)
Since the resistance Ron during conduction and the switching speed t f have the following relationship, the maximum electric field strength (Em) is increased by one digit or more, so that the performance is significantly improved.
【０００３】先ず、ＭＯＳＦＥＴにおいて、導通時の抵
抗Ｒｏｎについては、以下のような関係が近似的に成立
する。First, in the MOSFET, the following relationship approximately holds for the resistance Ron when the MOSFET is conductive.
【０００４】[0004]
【数１】 [Equation 1]
【０００５】また、スイッチング速度ｔf においては、
以下のような関係が近似的に成り立つ。At the switching speed t f ,
The following relationships approximately hold.
【０００６】[0006]
【数２】 [Equation 2]
【０００７】図７に示す従来のパワーＭＯＳＦＥＴの構
造を基に説明すると、式（１）は、導通時の素子の主な
抵抗がドレイン層１１の抵抗に等しいと考えたものであ
る。To explain based on the structure of the conventional power MOSFET shown in FIG. 7, the equation (1) is based on the assumption that the main resistance of the element during conduction is equal to the resistance of the drain layer 11.
【０００８】すなわち、従来のＭＯＳＦＥＴにおいて
は、ドレイン電極１２が裏面に接続されたｎ+ 型の半導
体基板５の表面にエピタキシャル成長させたｎ- 型のド
レイン層１１が形成されており、そのドレイン層１１の
表面にｐ型のベース層８、さらにそのベース層８の内部
にｎ+ 型のソース層６が形成されている。そして、ベー
ス層８の表面からソース層６の表面に亘ってソース電極
１０が接続されており、さらに、ソース層６の表面から
ベース層８を経てドレイン層１１の表面に亘ってゲート
絶縁膜２を介してゲート電極１が設置されている。この
ため、ゲート電極１に高電位を印加すると、ベース層８
の表面にチャネルが形成され、このチャネルを通ってソ
ース層６からドレイン層１１、さらに、基板５に電流が
流れる。そして、この主たる経路となるドレイン層１１
の抵抗に基づき近似した結果が式（１）に表されてい
る。この仮定は、３００Ｖ以下の耐圧の素子において
は、チャネルの抵抗が大きくなるため、その影響を加味
する必要があるが、３００Ｖ以上の耐圧をもった素子で
はほぼ正しい。すなわち、高耐圧の素子においては、最
大電界強度（Ｅｍ）が大きくなることにより、導通時の
抵抗Ｒｏｎが急激に低下するのである。このため、シリ
コンカーバイトを主たる半導体材料として用いたパワー
デバイスにおいては、シリコン製のパワーデバイスと比
べて抵抗を非常に小さくすることができるので、同じ電
流密度を確保する素子としては、素子面積を大幅に小さ
くすることができる。従って、従来のパワーデバイスと
比べて、小型軽量で、さらに低価格のパワーデバイスを
実現できることとなる。なお、近似式（１）によると最
大電界強度（Ｅｍ）が１桁大きくなると、３桁程度の導
通時の抵抗Ｒｏｎの減少が予想されるが、シリコンカー
バイト中の電子移動度が小さいため、約２桁程度の減少
となる。従って、シリコンカーバイトを用いることによ
り、素子抵抗をシリコンの場合の１／１０以下とするこ
とができる。That is, in the conventional MOSFET, the n − type drain layer 11 epitaxially grown is formed on the surface of the n + type semiconductor substrate 5 having the drain electrode 12 connected to the back surface, and the drain layer 11 is formed. A p-type base layer 8 is formed on the surface of, and an n + -type source layer 6 is formed inside the base layer 8. The source electrode 10 is connected from the surface of the base layer 8 to the surface of the source layer 6, and further, from the surface of the source layer 6 to the base layer 8 to the surface of the drain layer 11 to the gate insulating film 2 The gate electrode 1 is installed via the. Therefore, when a high potential is applied to the gate electrode 1, the base layer 8
A channel is formed on the surface of the substrate, and a current flows from the source layer 6 to the drain layer 11 and further to the substrate 5 through the channel. Then, the drain layer 11 serving as the main path
The result approximated based on the resistance of is expressed by equation (1). This assumption is correct in an element having a withstand voltage of 300 V or higher, although the channel resistance becomes large in an element having a withstand voltage of 300 V or lower, and it is necessary to consider the influence. That is, in the high breakdown voltage element, the maximum electric field strength (Em) becomes large, so that the resistance Ron at the time of conduction sharply decreases. Therefore, in a power device using silicon carbide as a main semiconductor material, the resistance can be made extremely smaller than that of a silicon power device. Can be significantly reduced. Therefore, it is possible to realize a power device which is smaller and lighter in weight and lower in price than the conventional power device. According to the approximate expression (1), when the maximum electric field strength (Em) increases by one digit, the resistance Ron during conduction is expected to decrease by about three digits, but the electron mobility in the silicon carbide is small, It will decrease by about 2 digits. Therefore, by using the silicon carbide, the element resistance can be reduced to 1/10 or less that of silicon.
【０００９】さらに、シリコンカーバイトは、シリコン
と比較し、バンドギャップがエネルギー差が２倍以上あ
るため、耐圧性能などへの温度の影響が非常に小さい。
従って、シリコンカーバイトを主たる材料としたパワー
デバイスにおいては、従来のパワーデバイスでは必要で
あった冷却を考慮する必要がない。このため、シリコン
カーバイトによるパワーデバイスを用いることにより装
置の小型化、低価格化を容易に実現することができる。Further, silicon carbide has a bandgap having an energy difference twice or more that of silicon, so that the influence of temperature on withstand voltage performance is very small.
Therefore, in the power device using silicon carbide as the main material, it is not necessary to consider the cooling required in the conventional power device. Therefore, by using the power device made of silicon carbide, it is possible to easily realize the miniaturization and cost reduction of the device.
【００１０】[0010]
【発明が解決しようとする課題】このように、シリコン
カーバイトを用いたパワーデバイスは、従来のシリコン
によるパワーデバイスに比べ多くの長所を有しており、
将来有望な半導体材料である。しかしながら、シリコン
カーバイト中のキャリアの移動度が低いという問題があ
る。特に、正孔の移動度が低く、ｐ領域の抵抗が大きく
なる傾向がある。As described above, the power device using the silicon carbide has many advantages as compared with the conventional power device using silicon.
It is a promising semiconductor material in the future. However, there is a problem that the low mobility of carriers in silicon carbide. In particular, the mobility of holes is low, and the resistance in the p region tends to increase.
【００１１】このため、下記するように、電圧阻止能力
が低下し、素子破壊に至ることが考えられる。Therefore, as described below, it is considered that the voltage blocking ability is lowered and the element is destroyed.
【００１２】すなわち、シリコンカーバイトを半導体材
料として採用した装置においても、シリコンと同様にド
ナー、アクセプタを導入することによりｐ型、ｎ型の伝
導領域や、ｐｎ接合面を形成している。そして、シリコ
ンカーバイトに対しては、アクセプタとしてＢやＡｌを
導入することによりｐ型の拡散領域を形成できることが
知られている。しかし、これらのアクセプタレベルが
０．２ｅＶとかなり深く、室温においては、導入された
アクセプタの内、熱的に活性化してキャリアを出してい
るのは数パーセント以下である。さらに、シリコンカー
バイト中の正孔の移動度は数１０程度と低い。従って、
シリコンと比較すると、同一のアクセプタ濃度では、シ
リコンカーバイトの方がはるかに抵抗が高くなる。That is, even in a device using silicon carbide as a semiconductor material, p-type and n-type conduction regions and a pn junction surface are formed by introducing a donor and an acceptor like silicon. It is known that a p-type diffusion region can be formed in silicon carbide by introducing B or Al as an acceptor. However, these acceptor levels are as deep as 0.2 eV, and at room temperature, only a few percent or less of the introduced acceptors thermally activated to generate carriers. Further, the mobility of holes in the silicon carbide is as low as several tens. Therefore,
When compared with silicon, in the same acceptor concentration, more of silicon carbide is a much higher resistance.
【００１３】一方、図７に示すＭＯＳＦＥＴにおいて、
ｐ型ベース層８のアクセプタ濃度は、チャネルを形成す
るＭＯＳ反転層の閾値が一定となるように設計される。
通常のシリコンのＭＯＳＦＥＴでは１０16〜１０17ｃｍ
-3程度に設定されるが、これ以上にアクセプタ濃度を高
くすると閾値が増大し容易に駆動できなくなることた
め、自由にアクセプタ濃度を大きくすることは不可能で
ある。従って、シリコンカーバイトを材料とするＭＯＳ
ＦＥＴにおいては、ｐ型ベースの抵抗値が高くなってし
まう。On the other hand, in the MOSFET shown in FIG.
The acceptor concentration of the p-type base layer 8 is designed so that the threshold value of the MOS inversion layer forming the channel becomes constant.
Normal silicon MOSFET is 10 16 to 10 17 cm
Although it is set to about −3 , if the acceptor concentration is further increased, the threshold value increases and it becomes impossible to drive easily. Therefore, it is impossible to freely increase the acceptor concentration. Therefore, MOS made from silicon carbide
In the FET, the resistance value of the p-type base becomes high.
【００１４】このように抵抗がベース層の動特性の悪化
をもたらすこととなる。すなわち、素子が導通状態から
非導通状態に移行するときは、外部電圧が素子のソース
１０・ドレイン１２間に除々に加わることとなる。この
電圧は、ｐ型ベース層８とｎ型ベース層１１との間のｐ
ｎ接合に印加され、それぞれの層に空乏層２０、１９が
広がる。そして、この空乏層１９、２０は、電圧の上昇
と共に広がり、イオン化したドナー１８およびイオン化
したアクセプタ１９を残して、この領域に位置したキャ
リアを排除していく。そして、正孔電流１６はソース電
極１０へ、また、電子電流１５はドレイン電極１２側へ
流れる。このため、これらのキャリアがｐｎ接合を充電
する充電電流としてソース電極１０へも流れ込む。そし
て、この充電電流によりソース層６、ベース層８および
ドレイン層１１により構成されるｎｐｎトランジスタが
導通状態となり、大きな電流が素子に流れ、電圧阻止能
力を失い素子破壊に至ることとなる。Thus, the resistance causes deterioration of the dynamic characteristics of the base layer. That is, when the element shifts from the conductive state to the non-conductive state, an external voltage is gradually applied between the source 10 and the drain 12 of the element. This voltage is p between the p-type base layer 8 and the n-type base layer 11.
Applied to the n-junction, the depletion layers 20 and 19 spread in each layer. Then, the depletion layers 19 and 20 spread as the voltage rises, leaving the ionized donor 18 and the ionized acceptor 19 to eliminate the carriers located in this region. Then, the hole current 16 flows to the source electrode 10 and the electron current 15 flows to the drain electrode 12 side. Therefore, these carriers also flow into the source electrode 10 as a charging current for charging the pn junction. Then, the charging current causes the npn transistor formed of the source layer 6, the base layer 8 and the drain layer 11 to be in a conductive state, and a large current flows through the element, resulting in loss of voltage blocking capability and destruction of the element. Becomes
【００１５】図８に、このターンオフ時の状態を説明す
るための等価回路を示してある。図７に示すＭＯＳＦＥ
Ｔにおいては、外部電源２１に負荷インダクタンス２４
を介してソース層６、ベース層８およびドレイン層１１
により構成されるｎｐｎトランジスタ１４が接続された
形となっている。そして、このトランジスタ１４のベー
スとエミッタの間にはベース層８の抵抗成分２３が、ま
た、ベースとコレクタとの間には、空乏層１９および２
０の接合容量２２が接続された形となっている。従っ
て、接合容量２２を充電する充電電流が抵抗成分２３に
流れると、この抵抗成分２３の電圧降下により、トラン
ジスタ１４のベース電位が上昇し、トランジスタ１４の
コレクタ・エミッタ間が導通状態となるのである。この
現象はラッチアップと呼ばれ、素子のターンオフ時に破
壊の原因となることがある。FIG. 8 shows an equivalent circuit for explaining the turn-off state. MOSFE shown in FIG.
At T, the load inductance 24 is added to the external power source 21.
Via the source layer 6, the base layer 8 and the drain layer 11
Is connected to the npn transistor 14 constituted by. The resistance component 23 of the base layer 8 is provided between the base and the emitter of the transistor 14, and the depletion layers 19 and 2 are provided between the base and the collector.
The junction capacitance 22 of 0 is connected. Therefore, when the charging current for charging the junction capacitance 22 flows through the resistance component 23, the base potential of the transistor 14 rises due to the voltage drop of the resistance component 23, and the collector-emitter of the transistor 14 becomes conductive. . This phenomenon is called latch-up, and it may cause damage when the element is turned off.
【００１６】このように、シリコンカーバイトを主たる
材料とする半導体装置においては、導通時の抵抗が低
く、また、耐熱性も高いなど多くの利点を有しながら、
ＭＯＳＦＥＴの閾値を一定に保つなどの条件からターン
オフ時の耐圧を高くとることが出来ないという問題があ
る。As described above, the semiconductor device containing silicon carbide as a main material has many advantages such as low resistance during conduction and high heat resistance.
There is a problem that the breakdown voltage at the time of turn-off cannot be made high due to the condition that the threshold value of the MOSFET is kept constant.
【００１７】そこで、本発明においては、上記の問題点
に鑑みて、シリコンカーバイトを主たる材料として用い
る絶縁ゲート型半導体装置のベース層の抵抗を低減する
ことによりターンオフ時の耐圧性能の保持された半導体
装置を実現することを目的としている。In view of the above problems, in the present invention, the withstand voltage performance at turn-off is maintained by reducing the resistance of the base layer of the insulated gate semiconductor device using silicon carbide as the main material. The purpose is to realize a semiconductor device.
【００１８】[0018]
【課題を解決するための手段】上記の課題を解決するた
めに、本発明においては、ベース領域の底部に局部的に
濃度の高い接合領域を形成するようにしている。すなわ
ち、本発明の第１の手段は、シリコンカーバイトを主た
る材料とする第２導電型ドレイン層と、該ドレイン層の
主面側に選択的に形成した第１導電型の高濃度ベース領
域と、前記ドレイン層及び前記高濃度ベース領域の上に
形成したシリコンカーバイトを主たる材料とする第２導
電型チャネル形成層と、前記チャネル形成層の主面に選
択的にゲート絶縁膜を介して形成したゲート電極と、前
記チャネル形成層内で前記高濃度ベース領域の直上に形
成した第２導電型のソース領域と、前記チャネル形成層
表面から前記高濃度ベース領域に達する露出部と、前記
ソース領域と前記高濃度ベース領域とに導電接触するソ
ース電極とを有し、耐圧３００Ｖ以上であることを特徴
とする。In order to solve the above problems, in the present invention, a junction region having a high concentration is locally formed at the bottom of the base region. That is, the first means of the present invention mainly uses silicon carbide.
A second conductivity type drain layer made of a material
High-concentration base region of the first conductivity type selectively formed on the main surface side
Area over the drain layer and the high concentration base region.
A second conductor whose main material is the formed silicon carbide
Electrical channel forming layer and the main surface of the channel forming layer.
Alternatively, a gate electrode formed through a gate insulating film
In the channel formation layer, a shape is formed immediately above the high concentration base region.
Formed second conductivity type source region and the channel formation layer
An exposed portion reaching from the surface to the high-concentration base region;
A conductive contact between the source region and the high concentration base region.
And a withstand voltage of 300 V or more .
【００１９】また、本発明の第２の手段は、シリコンカ
ーバイトを主たる材料とする第２導電型ドレイン層と、
該ドレイン層の主面側に選択的に形成した第１導電型の
高濃度ベース領域と、前記ドレイン層及び前記高濃度ベ
ース領域の上に形成したシリコンカーバイトを主たる材
料とする第２導電型チャネル形成層と、前記チャネル形
成層の主面に選択的にゲート絶縁膜を介して形成したゲ
ート電極と、前記チャネル形成層内で前記高濃度ベース
領域の直上に形成した第２導電型のソース領域と、前記
ソース領域及び前記高濃度ベース領域に接続する第１導
電型の高濃度領域と、前記ソース領域及び前記高濃度領
域に導電接触するソース電極とを有し、耐圧３００Ｖ以
上であることを特徴とする。 The second means of the present invention is a silicon mask.
A second conductive type drain layer mainly made of bite;
Of the first conductivity type selectively formed on the main surface side of the drain layer
The high-concentration base region, the drain layer, and the high-concentration base.
Main material is silicon carbide formed on the base area
Second conductive type channel forming layer as a material, and the channel type
A film formed selectively on the main surface of the layered structure through a gate insulating film.
Electrode and the high concentration base in the channel formation layer.
A second conductivity type source region formed immediately above the region;
A first conductor connected to the source region and the high concentration base region;
High-concentration region of electric type, the source region, and the high-concentration region
Source electrode in conductive contact with the region, withstand voltage of 300V or less
It is characterized by being above.
【００２０】また、製造方法として、シリコンカーバイ
トを主たる材料とする第２導電型ドレイン層の主面側に
選択的に第１導電型の高濃度ベース領域を形成する工程
と、前記ドレイン層および前記高濃度ベース領域の上に
シリコンカーバイトを主たる材料とする第２導電型チャ
ネル形成層を形成する工程と、前記第２導電型チャネル
形成層の主面上にゲート絶縁膜を介してゲート電極を形
成する工程と、前記第２導電型チャネル形成層内に前記
ゲート電極をマスクとしてイオン注入することにより第
２導電型のソース領域を前記高濃度ベース領域の直上に
形成する工程と、前記ソース領域を選択的に除去し前記
高濃度ベース領域の露出部を形成する工程と、前記ソー
ス領域及び前記高濃度ベース領域露出部に導電接触する
ソース電極を形成する工程とを有することを特徴とす
る。As a manufacturing method, silicon carbide is used.
On the main surface side of the second conductivity type drain layer whose main material is
Step of selectively forming a high-concentration base region of the first conductivity type
Over the drain layer and the high-concentration base region
Second conductivity type char mainly composed of silicon carbide
Forming a channel forming layer and the second conductivity type channel
Form the gate electrode on the main surface of the formation layer through the gate insulating film
And a step of forming in the second conductivity type channel forming layer.
By implanting ions using the gate electrode as a mask,
A two-conductivity type source region is provided directly above the high-concentration base region.
And a step of selectively removing the source region
Forming the exposed portion of the high-concentration base region,
Conductive contact with the exposed region and the high-concentration base region
And a step of forming a source electrode .
【００２１】他の製造方法として、シリコンカーバイト
を主たる材料とする第２導電型ドレイン層の主面側に選
択的に第１導電型の高濃度ベース領域を形成する工程
と、前記ドレイン層および前記高濃度ベース領域の上に
シリコンカーバイトを主たる材料とする第２導電型チャ
ネル形成層を形成する工程と、前記第２導電型チャネル
形成層の主面上にゲート絶縁膜を介してゲート電極を形
成する工程と、前記第２導電型チャネル形成層内に前記
ゲート電極をマスクとしてイオン注入することにより第
２導電型のソース領域を前記高濃度ベース領域の直上に
形成する工程と、前記ソース領域及び前記高濃度ベース
領域に接続する第１導電型の高濃度領域を形成する工程
と、前記ソース領域及び前記高濃度領域に導電接触する
ソース電極を形成する工程とを有することを特徴とす
る。As another manufacturing method, silicon carbide
Is selected as the main surface side of the second conductivity type drain layer whose main material is
Alternatively, a step of forming a high-concentration base region of the first conductivity type
Over the drain layer and the high-concentration base region
Second conductivity type char mainly composed of silicon carbide
Forming a channel forming layer and the second conductivity type channel
Form the gate electrode on the main surface of the formation layer through the gate insulating film
And a step of forming in the second conductivity type channel forming layer.
By implanting ions using the gate electrode as a mask,
A two-conductivity type source region is provided directly above the high-concentration base region.
Forming step, the source region and the high concentration base
Forming a high-concentration region of the first conductivity type connected to the region
And conductively contacts the source region and the high concentration region.
And a step of forming a source electrode .
【００２２】[0022]
【作用】シリコンカーバイトを主たる材料とする絶縁ゲ
ート型半導体装置において問題となる点は、上述したよ
うにチャネルを形成する閾値を一定に保つため、ベース
領域の抵抗を低くすることができないことである。従っ
て、ベース領域の表面に形成された第２導電型層を用い
て接合型の電界効果トランジスタを形成し、ターンオン
・ターンオフの機能を持たせることができる。従って、
第１導電型のベース領域を高濃度としても、チャネルを
形成する閾値には影響がなく、このため、高濃度のベー
ス領域を通じて充電電流を流すことが可能となり、３０
０Ｖ以上の高耐圧素子を提供できる。その結果、高濃度
のベース領域を流れる充電電流による電圧降下を小さく
抑えることができ、寄生トランジスタの動作を抑制し、
ラッチアップを防止することが可能となる。ソース電極
が高濃度のベース領域に直接導電接触しているので、ベ
ース抵抗の低減を図ることができる。 A problem in the insulated gate semiconductor device mainly made of silicon carbide is that the threshold value for forming the channel is kept constant as described above, so that the resistance of the base region cannot be lowered. is there. Therefore, the second conductivity type layer formed on the surface of the base region is used.
To form a junction field effect transistor and turn it on.
-It can have a turn-off function. Therefore,
Even if the concentration of the first conductivity type base region is high,
It has no effect on the threshold that forms, and as a result, it does not
It becomes possible to pass the charging current through
It is possible to provide a high breakdown voltage element of 0 V or higher. As a result, high concentration
The voltage drop due to the charging current flowing through the base region of
Can be suppressed, suppress the operation of the parasitic transistor,
It becomes possible to prevent latch-up. Source electrode
Is in direct conductive contact with the high-concentration base region,
The ground resistance can be reduced.
【００２３】[0023]
【００２４】[0024]
【００２５】[0025]
【００２６】ソース電極を高濃度ベース領域に直接導電
接触させずに、ソース領域及び高濃度ベース領域に接続
する第１導電型の高濃度領域を形成し、ソース領域及び
高濃度領域に導電接触するソース電極を設けた構成にお
いても、高濃度領域によりベース抵抗の低減を図ること
ができる。A high-concentration region of the first conductivity type connected to the source region and the high-concentration base region is formed without directly contacting the source electrode with the high-concentration base region.
Also in the structure in which a source electrode conductively contacting the high density region, it is possible to reduce the base resistance by the high concentration region.
【００２７】[0027]
【実施例】以下に図面を参照して、本発明の実施例を説
明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２８】〔参考例〕
図１に参考例に係る絶縁ゲート型半導体装置の構造を示
してある。本装置はシリコンカーバイトを主たる半導体
材料として構成されており、先ず、ドレイン電極１２が
裏面に接続されるｎ+ 型の半導体基板５の表面にエピタ
キシャル成長させたｎ- 型の第１のドレイン層４が形成
されている。そして、この第１のドレイン層４上にエピ
タキシャル成長によりｎ- 型の第２のドレイン層３が形
成されている。この第２のドレイン層３のドナー濃度
は、第１のドレイン層４より低くなるように調整されて
おり、さらに、第２のドレイン層の厚さも１μｍ前後と
できるだけ薄く形成されている。また、第１のドレイン
層４上には、高濃度であるｐ+ 型の埋め込み層９が形成
されている。そして、この埋め込み層９の上部に、第２
のドレイン層３を用いて形成されたｐ型のベース層８が
構成されている。このｐ型のベース層８内の表面部分に
は、ｎ+ 型のソース層６が、また、ベース層８の中心部
分にはｐ+ 型のウェル７が形成されている。そして、ソ
ース層６からウェル７にかけてソース電極１０が接続さ
れており、さらに、ソース層６の端部からベース層８の
表面、第２のドレイン層３の表面に亘って、ゲート酸化
膜２を介してゲート電極が設置されている。なお、本例
のＭＯＳＦＥＴの導通状態は、先に説明した従来のＭＯ
ＳＦＥＴと同様につき説明を省略する。 Reference Example FIG. 1 shows the structure of an insulated gate semiconductor device according to a reference example . This device is mainly composed of silicon carbide. First, the n − -type first drain layer 4 epitaxially grown on the surface of the n + -type semiconductor substrate 5 to which the drain electrode 12 is connected to the back surface. Are formed. Then, the n − -type second drain layer 3 is formed on the first drain layer 4 by epitaxial growth. The donor concentration of the second drain layer 3 is adjusted to be lower than that of the first drain layer 4, and the thickness of the second drain layer is also formed as thin as about 1 μm. Further, a high-concentration p + -type buried layer 9 is formed on the first drain layer 4. Then, the second layer is formed on the buried layer 9.
The p-type base layer 8 is formed by using the drain layer 3 of FIG. An n + type source layer 6 is formed on the surface of the p type base layer 8, and a p + type well 7 is formed on the center of the base layer 8. The source electrode 10 is connected from the source layer 6 to the well 7, and the gate oxide film 2 is further formed from the end of the source layer 6 to the surface of the base layer 8 and the surface of the second drain layer 3. A gate electrode is installed through. The conduction state of the MOSFET of this example is the same as that of the conventional MO described above.
The description is omitted because it is similar to the SFET.
【００２９】このような構成の本装置において、ターン
オフ時にソース電極１０とドレイン電極１２に電位差が
生ずると、ベース層８と第２のドレイン層３とのｐｎ接
合部および埋め込み層９と第１のドレイン層４とのｐｎ
接合部に空乏層が形成される。そして、主に埋め込み層
９と第１のドレイン層４とのｐｎ接合部から充電電流が
ソース電極１０に向かって流れる。これは、流れる電流
の総量が空乏層中のイオン化したドナーまたはアクセプ
タの総量に等しいためである。電圧Ｖが印加されている
ときの空乏層中のイオンの総量は以下の式により近似さ
れる。In this device having such a structure, when a potential difference is generated between the source electrode 10 and the drain electrode 12 at the time of turn-off, the pn junction between the base layer 8 and the second drain layer 3, the buried layer 9 and the first layer. Pn with drain layer 4
A depletion layer is formed at the junction. Then, a charging current mainly flows from the pn junction between the buried layer 9 and the first drain layer 4 toward the source electrode 10. This is because the total amount of current flowing is equal to the total amount of ionized donors or acceptors in the depletion layer. The total amount of ions in the depletion layer when the voltage V is applied is approximated by the following equation.
【００３０】[0030]
【数３】 [Equation 3]
【００３１】ここで、ρはイオン密度であり、Ｎはイオ
ンの総量である。つまり、イオン密度が小さいほどイオ
ンの総量も少なく、充電電流も少なくなるのである。本
装置においては、ベース層８のアクセプタ濃度は、埋め
込み層９に比べて低く、さらに、第２のドレイン層３の
ドナー濃度は、第１のドレイン層４のドナー濃度に比べ
て低い。従って、ベース層８と第２のドレイン層３との
ｐｎ接合部に広がる空乏層からの充電電流は、埋め込み
層９と第１のドレイン層４とのｐｎ接合部に空乏層から
の充電電流に比べて非常に小さくなる。Here, ρ is the ion density and N is the total amount of ions. That is, the smaller the ion density, the smaller the total amount of ions and the smaller the charging current. In this device, the acceptor concentration of the base layer 8 is lower than that of the buried layer 9, and the donor concentration of the second drain layer 3 is lower than that of the first drain layer 4. Therefore, the charging current from the depletion layer spreading in the pn junction between the base layer 8 and the second drain layer 3 becomes the charging current from the depletion layer in the pn junction between the buried layer 9 and the first drain layer 4. It is very small in comparison.
【００３２】このように、本装置においては、埋め込み
層９と第１のドレイン層４とのｐｎ接合部から主に充電
電流が流れ、その充電電流の多くが流れる埋め込み層９
は高濃度の拡散層であるため、抵抗値は低くなってい
る。さらに、本装置においては、ベース層８の内部にア
クセプタ濃度の高いウェル７が形成されているので、埋
め込み層９からの充電電流がソース電極１０に流れる経
路全体において抵抗値が低くなるように設計されてい
る。従って、充電電流がベース層を流れることに起因す
る電圧降下を低減することが可能となり、ソース層１
０、ベース層８およびドレイン層３、４により構成され
る寄生トランジスタを導通状態とするような不具合を避
けることができる。従って、本装置においては、ターン
オフ時に寄生トランジスタがオンとなり、過剰の電流が
流れることによる素子破壊発生を防止することができ
る。As described above, in this device, the charging current mainly flows from the pn junction between the buried layer 9 and the first drain layer 4, and most of the charging current flows through the buried layer 9.
Is a high-concentration diffusion layer, and has a low resistance value. Furthermore, in this device, since the well 7 having a high acceptor concentration is formed inside the base layer 8, the resistance value is designed to be low in the entire path through which the charging current from the buried layer 9 flows to the source electrode 10. Has been done. Therefore, it becomes possible to reduce the voltage drop caused by the charging current flowing through the base layer, and the source layer 1
It is possible to avoid such a problem that a parasitic transistor constituted by 0, the base layer 8 and the drain layers 3 and 4 becomes conductive. Therefore, in the present device, the parasitic transistor is turned on at the time of turn-off, and it is possible to prevent the occurrence of element destruction due to an excessive current flowing.
【００３３】このように、本装置においては、チャネル
形成の閾値には影響を与えずにターンオフ時の電流を抵
抗の低い高濃度の拡散層を経由して流すことにより、ベ
ース層における電圧降下を抑制することができる。従っ
て、最大電界強度（Ｅｍ）が大きく、導通時の抵抗Ｒｏ
ｎおよびスイッチング速度ｔf の大幅な改善が見込まれ
るシリコンカーバイトを半導体材料として用いながら、
問題であったターンオフ時の耐圧性能を向上することが
可能となる。As described above, in the present device, the voltage at the base layer is reduced by causing the current at turn-off to flow through the high-concentration diffusion layer having a low resistance without affecting the channel formation threshold value. Can be suppressed. Therefore, the maximum electric field strength (Em) is large and the resistance Ro during conduction is high.
While using silicon carbide as a semiconductor material, which is expected to significantly improve n and switching speed t f ,
It is possible to improve the breakdown voltage performance at the time of turn-off, which was a problem.
【００３４】不純物の拡散係数の小さいシリコンカーバ
イトを用いて本例のような半導体装置を形成するうえ
で、問題となる点に、高濃度の埋め込み型の拡散層を形
成することがある。そして、本例の装置においては、こ
の点を２層のドレイン層、すなわち、第１のドレイン層
３および第２のドレイン層４を順次形成することによ
り、高濃度の埋め込み型の拡散層の形成を容易としてい
る。When forming a semiconductor device like this example using silicon carbide having a small diffusion coefficient of impurities, a problem is that a high-concentration buried diffusion layer is formed. Then, in the device of this example, a high-concentration buried diffusion layer is formed by sequentially forming two drain layers, that is, the first drain layer 3 and the second drain layer 4 at this point. Is easy.
【００３５】図２に、本例の装置を製造する工程の一例
を示してある。先ず、図２（ａ）に示すように、ｎ+ 型
の半導体基板５上にエビタキシャル成長させたｎ- 型の
第１のドレイン層４に高濃度で低抵抗のｐ+ 型層９を部
分的に拡散などの方法で形成する。次に、図２（ｂ）に
示すように、この第１のドレイン層４上にｎ- 型の第２
のドレイン層３をエピタキシャル成長により形成する。
このように、ドレイン層を２層に分けて形成することに
より、深い高濃度の埋め込み層を容易に形成することが
できる。なお、第２のドレイン層３は、上述したよう
に、なるべく薄い方が良く、本例においては、約１μｍ
程度としてある。これは、この層厚が後述するｐ型ベー
ス層８から空乏層が広がる範囲となるため、層厚が少な
い程、空乏層領域を限定することが可能であり、充電電
流の減少を図ることができるからである。FIG. 2 shows an example of steps for manufacturing the device of this example. First, as shown in FIG. 2A, a high concentration and low resistance p + -type layer 9 is partially formed on the n − -type first drain layer 4 which is epitaxially grown on the n + -type semiconductor substrate 5. It is formed by a method such as diffusion. Next, as shown in FIG. 2B, an n − -type second layer is formed on the first drain layer 4.
The drain layer 3 is formed by epitaxial growth.
Thus, by forming the drain layer in two layers, a deep high-concentration buried layer can be easily formed. The second drain layer 3 is preferably as thin as possible as described above, and in this example, it is about 1 μm.
There is as a degree. This is because the layer thickness is in the range where the depletion layer spreads from the p-type base layer 8 which will be described later. Therefore, the thinner the layer thickness, the more the depletion layer region can be limited, and the charge current can be reduced. Because you can.
【００３６】次に、図２（ｃ）に示すように、上記にて
形成したシリコンカーバイト製の半導体基板上にゲート
絶縁膜２およびゲート電極１を形成する。そして、図２
（ｄ）に示すように、このゲート電極１をマスクとして
ｐ型のベース層８およびｎ+型のソース層６を形成す
る。さらに、ソース層６およびベース層８に接続される
ソース電極１０と、埋め込み層９との間の抵抗を下げる
ために、ベース層８内部にｐ+ 型のウェル領域７を形成
する。また、ベース層８と第２のドレイン層３との間に
広がる空乏層からの充電電流を低減するために、第２の
ドレイン層３の不純物濃度を第１のドレイン層４より低
下させた方が良いことは、上記にて説明した通りであ
る。Next, as shown in FIG. 2C, a gate insulating film 2 and a gate electrode 1 are formed on the semiconductor substrate made of silicon carbide formed above. And FIG.
As shown in (d), the gate electrode 1 is used as a mask to form a p-type base layer 8 and an n + -type source layer 6. Further, in order to reduce the resistance between the source electrode 10 connected to the source layer 6 and the base layer 8 and the buried layer 9, a p + type well region 7 is formed inside the base layer 8. Further, in order to reduce the charging current from the depletion layer extending between the base layer 8 and the second drain layer 3, the impurity concentration of the second drain layer 3 should be lower than that of the first drain layer 4. Is good as described above.
【００３７】〔実施例１〕
図３に本実施例に係る絶縁ゲート型半導体装置の構造を
示してある。本装置も参考例と同様に、シリコンカーバ
イトを主たる半導体材料として構成されている。また、
ドレイン電極１２が裏面に接続されるｎ+ 型の半導体基
板５の表面にエピタキシャル成長させたｎ- 型のドレイ
ン層４が形成されている点も参考例と同様である。本例
の装置において着目すべき点は、このドレイン層４の上
に高濃度であるｐ+ 型のベース層３０が形成されている
ことである。さらに、このベース層３０の表面に形成さ
れたｎ+ 型のソース層６からドレイン層４に亘って、ｎ
型のチャネル形成層３１が形成されていることである。
そして、このチャネル形成層３１の上にゲート酸化膜２
を介してゲート電極が設置されている。 [Embodiment 1] FIG. 3 shows the structure of an insulated gate semiconductor device according to the present embodiment. Like the reference example , this device is also composed of silicon carbide as a main semiconductor material. Also,
Similar to the reference example , the epitaxially grown n − -type drain layer 4 is formed on the surface of the n + -type semiconductor substrate 5 to which the drain electrode 12 is connected to the back surface. The point to be noted in the device of this example is that the high-concentration p + -type base layer 30 is formed on the drain layer 4. Further, from the n + type source layer 6 formed on the surface of the base layer 30 to the drain layer 4, n
That is, the channel forming layer 31 of the mold is formed.
Then, the gate oxide film 2 is formed on the channel forming layer 31.
A gate electrode is installed through.
【００３８】チャネルが形成される部分を拡大して示し
た図４に基づき、本装置の動作を説明する。本例の装置
は、チャネル形成層３１を用いて、いわゆる接合型電界
効果トランジスタ（ＪＦＥＴ）を形成したものである。
先ず、ゲート電極４にソース電極１０に対し正または小
さな値の負の電位が制御電源２８から印加されている場
合は、チャネル形成層３１の表面からベース層３０に向
かって形成される空乏層３６の広がりは小さい。従っ
て、ソース層６からの電子は、この空乏層３６と、ベー
ス層３０から広がる空乏層３５との間の経路３７を通っ
てドレイン層４へ流れる。The operation of the present apparatus will be described with reference to FIG. 4, which is an enlarged view of a portion where a channel is formed. In the device of this example, a so-called junction field effect transistor (JFET) is formed using the channel forming layer 31.
First, when a positive or negative negative potential with respect to the source electrode 10 is applied to the gate electrode 4 from the control power supply 28, the depletion layer 36 formed from the surface of the channel forming layer 31 toward the base layer 30. Spread is small. Therefore, the electrons from the source layer 6 flow to the drain layer 4 through the path 37 between the depletion layer 36 and the depletion layer 35 extending from the base layer 30.
【００３９】ゲート電極４に印加される負の電位を大き
くしていくと、空乏層３６はベース層３０に向かって広
がって行き電子の通路は狭くなる。そして、ついに、ベ
ース層３０から広がる空乏層３５と接続するピンチオフ
の状態となると、電子の通路はなくなるので、電子は流
れなくなり、本装置はターンオフの状態となる。オフ状
態で、ドレイン電極１２とソース電極１０との電位差が
大きくなると、ベース層３０から空乏層３５が広がり充
電電流が流れ、従来の装置では問題となっている。しか
し、本例の装置においては、ベース層３０を高濃度に設
定してあるので、充電電流によりベース層３０の電位が
高くなることはなく、ソース層６、ベース層３０および
ドレイン層４により構成される寄生トランジスタがオン
となることはない。従って、ターンオフ時のラッチアッ
プを防止することができる。As the negative potential applied to the gate electrode 4 is increased, the depletion layer 36 expands toward the base layer 30 and the electron passage narrows. Then, finally, when the pinch-off state in which the depletion layer 35 extending from the base layer 30 is connected is reached, the passage of electrons is lost, so that electrons do not flow and the device is turned off. When the potential difference between the drain electrode 12 and the source electrode 10 increases in the off state, the depletion layer 35 expands from the base layer 30 and a charging current flows, which is a problem in the conventional device. However, in the device of this example, since the base layer 30 is set to a high concentration, the potential of the base layer 30 does not increase due to the charging current, and the source layer 6, the base layer 30, and the drain layer 4 are used. The parasitic transistor is not turned on. Therefore, it is possible to prevent latch-up at turn-off.
【００４０】この素子のオン・オフは、上述したよう
に、ｎ型の領域であるチャネル形成層３１に広がる空乏
層３６により制御される。従って、本装置のゲート電位
の閾値Ｖｔは、チャネル形成層３１の厚さ、ドナー濃度
によって決定される。例えば、閾値Ｖｔとして空乏層３
６がチャネル形成層３１の厚さだけ広がった値を採用す
ると、Ｖｔは以下の式で表される。On / off of this element is controlled by the depletion layer 36 spreading in the channel forming layer 31 which is an n-type region as described above. Therefore, the threshold value Vt of the gate potential of this device is determined by the thickness of the channel formation layer 31 and the donor concentration. For example, as the threshold value Vt, the depletion layer 3
When the value of 6 is expanded by the thickness of the channel forming layer 31, Vt is represented by the following formula.
【００４１】[0041]
【数４】 [Equation 4]
【００４２】ここで、ｑは素電荷、Ｎｄはチャネル形成
層３１のドナー濃度、Ｗはチャネル形成層３１の厚さ、
Ｅｉはゲート絶縁膜２の誘電率、Ｅｓは半導体の誘電率
を示す。なお、電界電荷は無視している。この式を用い
て、例えば、ｄ＝１０００Å（ＳｉＯ2 ）、Ｗ＝０．１
μｍ、Ｎｄ＝１０16ｃｍ-3とすると、閾値Ｖｔとして略
１．２Ｖという値を得ることができ、シリコンを用いた
半導体装置と同様に取り扱うことができることが判る。
なお、本装置がオフするに従ってドレイン電極側の電圧
が上昇し、ベース層３０からの空乏層３５がさらに広が
ることから、閾値Ｖｔは上記の値より小さくなる。Here, q is the elementary charge, Nd is the donor concentration of the channel forming layer 31, W is the thickness of the channel forming layer 31, and
Ei represents the dielectric constant of the gate insulating film 2, and Es represents the dielectric constant of the semiconductor. The electric field charge is ignored. Using this formula, for example, d = 1000Å (SiO 2 ), W = 0.1
When μm and Nd = 10 16 cm −3 , a value of about 1.2 V can be obtained as the threshold value Vt, and it can be understood that it can be handled in the same manner as a semiconductor device using silicon.
The threshold voltage Vt becomes smaller than the above value because the drain electrode side voltage rises as the device turns off and the depletion layer 35 from the base layer 30 further spreads.
【００４３】図５および６に、本例の装置を製造する工
程の一例を示してある。先ず、図５（ａ）に示すよう
に、ｎ+ 型の半導体基板５上にエビタキシャル成長させ
たｎ-型のドレイン層４が形成されたＳｉＣ基板を用い
る。そして、このドレイン層４の表面に、フォトレジス
ト３２によりパターンを形成し、その上からｐ型不純物
イオン３３を注入し、高濃度で低抵抗のｐ+ 型層３０を
形成するためのｐ型不純物を導入する。勿論、このｐ+
型層３０をなるべく低抵抗とするために、その他の方
法、例えば、気相拡散あるいはエピタキシャル成長など
によって形成しても良い。FIGS. 5 and 6 show an example of steps for manufacturing the device of this example. First, as shown in FIG. 5A, a SiC substrate in which an n − type drain layer 4 that has been epitaxially grown on an n + type semiconductor substrate 5 is formed is used. Then, a pattern is formed on the surface of the drain layer 4 with a photoresist 32, p-type impurity ions 33 are implanted from above, and a p-type impurity for forming a high-concentration and low-resistance p + -type layer 30 is formed. To introduce. Of course, this p +
In order to reduce the resistance of the mold layer 30 as much as possible, it may be formed by another method, for example, vapor phase diffusion or epitaxial growth.
【００４４】次に、図５（ｂ）に示すように、イオン注
入で導入した不純物を熱処理により活性化しｐ+ 型層３
０を形成する。そして、図５（ｃ）に示すように、ｐ+
型層３０が形成された上に、さらにｎ領域３１を一様に
エピタキシャル成長により形成する。このｎ領域により
チャネル形成層３１が構成されるが、不純物濃度は１０
15〜１０18ｃｍ-3程度、厚さは０．１〜数μｍ程度が実
現しうる値である。Next, as shown in FIG. 5B, the impurities introduced by ion implantation are activated by heat treatment to activate the p + -type layer 3
Form 0. Then, as shown in FIG. 5C, p +
On the mold layer 30, the n region 31 is further uniformly formed by epitaxial growth. The n region constitutes the channel forming layer 31, but the impurity concentration is 10
A value that can be realized is about 15 to 10 18 cm −3 and a thickness of about 0.1 to several μm.
【００４５】次に、図６（ａ）に示すように、ゲート絶
縁膜２およびゲート電極１を形成して、パターニングを
行う。ＳｉＣは熱酸化することによりＳｉＯ2 が成長で
きるので、絶縁膜２としてはこのＳｉＯ2 を用いること
が望ましい。そして、図６（ｂ）に示すように、ゲート
電極１をマスクとして、イオン注入法あるいは気相拡散
法などによりｎ+ 型のソース層６を形成する。その後、
図６（ｃ）に示すように、ソース層６を部分的に掘っ
て、ベース層３０を露出させ、ソース電極との接合が可
能なようにしている。勿論、図６（ｂ）に示す工程にお
いて、ソース層６の一部に表面からｐ+ 型の拡散を形成
し、ベース層３０と接合させることによっても、ソース
電極とベース層３０を接続することも可能である。この
ようにして形成された半導体装置に、電極を形成して本
例の装置は完成する。Next, as shown in FIG. 6A, the gate insulating film 2 and the gate electrode 1 are formed and patterned. Since SiC can grow SiO 2 by thermal oxidation, it is desirable to use this SiO 2 as the insulating film 2. Then, as shown in FIG. 6B, using the gate electrode 1 as a mask, an n + type source layer 6 is formed by an ion implantation method or a vapor phase diffusion method. afterwards,
As shown in FIG. 6C, the source layer 6 is partially dug to expose the base layer 30 so that the source layer 6 can be joined to the source electrode. Of course, in the step shown in FIG. 6B, the source electrode and the base layer 30 can be connected by forming a p + -type diffusion from the surface in a part of the source layer 6 and joining it to the base layer 30. Is also possible. Electrodes are formed on the semiconductor device thus formed to complete the device of this example.
【００４６】なお、上記実施例１において、半導体基板
の裏面にドレイン電極が設置され、表面にソース電極が
設置された縦型のパワーデバイスに基づき説明したが、
同じ面にドレイン電極およびソース電極が設置される横
型のパワーデバイスにおいても、上記実施例と同様の構
成により低導通抵抗および高速スイッチングが可能で、
ターンオフ時の耐圧性能の高いデバイスを実現すること
ができる。そして、装置の小型化、軽量化など、近年パ
ワーデバイスに要求される種々の性能を備えたものを実
現することが可能となる。また、上記の実施例は、ＭＯ
ＳＦＥＴに基づき説明してきたが、本発明に係る技術
は、ＩＧＢＴ、ＭＣＴなどのすべての絶縁ゲート型半導
体装置に適用可能なものである。In the first embodiment , the description has been given based on the vertical power device in which the drain electrode is installed on the back surface of the semiconductor substrate and the source electrode is installed on the front surface.
Even in a horizontal power device in which the drain electrode and the source electrode are installed on the same surface, low conduction resistance and high-speed switching are possible with the same configuration as the above embodiment,
It is possible to realize a device having high breakdown voltage performance at turn-off. Then, it is possible to realize devices having various performances required for power devices in recent years, such as downsizing and weight reduction of devices. In addition, the above embodiment is based on MO
Although the description has been given based on the SFET, the technique according to the present invention is applicable to all insulated gate type semiconductor devices such as IGBT and MCT.
【００４７】[0047]
【発明の効果】以上に説明したように、本発明に係る絶
縁ゲート型半導体装置においては、最大電界強度（Ｅ
ｍ）が大きく、導通時の抵抗Ｒｏｎおよびスイッチング
速度ｔfの大幅な改善が見込まれるうえ、耐熱特性の良
好なシリコンカーバイトを、半導体材料として採用する
うえで問題となっていたターンオフ時の耐圧性能を、埋
め込み高濃度領域を形成することにより解決している。 As described above, in the insulated gate semiconductor device according to the present invention, the maximum electric field strength (E
m) is large, resistance Ron at conduction and switching speed tf are expected to be greatly improved, and withstand voltage performance at turn-off has been a problem when adopting silicon carbide with good heat resistance as a semiconductor material. Buried
The problem is solved by forming a high-density embedded region.
【００４８】特に、ベース領域の表面に形成されたチャ
ネル形成層を用いて接合型の電界効果トランジスタを形
成し、ターンオン・ターンオフの機能を持たせることが
できる。従って、第１導電型のベース領域を高濃度とし
ても、チャネルを形成する閾値には影響がなく、このた
め、高濃度のベース領域を通じて充電電流を流すことが
可能となる。その結果、高濃度のベース領域を流れる充
電電流による電圧降下を小さく抑えることができ、寄生
トランジスタの動作を抑制し、ラッチアップを防止する
ことが可能となり、３００Ｖ以上の高耐圧素子を提供で
きる。ソース電極が高濃度のベース領域に直接導電接触
しているので、ベース抵抗の低減を図ることができる。[0048] In particular, tea formed on the surface of the base region
A junction-type field effect transistor can be formed by using the flannel forming layer to have a turn-on / turn-off function. Therefore, even if the first-conductivity-type base region is made to have a high concentration, it does not affect the threshold value for forming the channel, so that the charging current can be passed through the high-concentration base region. As a result, the voltage drop due to the charging current flowing through the high-concentration base region can be suppressed small, the operation of the parasitic transistor can be suppressed, and the latch-up can be prevented, so that a high withstand voltage element of 300 V or more can be provided. Since the source electrode is in direct conductive contact with the high-concentration base region, the base resistance can be reduced.
【００４９】このように、本発明に係る構成の半導体装
置を用いることにより、シリコンカーバイトの特性を活
かしたパワーデバイスを実現することが可能となり、高
性能で小型、軽量の絶縁ゲート型半導体装置を提供する
ことが可能となる。そして、本発明に係るパワーデバイ
スを用いることにより、各種装置の小型、軽量、さらに
省電力化に寄与することができる。As described above, by using the semiconductor device having the structure according to the present invention, it becomes possible to realize a power device which makes use of the characteristics of silicon carbide, and a high performance, small size and lightweight insulated gate type semiconductor device. Can be provided. Then, by using the power device according to the present invention, it is possible to contribute to the reduction in size and weight of various devices and further to the power saving.
【図１】本発明の参考例に係る絶縁ゲート型半導体装置
の構成を示す断面図である。FIG. 1 is a sectional view showing a configuration of an insulated gate semiconductor device according to a reference example of the present invention.
【図２】図１に示す絶縁ゲート型半導体装置の製造過程
を示す断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process of the insulated gate semiconductor device shown in FIG.
【図３】本発明の実施例１に係る絶縁ゲート型半導体装
置の構成を示す断面図である。FIG. 3 is a sectional view showing a configuration of an insulated gate semiconductor device according to a first embodiment of the present invention.
【図４】図３に示す絶縁ゲート型半導体装置のチャネル
形成層に係る部分を拡大して示す断面図である。4 is an enlarged cross-sectional view showing a portion related to a channel formation layer of the insulated gate semiconductor device shown in FIG.
【図５】図３に示す絶縁ゲート型半導体装置の製造過程
の前半を示す断面図である。5 is a cross-sectional view showing the first half of the manufacturing process of the insulated gate semiconductor device shown in FIG.
【図６】図３に示す絶縁ゲート型半導体装置の製造過程
の後半を示す断面図である。6 is a cross-sectional view showing the latter half of the manufacturing process of the insulated gate semiconductor device shown in FIG.
【図７】従来の絶縁ゲート型半導体装置の動作を説明す
るための概略構成図である。FIG. 7 is a schematic configuration diagram for explaining the operation of a conventional insulated gate semiconductor device.
【図８】図７に示す絶縁ゲート型半導体装置の等価回路
を示す回路図である。8 is a circuit diagram showing an equivalent circuit of the insulated gate semiconductor device shown in FIG.
１ ・・・ ゲート電極 ２ ・・・ ゲート絶縁膜 ３ ・・・ ｎ- 型の第２のドレイン層 ４ ・・・ ｎ- 型の第１のドレイン層 ５ ・・・ ｎ+ 型の半導体基板 ６ ・・・ ｎ+ 型のソース層 ７ ・・・ ｐ+ 型のウェル領域 ８ ・・・ ｐ型のベース層 ９ ・・・ ｐ+ 型の埋め込み層 １０・・・ ソース電極 １１・・・ ドレイン層 １２・・・ ドレイン電極 １４・・・ ｎｐｎトランジスタ １５・・・ 電子電流 １６・・・ 正孔電流 １７・・・ イオン化したドナー １８・・・ イオン化したアクセプタ １９、２０・・・ 空乏層 ３０・・・ ｐ+ 型のベース層 ３１・・・ ｎ型のチャネル形成層 ３２・・・ フォトレジスト ３３・・・ ｐ型不純物イオン ３４・・・ ｐ型不純物 ３５、３６・・・ 空乏層 ３７・・・ 電子電流の経路 ３８・・・ 制御電源DESCRIPTION OF SYMBOLS 1 ... Gate electrode 2 ... Gate insulating film 3 ... N < - > type 2nd drain layer 4 ... N < - > type 1st drain layer 5 ... N <+> type semiconductor substrate 6 ... n + type source layer 7 ... p + type well region 8 ... p type base layer 9 ... p + type buried layer 10 ... source electrode 11 ... drain layer 12 ... Drain electrode 14 ... Npn transistor 15 ... Electron current 16 ... Hole current 17 ... Ionized donor 18 ... Ionized acceptor 19, 20 ... Depletion layer 30 ... P + type base layer 31 n type channel forming layer 32 photoresist 33 p type impurity ions 34 p type impurities 35, 36 depletion layer 37 Electronic current path 38 ... Control power supply
Claims (4)
２導電型ドレイン層と、該ドレイン層の主面側に選択的
に形成した第１導電型の高濃度ベース領域と、前記ドレ
イン層及び前記高濃度ベース領域の上に形成したシリコ
ンカーバイトを主たる材料とする第２導電型チャネル形
成層と、前記チャネル形成層の主面に選択的にゲート絶
縁膜を介して形成したゲート電極と、前記チャネル形成
層内で前記高濃度ベース領域の直上に形成した第２導電
型のソース領域と、前記チャネル形成層表面から前記高
濃度ベース領域に達する露出部と、前記ソース領域と前
記高濃度ベース領域とに導電接触するソース電極とを有
し、耐圧３００Ｖ以上であることを特徴とする絶縁ゲー
ト型半導体装置。1. A method using silicon carbide as a main material.
Two-conductivity type drain layer and selective to the main surface side of the drain layer
A high-concentration base region of the first conductivity type formed on the substrate, and the drain.
Silicon layer formed on the in layer and the high-concentration base region
Second conductivity type channel type with carbite as the main material
Gate isolation is selectively formed on the main surface of the layer and the channel formation layer.
Gate electrode formed through the edge film and the channel formation
A second conductive layer formed immediately above the high-concentration base region in the layer
From the source region of the mold and the surface of the channel forming layer.
The exposed portion reaching the concentration base region, the source region and the front
With a source electrode in conductive contact with the high-concentration base region
An insulated gate semiconductor device having a withstand voltage of 300 V or more .
２導電型ドレイン層と、該ドレイン層の主面側に選択的
に形成した第１導電型の高濃度ベース領域と、前記ドレ
イン層及び前記高濃度ベース領域の上に形成したシリコ
ンカーバイトを主たる材料とする第２導電型チャネル形
成層と、前記チャネル形成層の主面に選択的にゲート絶
縁膜を介して形成したゲート電極と、前記チャネル形成
層内で前記高濃度ベース領域の直上に形成した第２導電
型のソース領域と、前記ソース領域及び前記高濃度ベー
ス領域に接続する第１導電型の高濃度領域と、前記ソー
ス領域及び前記高濃度領域に導電接触するソース電極と
を有し、耐圧３００Ｖ以上であることを特徴とする絶縁
ゲート型半導体装置。2. A method using silicon carbide as a main material.
Two-conductivity type drain layer and selective to the main surface side of the drain layer
A high-concentration base region of the first conductivity type formed on the substrate, and the drain.
Silicon layer formed on the in layer and the high-concentration base region
Second conductivity type channel type with carbite as the main material
Gate isolation is selectively formed on the main surface of the layer and the channel formation layer.
Gate electrode formed through the edge film and the channel formation
A second conductive layer formed immediately above the high-concentration base region in the layer
The source region of the mold, the source region and the high concentration bain.
A high-concentration region of the first conductivity type connected to the source region and the saw.
And a source electrode in conductive contact with the high concentration region and
And a withstand voltage of 300 V or more .
２導電型ドレイン層の主面側に選択的に第１導電型の高
濃度ベース領域を形成する工程と、前記ドレイン層およ
び前記高濃度ベース領域の上にシリコンカーバイトを主
たる材料とする第２導電型チャネル形成層を形成する工
程と、前記第２導電型チャネル形成層の主面上にゲート
絶縁膜を介してゲート電極を形成する工程と、前記第２
導電型チャネル形成層内に前記ゲート電極をマスクとし
てイオン注入することにより第２導電型のソース領域を
前記高濃度ベース領域の直上に形成する工程と、前記ソ
ース領域を選択的に除去し前記高濃度ベース領域の露出
部を形成する工程と、前記ソース領域及び前記高濃度ベ
ース領域露出部に導電接触するソース電極を形成する工
程とを有することを特徴とする絶縁ゲート型半導体装置
の製造方法。3. A method using silicon carbide as a main material.
The second conductivity type drain layer is selectively formed on the main surface side with a high conductivity of the first conductivity type.
Forming a concentration base region, the drain layer and
And silicon carbide on top of the high-concentration base area
A process for forming a second conductivity type channel forming layer using a barrel material
And a gate on the main surface of the second conductivity type channel forming layer.
A step of forming a gate electrode via an insulating film, and the second step
Using the gate electrode as a mask in the conductivity type channel formation layer
The second conductivity type source region by ion implantation
Forming directly above the high concentration base region, and
Of the high concentration base region by selectively removing the source region
A step of forming a portion, the source region and the high concentration layer.
Process to form a source electrode in conductive contact with the exposed area
Insulated gate type semiconductor device characterized by having
Manufacturing method .
２導電型ドレイン層の主面側に選択的に第１導電型の高
濃度ベース領域を形成する工程と、前記ドレイン層およ
び前記高濃度ベース領域の上にシリコンカーバイトを主
たる材料とする第２導電型チャネル形成層を形成する工
程と、前記第２導電型チャネル形成層の主面上にゲート
絶縁膜を介してゲート電極を形成する工程と、前記第２
導電型チャネル形成層内に前記ゲート電極をマスクとし
てイオン注入することにより第２導電型のソース領域を
前記高濃度ベース領域の直上に形成する工程と、前記ソ
ース領域及び前記高濃度ベース領域に接続する第１導電
型の高濃度領域を形成する工程と、前記ソース領域及び
前記高濃度領域に導電接触するソース電極を形成する工
程とを有することを特徴とする絶縁ゲート型半導体装置
の製造方法。4. A silicon carbide as a main material
The second conductivity type drain layer is selectively formed on the main surface side with a high conductivity of the first conductivity type.
Forming a concentration base region, the drain layer and
And silicon carbide on top of the high-concentration base area
A process for forming a second conductivity type channel forming layer using a barrel material
And a gate on the main surface of the second conductivity type channel forming layer.
A step of forming a gate electrode via an insulating film, and the second step
Using the gate electrode as a mask in the conductivity type channel formation layer
The second conductivity type source region by ion implantation
Forming directly above the high concentration base region, and
A first conductive layer connected to the source region and the high-concentration base region.
Forming a high concentration region of the mold, the source region and
A process for forming a source electrode in conductive contact with the high concentration region.
Insulated gate type semiconductor device characterized by having
Manufacturing method .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10658992A JP3471823B2 (en) | 1992-01-16 | 1992-04-24 | Insulated gate semiconductor device and method of manufacturing the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4-5942 | 1992-01-16 | ||
| JP594292 | 1992-01-16 | ||
| JP10658992A JP3471823B2 (en) | 1992-01-16 | 1992-04-24 | Insulated gate semiconductor device and method of manufacturing the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003201879A Division JP4016901B2 (en) | 1992-01-16 | 2003-07-25 | Insulated gate semiconductor device and method for manufacturing insulated gate semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05259443A JPH05259443A (en) | 1993-10-08 |
| JP3471823B2 true JP3471823B2 (en) | 2003-12-02 |
Family
ID=30002078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10658992A Expired - Lifetime JP3471823B2 (en) | 1992-01-16 | 1992-04-24 | Insulated gate semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3471823B2 (en) |
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| KR100199997B1 (en) * | 1995-09-06 | 1999-07-01 | 오카메 히로무 | Silicon carbide semiconductor device |
| SE9601178D0 (en) * | 1996-03-27 | 1996-03-27 | Abb Research Ltd | A field controlled semiconductor device of SiC and a method of production thereof |
| US5932894A (en) * | 1997-06-26 | 1999-08-03 | Abb Research Ltd. | SiC semiconductor device comprising a pn junction |
| US6054752A (en) * | 1997-06-30 | 2000-04-25 | Denso Corporation | Semiconductor device |
| SE9704149D0 (en) * | 1997-11-13 | 1997-11-13 | Abb Research Ltd | A semiconductor device of SiC and a transistor of SiC having an insulated gate |
| JPH11251592A (en) | 1998-01-05 | 1999-09-07 | Denso Corp | Carbon silicon semiconductor device |
| JP4186337B2 (en) | 1998-09-30 | 2008-11-26 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method thereof |
| JP4568930B2 (en) * | 1998-10-16 | 2010-10-27 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
| JP4595139B2 (en) * | 1998-10-29 | 2010-12-08 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
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| JP4450123B2 (en) * | 1999-11-17 | 2010-04-14 | 株式会社デンソー | Silicon carbide semiconductor device |
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| JP4848595B2 (en) * | 2001-05-16 | 2011-12-28 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method thereof |
| US8952391B2 (en) | 2002-10-18 | 2015-02-10 | National Institute Of Advanced Industrial Science And Technology | Silicon carbide semiconductor device and its manufacturing method |
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| JP5044151B2 (en) * | 2006-06-26 | 2012-10-10 | 株式会社東芝 | Semiconductor device |
| JP5036399B2 (en) * | 2007-05-22 | 2012-09-26 | 三菱電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP2009016601A (en) * | 2007-07-05 | 2009-01-22 | Denso Corp | Silicon carbide semiconductor device |
| US7687825B2 (en) * | 2007-09-18 | 2010-03-30 | Cree, Inc. | Insulated gate bipolar conduction transistors (IBCTS) and related methods of fabrication |
| CN102820338B (en) * | 2008-02-06 | 2016-05-11 | 罗姆股份有限公司 | Semiconductor device |
| JP5452062B2 (en) | 2009-04-08 | 2014-03-26 | 三菱電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
| US8476733B2 (en) | 2009-11-17 | 2013-07-02 | Panasonic Corporation | Semiconductor element and manufacturing method therefor |
| CN103460390B (en) * | 2011-04-08 | 2017-03-08 | 富士电机株式会社 | Silicon carbide vertical field-effect transistor |
| JP2014063852A (en) * | 2012-09-20 | 2014-04-10 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
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- 1992-04-24 JP JP10658992A patent/JP3471823B2/en not_active Expired - Lifetime
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|---|---|
| JPH05259443A (en) | 1993-10-08 |
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