CN113130650A - Power semiconductor device and preparation process thereof - Google Patents

Power semiconductor device and preparation process thereof Download PDF

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CN113130650A
CN113130650A CN202010032135.1A CN202010032135A CN113130650A CN 113130650 A CN113130650 A CN 113130650A CN 202010032135 A CN202010032135 A CN 202010032135A CN 113130650 A CN113130650 A CN 113130650A
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conductivity type
well region
layer
region
wide band
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CN113130650B (en
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不公告发明人
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Pure Semiconductor Ningbo Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Abstract

According to the power semiconductor device and the preparation process thereof provided by the embodiment of the invention, the first conduction type well region is arranged in the first conduction type semiconductor layer, the second conduction type well region is arranged in the first conduction type well region, and the second conduction type well region is completely surrounded by the first conduction type well region, so that the output capacitance (Coss) of the power semiconductor device can be reduced, the ratio of the input capacitance (Ciss) to the output capacitance (Coss) of the power semiconductor device is improved, namely the value of Ciss/Coss, the electric field of a gate oxide layer can be reduced, and the stability of the device is finally improved.

Description

Power semiconductor device and preparation process thereof
Technical Field
The present invention relates to the field of semiconductor device technology, and more particularly to a power semiconductor device and a process for manufacturing the same.
Background
Power metal oxide semiconductor field effect transistors ("MOSFETs") are a well-known type of semiconductor transistor that can be used as switching devices in high power applications. The power MOSFET may be turned on or off by applying a gate bias to the gate electrode of the device. When the power MOSFET is turned on (i.e., it is in its "on state"), current is conducted through the channel of the MOSFET. When the bias is removed from the gate electrode (or lowered below a threshold level), current stops conducting through the channel. For example, an n-type MOSFET is turned on when a gate bias sufficient to form a conductive n-type inversion layer in the p-type channel region of the device is applied. The n-type inversion layer electrically connects the n-type source and drain regions of the MOSFET, thereby allowing for majority carrier conduction therebetween.
A thin oxide gate insulation layer separates the gate electrode from the channel region of the power MOSFET. Since the gate of the MOSFET is isolated from the channel region, a minimum gate current is required to either keep the MOSFET in its on-state or to switch the MOSFET between its on-state and its off-state. Since the gate forms a capacitor together with the channel region, the gate current is kept small during switching. Thus, only minimal charging and discharging currents are required during switching, allowing for a lower complexity gate drive circuit. Furthermore, since MOSFETs are unipolar devices in which current conduction occurs entirely by majority carrier transport, MOSFETs can exhibit very high switching speeds. However, the drift region of a power MOSFET may exhibit a relatively high on-resistance due to the lack of minority carrier injection. This increased resistance may limit the forward current density achievable with the power MOSFET. In addition, in the case of using a MOSFET, a gate oxide layer of the MOSFET may deteriorate with time.
Bipolar junction transistors ("BJTs") are another well-known type of semiconductor device that can be used as switching devices in high power applications. As known to those skilled in the art, a BJT includes two p-n junctions formed closely adjacent to each other in a semiconductor material. In operation, charge carriers enter a first region of the semiconductor material (which is referred to as the emitter) adjacent one of the p-n junctions. The majority of the charge carriers leave the device from a second region of the semiconductor material, referred to as the collector, adjacent to the other p-n junction. The collector and emitter are formed in regions of the semiconductor material having the same conductivity type. A relatively thin third region of semiconductor material, referred to as the base, is located between the collector and emitter and has a conductivity type opposite to that of the collector and emitter. Thus, two p-n junctions of the BJT are formed where the collector meets the base and where the base meets the emitter. By passing a small current through the base of the BJT, a proportionally larger current passes from the emitter to the collector.
A BJT is a current-controlled device because the BJT is turned "on" by passing current through the base of the transistor (i.e., it is biased such that current flows between the emitter and collector). For example, in an NPN BJT (i.e., a BJT having an n-type collector and emitter region and a p-type base region), the transistor is typically turned on by forward biasing the base-emitter p-n junction by applying a positive voltage to the base. When the device is biased in this way, holes flow into the base of the transistor where they are injected into the emitter. Since the base is a p-type region, holes are referred to as "majority carriers," and holes are "normal" charge carriers in such a region. At the same time, electrons are injected from the emitter into the base where they diffuse towards the collector. Since electrons are not normal charge carriers in the p-type base region, these electrons are called "minority carriers". Since the emitter-collector current includes both electron and hole currents, the device is referred to as a "bipolar" device.
BJTs may require a relatively large base current to maintain the device in its on state. Thus, a relatively complex external drive circuit may be required to provide the relatively large base current that may be required for a high power BJT. Furthermore, due to the bipolar nature of current conduction, the switching speed of BJTs can be significantly slower than that of power MOSFETs.
Devices comprising a combination of bipolar current conduction and MOS control current are also known. One example of such a device is an insulated gate bipolar transistor ("IGBT"), which is a device that combines the high impedance gate of a power MOSFET with small on-state conduction losses of a power BJT. The IGBT may for example be implemented as a pair of composite transistors (Darlington pair) comprising a high voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is provided through the channel of the MOSFET, thereby allowing a simplified external driving circuit. IGBTs can combine the high temperature, high current density switching characteristics of BJTs with the minimal drive requirements of MOSFETs.
Most power semiconductor devices are formed of silicon ("Si"), but various other semiconductor materials have also been used. Silicon carbide ("SiC") is one of these alternative materials. Silicon carbide has potentially advantageous semiconductor properties including, for example, wide bandgap, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Thus, electronic devices formed from silicon carbide may have the ability to operate at higher temperatures, at high power densities, at higher speeds, at higher power levels, and/or at high radiation densities relative to devices formed from other semiconductor materials, such as silicon, for example.
Disclosure of Invention
According to an embodiment of the present invention, a power semiconductor device is provided, which includes:
a first conductive type semiconductor layer having a first conductive type;
a well region component comprising a first conductivity type well region and a second conductivity type well region;
a first conductivity type well region having the first conductivity type and disposed within the first conductivity type semiconductor layer;
and a second conductivity type well region of a second conductivity type disposed within and completely surrounded by the first conductivity type well region.
In some embodiments, a doping concentration of the first conductive type well region is greater than a doping concentration of the first conductive type semiconductor layer; preferably, the doping concentration of the first conductivity type well region is 1 × 1016cm-3—5×1017cm-3The doping concentration of the first conductivity type semiconductor layer is 1 × 1014cm-3—5×1017cm-3. For example, the doping concentration of the first conductivity type well region is 1 × 1016cm-3—5×1017cm-3The doping concentration of the first conductivity type semiconductor layer is 1 × 1014cm-3—5×1015cm-3。
In some embodiments, the first conductive type semiconductor layer includes at least two drift layers sequentially stacked, the first conductive type well region is disposed in a first drift layer closest thereto and overlaps a second drift layer adjacent to the first drift layer to form an overlapping region; preferably, the doping concentration of the first drift layer is less than that of the second drift layer, and the doping concentration of the second drift layer is greater than that of other drift layers far away from the first conductivity type well region relative to the second drift layer;
preferably, the first drift layer is a first wide band gap drift layer, the second drift layer is a second wide band gap drift layer, the first conductivity type semiconductor layer is composed of a first wide band gap drift layer and a second wide band gap drift layer which are sequentially stacked, the doping concentration of the first wide band gap drift layer is less than that of the second wide band gap drift layer, and the first conductivity type well region at least partially overlaps the second wide band gap drift layer to form an overlap region.
In some embodiments, a doping concentration of the second conductivity type well region becomes smaller along a depth direction of the second conductivity type well region; preferably tapered.
In some embodiments, the second conductivity type well region includes, in a direction of a depth thereof, a first well section, a second well section, and a third well section connected in this order, and a doping concentration of the first well section is not less than 1 × 1019cm-3The doping concentration of the second well section is 1 × 1017cm-3—5×1018cm-3The doping concentration of the third well section is not less than 1 x 1016cm-3Preferably 1X 1016cm-3—5×1017cm-3。
In some embodiments, a wall thickness H1 of the first conductivity type well region is not greater than 2 μm.
In some embodiments, the first wide band gap drift layer has a doping concentration of 1 × 1014cm-3—5×1017cm-3(ii) a The second wide band gap drift layer has a doping concentration of 1 × 1014cm-3—5×1017cm-3；
The depth d of the second conductivity type well region is 1-2 μm.
In some embodiments, the number of the well region elements is at least two, adjacent well region elements are spaced apart, and a wide band-gap JFET region is between adjacent well region elements, the wide band-gap JFET region having a first conductivity type;
the wide band gap JFET device further comprises a gate oxide layer and a gate electrode, wherein the gate oxide layer is located on the adjacent well region assemblies and the wide band gap JFET regions between the adjacent well region assemblies, and the gate electrode is located on the gate oxide layer.
In some embodiments, the power semiconductor device comprises a MOSFET, the MOSFET, including,
a wide band-gap source region located within the second conductivity type well region and having a first conductivity type;
a wide band gap drain region having a second conductivity type.
In some embodiments, the drift layer comprises an n-type silicon carbide drift layer, wherein the first conductivity type well region comprises an n-type silicon carbide n-well and the second conductivity type well region comprises a p-type silicon carbide p-well;
the wide bandgap source region comprises an n-type silicon carbide source region;
the wide bandgap drain region comprises a p-type silicon carbide drain region;
the wide bandgap JFET region includes an n-type silicon carbide JFET region.
In some embodiments, the power semiconductor device comprises a silicon carbide insulated gate bipolar junction transistor ("IGBT").
In some embodiments, the semiconductor device further comprises an n-type silicon carbide substrate and an n-type well region formed in the second conductivity type well region+A silicon carbide emitter region, and wherein the first conductivity type semiconductor layer comprises a p-type silicon carbide drift layer, wherein the second conductivity type well region comprises an n-type silicon carbide n-well;
further comprising a collector disposed on a side of the n-type silicon carbide substrate remote from the second conductivity type well region, the collector being a p-type silicon carbide collector, and wherein the wide band-gap JFET region comprises a p-type silicon carbide JFET region.
In some embodiments, further comprising a p-type silicon carbide current spreading layer, wherein the p-type silicon carbide JFET region is part of the p-type silicon carbide current spreading layer.
In addition, an embodiment of the present invention also provides an insulated gate bipolar junction transistor ("IGBT"), which includes: a first conductive type semiconductor layer having a first conductive type on a wide band gap substrate having a second conductive type opposite to the first conductive type;
a well region component comprising a first conductivity type well region and a second conductivity type well region; a first conductivity type well region having the first conductivity type and disposed within the first conductivity type semiconductor layer; a second conductivity type well region having a second conductivity type, disposed within and completely surrounded by the first conductivity type well region;
a wide band-gap emitter region located within the second conductivity type well region and having a first conductivity type;
a wide band-gap collector region having the second conductivity type and located on the second conductivity type well region;
a wide band-gap JFET region having the first conductivity type and located between adjacent well region components.
In some embodiments, a doping concentration of the first conductive type well region is greater than a doping concentration of the first conductive type semiconductor layer; preferably, the doping concentration of the first conductivity type well region is 1 × 1016cm-3—5×1017cm-3The doping concentration of the first conductivity type semiconductor layer is 1 × 1014cm-3—5×1017cm-3。
In some embodiments, further comprising a gate oxide layer over adjacent well region components and the wide band-gap JFET region between adjacent well region components and a gate electrode over the gate oxide layer;
the first conductivity type is p-type and the second conductivity type is n-type.
In addition, an embodiment of the present invention further provides a process for manufacturing a power semiconductor device, including:
forming a first conductive type semiconductor layer;
forming a first conductive type well region in the first conductive type semiconductor layer;
a second conductivity type well region is formed within the first conductivity type well region and is completely surrounded by the first conductivity type well region.
Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:
forming a first mask layer on the first conductivity type semiconductor layer, etching the first mask layer by a dry or wet etching process to form a first opening to expose a portion of the first conductivity type semiconductor layer, and implanting a dopant (e.g., P-type dopant) having a second conductivity type into the first conductivity type semiconductor layer through the first opening by ion implantation or tilted ion implantation to form a second conductivity type well region.
Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:
forming a second conductivity type well region within the first conductivity type well region, comprising:
and etching the first mask layer near the first opening through a dry etching process or a wet etching process, and injecting a dopant (such as an N-type dopant) with the first conductivity type into the first conductivity type semiconductor layer on which the first mask layer is etched through a self-alignment process to form the first conductivity type well region.
In the present invention, the meaning of the well region (e.g., the first conductivity type well region and the second conductivity type well region) is more extensive, i.e., the well region may refer to the meaning commonly used in the MOSFET or the IGBT, or may be customized instead of the meaning commonly used in the MOSFET or the IGBT, for example, the "first conductivity type well region" and the "second conductivity type well region" in the schottky diode (fig. 3 and 4) are customized and do not have the meaning commonly used in the MOSFET or the IGBT.
According to the power semiconductor device provided by the embodiment of the invention, the first conduction type well region is arranged in the first conduction type semiconductor layer, the second conduction type well region is arranged in the first conduction type well region, and the second conduction type well region is completely surrounded by the first conduction type well region, so that the output capacitance (Coss) of the power semiconductor device can be reduced, the ratio of the input capacitance (Ciss) to the output capacitance (Coss) of the power semiconductor device, namely the value of Ciss/Coss, can be increased, the electric field of a gate oxide layer can be reduced, and the stability of the device is improved finally. In addition, the power semiconductor device provided by the embodiment of the invention can also reduce the unit cell size.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of a power MOSFET according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a power MOSFET according to further embodiments of the invention.
Fig. 3 is a schematic cross-sectional view of a schottky diode according to a further embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a schottky diode according to a further embodiment of the present invention.
FIG. 5 is a process flow diagram of a power semiconductor device according to an embodiment of the invention;
fig. 6 is a schematic cross-sectional view of a power IGBT according to an embodiment of the invention.
Fig. 7 is a circuit diagram of a power IGBT according to some embodiments of the invention.
Fig. 8A to 8E are flowcharts showing a manufacturing process for forming a power MOSFET according to embodiment 1 of the present invention.
Description of reference numerals:
1-a first conductivity type semiconductor layer; 1 a-a first drift layer; 1 b-a second drift layer; 2-well region components; 2 a-a first conductivity type well region; 2 b-a second conductivity type well region; a 3-wide bandgap JFET region; 4-gate oxide layer; 5-a gate electrode; 6-an insulating layer; 7-source or emitter; 8-a drain electrode or collector electrode; 9-a substrate; 10-a cathode metal layer; 11-an anodic metal layer; 12-a protective layer; 13-a passivation layer; 14-a first mask layer; 15-second mask layer.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled with" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled with" another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.
It will be understood that, although the terms first and second are used herein to describe various regions, layers and/or elements, these regions, layers and/or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Thus, a first region, layer or element discussed below could be termed a second region, layer or element, and similarly, a second region, layer or element may be termed a first region, layer or element without departing from the scope of the present invention.
Relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device on one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the source and drain regions may be collectively referred to as "source/drain regions," which is a term used to indicate either a source region or a drain region.
It should be understood that the various embodiments disclosed herein may be combined. Thus, features depicted and/or described with respect to the first embodiment may equally be included in the second embodiment, and vice versa.
The description of some embodiments of the invention refers to semiconductor layers and/or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be assigned a "+" or "-" (e.g., n +, n-, p +, p-, n + +, n- -, p + +, p- -, etc.) to indicate a relatively large ("+") or small ("-") concentration of majority carriers relative to another layer or region. However, such notation does not imply the presence of a particular concentration of majority or minority carriers in a layer or region.
As shown in fig. 1, a schematic cross-sectional view of a power MOSFET in an embodiment of the invention. From fig. 1, it can be seen that: the power MOSFET includes a first conductive type semiconductor layer 1 having a first conductive type, for example, the first conductive type is N-type, which may be an N-type silicon carbide layer; a well region component 2, the well region component 2 including a first conductivity type well region 2a and a second conductivity type well region 2 b; a first conductivity type well region 2a having a first conductivity type, for example, the first conductivity type is N-type, the first conductivity type well region 2a may be an N-type silicon carbide N-well, and is disposed in the first conductivity type semiconductor layer 1; the second conductivity type well region 2b has a second conductivity type, for example, the second conductivity type is a P-type, and the second conductivity type well region 2b includes a P-type silicon carbide P-well disposed in the first conductivity type well region 2a and completely surrounded by the first conductivity type well region 2 a.
In the power MOSFET, the first conductivity type well region 2a is arranged in the first conductivity type semiconductor layer 1, the second conductivity type well region 2b is arranged in the first conductivity type well region 2a, and the second conductivity type well region 2b is completely surrounded by the first conductivity type well region 2a, so that the output capacitance (Coss) of the power semiconductor device can be reduced, the ratio of the input capacitance (Ciss) to the output capacitance (Coss) of the power semiconductor device is improved, namely the value of Ciss/Coss, the electric field of a gate oxide layer can be reduced, and the stability of the device is improved finally.
In some embodiments, the doping concentration of the first conductive type well region 2a is greater than the doping concentration of the first conductive type semiconductor layer 1; preferably, the doping concentration of the first conductivity type well region is 1 × 1016cm-3—5×1017cm-3The doping concentration of the first conductivity type semiconductor layer is 1 × 1014cm-3—5×1017cm-3The COSS can be reduced and the gate oxide electric field can be reduced by the arrangement.
In some embodiments, the first conductivity type semiconductor layer 1 includes at least two drift layers sequentially stacked, the first conductivity type well region 2a is disposed in the first drift layer 1a closest thereto and overlaps with the second drift layer 1b adjacent to the first drift layer 1a to form an overlapping region; preferably, the doping concentration of the first drift layer 1a is less than that of the second drift layer 1b, and the doping concentration of the second drift layer 1b is greater than that of the other drift layers which are far from the first conductivity type well region 2a, for example, the other drift layers may be a third drift layer, a fourth drift layer, … … and an nth drift layer which are sequentially far from the second drift layer 1b, and the doping concentrations of the third drift layer to the nth drift layer become gradually smaller. The gate oxide electric field can be reduced by the above arrangement.
Preferably, the first drift layer 1a is a first wide band gap drift layer, the second drift layer 1b is a second wide band gap drift layer, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer which are sequentially stacked, a doping concentration of the first wide band gap drift layer is smaller than a doping concentration of the second wide band gap drift layer, and the first conductivity type well region 2a at least partially overlaps the second wide band gap drift layer to form an overlapping region.
In some embodiments, as shown in fig. 2, along the depth direction of the second conductivity type well region, the doping concentration of the second conductivity type well region becomes smaller, so that the arrangement can improve the breakdown voltage of the power semiconductor device; preferably tapered.
In some embodiments, the second conductivity type well region 2b includes, in a direction of a depth thereof, a first well section, a second well section, and a third well section connected in this order, the first well section having a doping concentration of not less than 1 × 1019cm-3The doping concentration of the second well region is 1 × 1017cm-3—5×1018cm-3The doping concentration of the third well region is not less than 1 × 1016cm-3Preferably 1X 1016cm-3—5×1017cm-3(ii) a Specifically, as shown in FIG. 2, the first well region is P+The segment, the second well segment is P segment, the third well segment is P—And (4) section.
In some embodiments, a wall thickness H1 of the first conductivity type well region is not greater than 2 μm.
In some embodiments, the first wide band gap drift layer has a doping concentration of 1 × 1014cm-3—5×1017cm-3(ii) a The second wide band gap drift layer has a doping concentration of 1 × 1014cm-3—5×1017cm-3(ii) a The depth d of the second conductivity type well region is 1-2 μm.
In some embodimentsAt least two well region elements 2 are provided, adjacent well region elements 2 are arranged at intervals, a wide band-gap JFET region 3 is provided between adjacent well region elements 2, the wide band-gap JFET region 3 has a first conductivity type, for example the first conductivity type is N-type, and specifically can be an N-type silicon carbide JFET region; the wide-band-gap JFET device further comprises a gate oxide layer 4 and a gate electrode 5, wherein the gate oxide layer 4 is positioned on the adjacent well region assemblies 2 and the wide-band-gap JFET region 3 between the adjacent well region assemblies 2; a wide band-gap source region having a first conductivity type and located in the second conductivity type well region; a wide band gap drain region of the second conductivity type, e.g., the first conductivity type may be N-type, and in one embodiment, as shown in FIG. 1, the wide band gap source region includes P-type contact regions+Region and N+And the region further comprises a source electrode 7 arranged on the insulating layer 6 and a drain electrode 8 arranged on one side of the substrate far away from the source electrode 7, wherein the source electrode 7 is connected with the wide-band-gap source region, and the drain electrode 8 is connected with the wide-band-gap drain region.
Furthermore, the drift-type solar cell further comprises a field limiting ring which is arranged in the drift layer on the side, far away from the substrate 9, of the drift layer; in particular, a number of P's spaced within the drift layer as in fig. 1 and 2+And (4) a zone.
In some embodiments, the power semiconductor device comprises a silicon carbide insulated gate bipolar junction transistor ("IGBT").
In some embodiments, the semiconductor device further comprises an n-type silicon carbide substrate and an n-type well region formed in the second conductivity type well region+A silicon carbide emitter region, and wherein the first conductivity type semiconductor layer comprises a p-type silicon carbide drift layer, wherein the second conductivity type well region comprises an n-type silicon carbide n-well;
further comprising a collector disposed on a side of the n-type silicon carbide substrate remote from the second conductivity type well region, the collector being a p-type silicon carbide collector, and wherein the wide band-gap JFET region comprises a p-type silicon carbide JFET region.
In some embodiments, further comprising a p-type silicon carbide current spreading layer, wherein the p-type silicon carbide JFET region is part of the p-type silicon carbide current spreading layer.
Specifically, in addition, an embodiment of the present invention also provides an insulated gate bipolar junction transistor ("IGBT") including: a first conductive type semiconductor layer having a first conductive type on a wide band gap substrate having a second conductive type opposite to the first conductive type;
a well region component comprising a first conductivity type well region and a second conductivity type well region; a first conductivity type well region having the first conductivity type and disposed within the first conductivity type semiconductor layer; a second conductivity type well region having a second conductivity type, disposed within and completely surrounded by the first conductivity type well region;
a wide band-gap emitter region located within the second conductivity type well region and having a first conductivity type;
a wide band-gap collector region having the second conductivity type and located on the second conductivity type well region;
a wide band-gap JFET region having the first conductivity type and located between adjacent well region components.
In some embodiments, a doping concentration of the first conductive type well region is greater than a doping concentration of the first conductive type semiconductor layer; preferably, the doping concentration of the first conductivity type well region is 1 × 1016cm-3—5×1017cm-3The doping concentration of the first conductivity type semiconductor layer is 1 × 1014cm-3—5×1017cm-3。
In some embodiments, further comprising a gate oxide layer over adjacent well region components and the wide band-gap JFET region between adjacent well region components and a gate electrode over the gate oxide layer;
the first conductivity type is p-type and the second conductivity type is n-type.
In addition, an embodiment of the present invention further provides a manufacturing process of a power semiconductor device, as shown in fig. 5, including:
s101, forming a first conductive type semiconductor layer; specifically, the first conductive type semiconductor layer may form a multi-layer drift layer on the substrate by means of epitaxial growth, ion implantation, or tilted ion implantation;
s102, forming a first conductive type well region in the first conductive type semiconductor layer; the ion implantation or the inclined ion implantation can be carried out;
s103, forming a second conductive type well region in the first conductive type well region, wherein the second conductive type well region is completely surrounded by the first conductive type well region; and can also be formed by means of ion implantation or tilted ion implantation.
Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:
forming a first mask layer on the first conductivity type semiconductor layer, etching the first mask layer by a dry or wet etching process to form a first opening to expose a portion of the first conductivity type semiconductor layer, and implanting a dopant (e.g., P-type dopant) having a second conductivity type into the first conductivity type semiconductor layer through the first opening by ion implantation or tilted ion implantation to form a second conductivity type well region.
Further, forming a first conductive type well region in the first conductive type semiconductor layer includes:
forming a second conductivity type well region within the first conductivity type well region, comprising:
and etching the first mask layer near the first opening through a dry etching process or a wet etching process, and injecting a dopant (such as an N-type dopant) with the first conductivity type into the first conductivity type semiconductor layer on which the first mask layer is etched through a self-alignment process to form the first conductivity type well region.
In order to explain the technical scheme of the invention in detail, the following specific embodiments are provided:
example 1
The embodiment provides a power MOSFET and a preparation process thereof. As shown in FIG. 1, the power MOSFET includes a first conductivity type semiconductor layer 1 having a first conductivity type, for example, the first conductivity type semiconductor layer 1 is formed of a first wide band arranged by being sequentially stackedA gap drift layer and a second wide band gap drift layer, the doping concentration of the first wide band gap drift layer is less than that of the second wide band gap drift layer, and the first wide band gap drift layer is lightly doped N-A silicon carbide layer, for example, doped with phosphorus or nitrogen, a second wide band gap drift layer, for example, doped N-type silicon carbide layer, for example, doped with phosphorus or nitrogen, the second wide band gap drift layer being disposed on a substrate 9, the substrate 9 being heavily doped N+A silicon carbide layer, for example, the dopant can be phosphorus or nitrogen, and the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or inclined ion implantation; a well region component 2, the well region component 2 including a first conductivity type well region 2a and a second conductivity type well region 2 b; a first conductivity type well region 2a having a first conductivity type, for example, the first conductivity type is N-type, the first conductivity type well region 2a may be an N-type silicon carbide N-well, and is disposed in the first conductivity type semiconductor layer 1; a second conductivity type well region 2b having a second conductivity type, for example, the second conductivity type is P-type, the second conductivity type well region 2b includes a P-type silicon carbide P-well, and dopants in the P-type silicon carbide P-well may be aluminum, boron, or gallium, and are disposed in the first conductivity type well region 2a and completely surrounded by the first conductivity type well region 2 a;
wide band gap JFET regions 3 are arranged at intervals between adjacent well region assemblies 2, the wide band gap JFET regions 3 are n-type silicon carbide JFET regions, gate oxide layers 4 are arranged on the wide band gap JFET regions 3 between the adjacent well region assemblies 2 and the adjacent well region assemblies 2, gate electrodes 5 are arranged on the gate oxide layers 4, and insulating layers 6 are arranged on the gate electrodes 5; a wide band-gap source region located within the second conductivity type well region and having a first conductivity type; a wide band gap drain region of the second conductivity type, e.g., the first conductivity type may be N-type, as shown in FIG. 1, a wide band gap source region comprising P-type contacts+Region and N+The region further comprises a source electrode 7 arranged on the insulating layer 6 and a drain electrode 8 arranged on one side of the substrate 9 far away from the source electrode 7, wherein the source electrode 7 is connected with the wide-band-gap source region, and the drain electrode 8 is connected with the wide-band-gap drain region.
The manufacturing process of the power MOSFET, as shown in fig. 8A to 8E, includes the following steps:
(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by epitaxial growth, ion implantation or inclined ion implantation;
(2) forming a first mask layer (for example, silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, for example, silicon nitride) on the first wide band gap drift layer, etching the first mask layer 14 by a dry or wet etching process to form a first opening to expose the first wide band gap drift layer, implanting a dopant of aluminum, boron, or gallium into the first wide band gap drift layer and the second wide band gap drift layer through the first opening by means of ion implantation to a depth up to the second wide band gap drift layer, forming a second conductivity type well region 2b, namely, P-P #, where the second conductivity type well region 2b has an overlapping region with the second wide band gap drift layer; then, doping dopant phosphorus or nitrogen into the second conductive type well region 2b through a self-alignment process to form an N + region;
(3) etching the first mask layer near the first opening in the step (2) by a dry or wet etching process, and injecting dopant phosphorus or nitrogen into the first wide band gap drift layer on which the first mask layer is etched by a self-alignment process to form a first conductivity type well region 2a, wherein the first conductivity type well region 2a completely surrounds a second conductivity type well region 2 b;
(4) forming a second mask layer (for example, silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, for example, silicon nitride) on the first wide band gap drift layer, etching the second mask layer 15 by a dry or wet etching process to form a second opening to expose the second conductive type well region 2b, and implanting dopant aluminum, boron, or gallium into the second conductive type well region 2b through the second opening by means of ion implantation to form a P + region, where the field limiting ring and the gate oxide layer 4 can be simultaneously formed;
(5) etching the second mask layer left on the first wide band gap drift layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then forming a mask layer and selectively etching to form a gate electrode 5, an insulating layer 7, a source electrode 7 and a drain electrode 8;
(6) the device prepared in step (5) can be protected from the front side, such as an epitaxial growth protection layer (marked in fig. 1), back thinning, ohmic contact, metal deposition and the like, and thus the process can be prepared by adopting the existing process.
Example 2
The embodiment provides a power MOSFET and a preparation process thereof. As shown in fig. 2, the power MOSFET includes a first conductivity type semiconductor layer 1 having the first conductivity type, for example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer which are sequentially stacked, the doping concentration of the first wide band gap drift layer is less than that of the second wide band gap drift layer, and the first wide band gap drift layer is lightly doped N-A silicon carbide layer, for example, doped with phosphorus or nitrogen, a second wide band gap drift layer, for example, doped N-type silicon carbide layer, for example, doped with phosphorus or nitrogen, the second wide band gap drift layer being disposed on a substrate 9, the substrate 9 being heavily doped N+A silicon carbide layer, for example, the dopant can be phosphorus or nitrogen, and the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or inclined ion implantation; a well region component 2, the well region component 2 including a first conductivity type well region 2a and a second conductivity type well region 2 b; a first conductivity type well region 2a having a first conductivity type, for example, the first conductivity type is N-type, the first conductivity type well region 2a may be an N-type silicon carbide N-well, and is disposed in the first conductivity type semiconductor layer 1; a second conductivity type well region 2b having a second conductivity type, for example, the second conductivity type is P-type, the second conductivity type well region 2b includes a P-type silicon carbide P-well, and dopants in the P-type silicon carbide P-well may be aluminum, boron, or gallium, and are disposed in the first conductivity type well region 2a and completely surrounded by the first conductivity type well region 2 a; along the depth direction of the second conductive type well region 2b, the second conductive type well region 2b comprises a first well section, a second well section and a third well section which are connected in sequence, and the doping concentration of the first well section is not less than 1 x 1019cm-3The doping concentration of the second well region is 1 × 1017cm-3—5×1018cm-3The doping concentration of the third well region is not less than 1 × 1016cm-3Preferably 1X 1016cm-3—5×1017cm-3(ii) a Specifically, as shown in fig. 2, the first well section is a P + section, the second well section is a P section, and the third well section is a P-section;
wide band gap JFET regions 3 are arranged at intervals between adjacent well region assemblies 2, the wide band gap JFET regions 3 are n-type silicon carbide JFET regions, gate oxide layers 4 are arranged on the wide band gap JFET regions 3 between the adjacent well region assemblies 2 and the adjacent well region assemblies 2, gate electrodes 5 are arranged on the gate oxide layers 4, and insulating layers 6 are arranged on the gate electrodes 5; a wide band-gap source region located within the second conductivity type well region and having a first conductivity type; a wide band gap drain region of the second conductivity type, e.g., the first conductivity type may be N-type, as shown in FIG. 2, a wide band gap source region comprising P-type contacts+The region further comprises a source electrode 7 arranged on the insulating layer 6 and a drain electrode 8 arranged on one side of the substrate 9 far away from the source electrode 7, wherein the source electrode 7 is connected with the wide-band-gap source region, and the drain electrode 8 is connected with the wide-band-gap drain region.
The preparation process of the power MOSFET comprises the following steps:
(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by epitaxial growth, ion implantation or inclined ion implantation;
(2) forming a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide band gap drift layer, etching the first mask layer by a dry or wet etching process to form a first opening to expose the first wide band gap drift layer, implanting a dopant of aluminum, boron, or gallium into the first wide band gap drift layer and the second wide band gap drift layer by ion implantation through the first opening to a depth reaching the second wide band gap drift layer, and forming a second conductivity type well region 2b, namely P-P #, wherein the second conductivity type well region 2b has an overlapping region with the second wide band gap drift layer; then, doping aluminum or boron or gallium into the second conductive type well region 2b again through a self-alignment process, and finally, doping aluminum or boron or gallium into the second conductive type well region 2b again through the self-alignment process so as to finally form a P-section, a P-section and a P + section in the second conductive type well region 2b from bottom to top in sequence;
(3) etching the first mask layer near the first opening in the step (2) by a dry or wet etching process, and injecting dopants phosphorus and nitrogen in the first wide band gap drift layer on which the first mask layer is etched by a self-alignment process to form a first conductivity type well region 2a, wherein the first conductivity type well region 2a completely surrounds a second conductivity type well region 2 b;
(4) forming a second mask layer (for example, silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, for example, silicon nitride) on the first wide band gap drift layer, etching the second mask layer by a dry or wet etching process to form a second opening to expose a portion outside the second conductive type well region 2b, and implanting dopant aluminum, boron, or gallium into the portion outside the second conductive type well region 2b through the second opening by ion implantation to form a field limiting ring (P +), where the gate oxide layer 4 may be formed simultaneously;
(5) etching the second mask layer left on the first wide band gap drift layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then forming a mask layer and selectively etching to form a gate electrode 5, an insulating layer 7, a source electrode 7 and a drain electrode 8;
(6) the device prepared in step (5) may also be subjected to front protection, such as epitaxial growth of a protective layer (labeled in fig. 2), back thinning, ohmic contact, metal deposition, and the like, and thus the process may be performed by using conventional processes.
Example 3
The embodiment provides a Schottky diode and a preparation process thereof. As shown in fig. 3, the schottky diode includes a first conductivity type semiconductor layer 1 having the first conductivity type, for example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer which are sequentially stacked, the doping concentration of the first wide band gap drift layer is less than that of the second wide band gap drift layer, and the first wide band gap drift layer is lightly doped N-A silicon carbide layer, e.g. with a dopant of phosphorus or nitrogen, and a second wide band gap drift layer of doped N-typeA silicon carbide layer, e.g. doped with phosphorus or nitrogen, a second wide band gap drift layer provided on the substrate 9, the substrate 9 being heavily doped N+A silicon carbide layer, for example, the dopant may be phosphorus or nitrogen, and the first wide band gap drift layer and the second wide band gap drift layer may be formed by epitaxial growth, ion implantation, or tilted ion implantation; a well region component 2, the well region component 2 including a first conductivity type well region 2a and a second conductivity type well region 2 b; a first conductivity type well region 2a having a first conductivity type, for example, the first conductivity type is N-type, the first conductivity type well region 2a may be an N-type silicon carbide N-well, and is disposed in the first conductivity type semiconductor layer 1; a second conductivity type well region 2b having a second conductivity type, for example, the second conductivity type is P-type, the second conductivity type well region 2b includes a P-type silicon carbide P-well, a dopant in the P-type silicon carbide P-well may be aluminum, boron or gallium, and is disposed in the first conductivity type well region 2a and completely surrounded by the first conductivity type well region 2 a; in one embodiment, a P-type silicon carbide P-well is implanted with P + so that the doping concentration thereof is higher than that of the first drift layer 1a in the first conductivity type semiconductor layer 1; in another embodiment, P + is not implanted into the P-type silicon carbide P-well, so that the doping concentration of the P + is the same as that of the first drift layer 1a in the first conductivity-type semiconductor layer 1, thereby reducing the number of implantation steps and simplifying the manufacturing process.
An anode metal layer 11 (for example, an Al layer) disposed between the adjacent well region elements 2 and the adjacent well region elements 2, and a cathode metal layer 10 disposed on the substrate 9 on a side away from the anode metal layer 11, wherein a protective layer (for example, an SiO wide band gap drift layer) is disposed on the first wide band gap drift layer not covered and contacted by the anode metal layer 112Layer or Si3N4Layer) to protect the drift layer and the first conductivity type well region 2a and the second conductivity type well region 2 b; a schottky barrier layer (not shown) is disposed between the anode metal layer 11 and the adjacent well region component 2 and between the adjacent well region components 2, and the material of the schottky barrier layer can be selected from Ti, Ni, Al, Mo, W, polysilicon, etc., and the thickness is generally equal to
Figure BDA0002364708030000151
By evaporation or sputteringShot form formation;
the preparation process of the Schottky diode comprises the following steps:
(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by epitaxial growth, ion implantation or inclined ion implantation;
(2) forming a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide band gap drift layer, etching the first mask layer by a dry or wet etching process to form a first opening to expose the first wide band gap drift layer, implanting a dopant of aluminum, boron, or gallium into the first wide band gap drift layer and the second wide band gap drift layer by ion implantation through the first opening to a depth reaching the second wide band gap drift layer, and forming a second conductivity type well region 2b, namely P-P #, wherein the second conductivity type well region 2b has an overlapping region with the second wide band gap drift layer;
(3) etching the first mask layer near the first opening in the step (2) by a dry or wet etching process, and injecting dopant phosphorus or nitrogen into the first wide band gap drift layer on which the first mask layer is etched by a self-alignment process to form a first conductivity type well region 2a, wherein the first conductivity type well region 2a completely surrounds a second conductivity type well region 2 b;
(4) forming Schottky barrier layers on the adjacent well region assemblies 2 and the region between the adjacent well region assemblies 2 in an evaporation or sputtering mode;
(5) an anode metal layer 11 is formed on the schottky barrier layer by sputtering or evaporation, the anode metal layer 11 at least partially covers the first and second conductivity type well regions 2b, and a protective layer (for example, SiO) is formed on the first wide band gap drift layer not covered and contacted by the anode metal layer 11 by sputtering or chemical vapor deposition2Layer or Si3N4A layer); and a cathode metal layer 10 is formed by means of evaporation or sputtering on the side of the substrate 9 remote from the anode metal layer 11.
Example 4
The embodiment providesA Schottky diode and a preparation process thereof are provided. As shown in fig. 3, the schottky diode includes a first conductivity type semiconductor layer 1 having the first conductivity type, for example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer which are sequentially stacked, the doping concentration of the first wide band gap drift layer is less than that of the second wide band gap drift layer, and the first wide band gap drift layer is lightly doped N-A silicon carbide layer, for example, with a dopant of phosphorus or nitrogen, a second wide band gap drift layer, for example, with a dopant of phosphorus or nitrogen, a doped N-type silicon carbide layer, for example, with a dopant of phosphorus or nitrogen, the second wide band gap drift layer being provided on a substrate 9, the substrate 9 being a heavily doped N-type silicon carbide layer+A silicon carbide layer, for example, the dopant may be phosphorus or nitrogen, and the first wide band gap drift layer and the second wide band gap drift layer may be formed by epitaxial growth, ion implantation, or tilted ion implantation; a well region component 2, the well region component 2 including a first conductivity type well region 2a and a second conductivity type well region 2 b; a first conductivity type well region 2a having a first conductivity type, for example, the first conductivity type is N-type, the first conductivity type well region 2a may be an N-type silicon carbide N-well, and is disposed in the first conductivity type semiconductor layer 1; a second conductivity type well region 2b having a second conductivity type, for example, the second conductivity type is P-type, the second conductivity type well region 2b includes a P-type silicon carbide P-well, a dopant in the P-type silicon carbide P-well may be aluminum, boron or gallium, and is disposed in the first conductivity type well region 2a and completely surrounded by the first conductivity type well region 2 a;
an anode metal layer 11 (for example, an Al layer) disposed between the adjacent well region elements 2 and the adjacent well region elements 2, and a cathode metal layer 10 disposed on a side of the substrate 9 away from the anode metal layer 11, wherein the anode metal layer 11 disposed in the second conductivity type well region 2b protrudes toward the second conductivity type well region 2b and enters the second conductivity type well region 2 b; a passivation layer 13 (which may be SiO, for example) is disposed on the anode metal layer 112Layer or Si3N4Layer) and is completely covered by the passivation layer 13; a schottky barrier layer (not shown) is disposed between the anode metal layer 11 and the adjacent well region component 2 and between the adjacent well region components 2, and the material of the schottky barrier layer can be selected from Ti, Ni, Al, Mo, W, and polySilicon, etc., generally having a thickness of
Figure BDA0002364708030000161
Can be formed by evaporation or sputtering;
the preparation process of the Schottky diode comprises the following steps:
(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by epitaxial growth, ion implantation or inclined ion implantation;
(2) forming a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide band gap drift layer, etching the first mask layer by a dry or wet etching process to form a first opening to expose the first wide band gap drift layer, implanting a dopant of aluminum, boron, or gallium into the first wide band gap drift layer and the second wide band gap drift layer by ion implantation through the first opening to a depth reaching the second wide band gap drift layer, and forming a second conductivity type well region 2b, namely P-P #, wherein the second conductivity type well region 2b has an overlapping region with the second wide band gap drift layer; then, doping dopant phosphorus or nitrogen into the second conductive type well region 2b through a self-alignment process to form an N + region;
(3) etching the first mask layer near the first opening in the step (2) by a dry or wet etching process, and injecting dopant phosphorus or nitrogen into the first wide band gap drift layer on which the first mask layer is etched by a self-alignment process to form a first conductivity type well region 2a, wherein the first conductivity type well region 2a completely surrounds a second conductivity type well region 2 b;
(4) forming Schottky barrier layers on the adjacent well region assemblies 2 and the region between the adjacent well region assemblies 2 in an evaporation or sputtering mode;
(5) an anode metal layer 11 is formed on the schottky barrier layer by sputtering or evaporation, the anode metal layer 11 at least partially covers the first conductivity type well region and the second conductivity type well region 2b, and a passivation layer 13 (which may be SiO for example) is formed on the anode metal layer 11 by sputtering or chemical vapor deposition2Layer or Si3N4A layer); and a cathode metal layer 10 is formed by means of evaporation or sputtering on the side of the substrate 9 remote from the anode metal layer 11.
Example 5
The embodiment provides an IGBT and a preparation process thereof. As shown in fig. 6, the IGBT includes a first conductivity type semiconductor layer 1 having a first conductivity type, for example, the first conductivity type semiconductor layer 1 is composed of a first wide band gap drift layer and a second wide band gap drift layer which are sequentially stacked, the doping concentration of the first wide band gap drift layer is smaller than that of the second wide band gap drift layer, and the first wide band gap drift layer is a lightly doped P-A silicon carbide layer, for example, with a dopant of aluminum, boron, gallium, a second wide band gap drift layer, for example, with a dopant of aluminum, boron, gallium, a doped P-type silicon carbide layer, for example, with a dopant of aluminum, boron, gallium, a second wide band gap drift layer disposed on a substrate 9, the substrate 9 being a heavily doped N+A silicon carbide layer, for example, the dopant can be phosphorus or nitrogen, and the first wide band gap drift layer and the second wide band gap drift layer can be formed by epitaxial growth, ion implantation or inclined ion implantation; a well region component 2, the well region component 2 including a first conductivity type well region 2a and a second conductivity type well region 2 b; a first conductivity type well region 2a having a first conductivity type, for example, the first conductivity type is P-type, and the first conductivity type well region 2a may be a P-type silicon carbide P-well and is disposed in the first conductivity type semiconductor layer 1; a second conductivity type well region 2b having a second conductivity type, for example, the second conductivity type is N-type, the second conductivity type well region 2b includes an N-type silicon carbide N-well, and a dopant in the N-type silicon carbide N-well may be phosphorus or nitrogen, and is disposed in the first conductivity type well region 2a and completely surrounded by the first conductivity type well region 2 a; the second conductive type well region 2b is not divided into well sections along the depth direction, and the doping concentration is consistent;
wide-band-gap JFET regions 3 are arranged at intervals between adjacent well region assemblies 2, the wide-band-gap JFET regions 3 are P-type silicon carbide JFET regions, gate oxide layers 4 are arranged on the wide-band-gap JFET regions 3 between the adjacent well region assemblies 2 and the adjacent well region assemblies 2, gate electrodes 5 are arranged on the gate oxide layers 4, and insulating layers 6 are arranged on the gate electrodes 5; a wide band gap emitter region on the second conductivity type well regionAnd has a first conductivity type, connected to the emitter 7; for example, the first conductivity type may be P-type, as shown in FIG. 6, P+The region is adjacent to the wide bandgap JFET region 3; a wide band-gap collector region having the second conductivity type and located on the second conductivity type well region; a wide band-gap JFET region having the first conductivity type and located between adjacent well region components; a wide band gap collector region, which may be arranged on the substrate 9 on the side remote from the wide band gap emitter region, is connected to the collector electrode 8.
The preparation process of the IGBT comprises the following steps:
(1) sequentially forming a second wide band gap drift layer and a first wide band gap drift layer on the substrate 9 by epitaxial growth, ion implantation or inclined ion implantation;
(2) forming a first mask layer (such as silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) on the first wide band gap drift layer, etching the first mask layer by a dry or wet etching process to form a first opening to expose the first wide band gap drift layer, implanting dopant phosphorus or nitrogen into the first wide band gap drift layer and the second wide band gap drift layer through the first opening by ion implantation to a depth reaching the second wide band gap drift layer, and forming a second conductivity type well region 2b, namely N-N #, wherein the second conductivity type well region 2b and the second wide band gap drift layer have an overlapping region; then, doping dopant phosphorus or nitrogen into the second conductive type well region 2b through a self-alignment process to form a P + region;
(3) etching the first mask layer near the first opening in the step (2) by a dry or wet etching process, and injecting a dopant of aluminum or boron or gallium into the first wide band gap drift layer on which the first mask layer is etched by a self-alignment process to form a first conductivity type well region 2a, wherein the first conductivity type well region 2a completely surrounds a second conductivity type well region 2 b;
(4) forming a second mask layer (for example, silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, for example, silicon nitride) on the first wide band gap drift layer, etching the second mask layer by a dry or wet etching process to form a second opening to expose the second conductive type well region 2b, and implanting dopant phosphorus or nitrogen into the second conductive type well region 2b through the second opening by ion implantation to form an N + region, where a field limiting ring and a gate oxide layer 4 may be simultaneously formed;
(5) etching the second mask layer left on the first wide band gap drift layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then forming a mask layer and selectively etching to form a gate electrode 5, an insulating layer 7, a source electrode 7 and a drain electrode 8;
(6) the device prepared in step (5) may also be subjected to front protection, such as epitaxial growth of a protective layer (labeled in fig. 6), backside thinning, ohmic contact, metal deposition, and the like, and thus the process may be performed by using conventional processes.
Fig. 7 is a circuit diagram of a power IGBT according to some embodiments of the invention, as can be appreciated from fig. 7: IGBT 500 includes NPN silicon carbide power BJT 501 having base 502, emitter 503, and collector 504. IGBT 500 also includes a silicon carbide power MOSFET 505 having a gate 506, a source 507, and a drain 508. The source 507 of the silicon carbide power MOSFET 505 is electrically connected to the base 502 of the silicon carbide power BJT 501, and the drain 508 of the silicon carbide power MOSFET 505 is electrically connected to the collector 504 of the silicon carbide power BJT 501.
The IGBT 500 may operate as follows. An external drive circuit is connected to the gate 506 of the MOSFET 505 to apply a gate bias to the power MOSFET 505. When the external drive circuit applies a sufficient voltage to gate electrode 506, an inversion layer is formed under gate 506, which acts as a channel 509 that electrically connects collector 504 of BJT 501 to base 502 of BJT 501. Holes are conducted from the collector region 504 through the channel 509 into the base 501. This hole current acts as a base current that drives BJT 501. In response to this hole current, electrons are conducted from emitter 503 of BJT 501 across base 502 to collector 504 of BJT 501. Thus, silicon carbide power MOSFET 505 converts silicon carbide power BJT 501 from a current driven device to a voltage driven device, which may allow for simplified external drive circuitry. Silicon carbide power MOSFET 505 acts as a driver transistor and silicon carbide power BJT 501 acts as an output transistor of IGBT 500.
In addition, according to the above description, the P-type MOSFET device and the n-type MOSFET device can be switched with each other, the P-type IGBT and the n-type IGBT can be switched with each other, and the P-type MOSFET device, the n-type MOSFET device, the P-type IGBT and the n-type IGBT are all within the protection scope of the present invention.
Although the foregoing embodiments have been described with reference to specific figures, it should be understood that some embodiments of the invention may include additional and/or intervening layers, structures, or elements, and/or may be deleted or omitted. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present invention and that the invention is not to be considered limited to the specific embodiments disclosed and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims (19)

1. A power semiconductor device comprising:
a first conductive type semiconductor layer having a first conductive type;
a well region component comprising a first conductivity type well region and a second conductivity type well region;
a first conductivity type well region having the first conductivity type and disposed within the first conductivity type semiconductor layer;
and a second conductivity type well region of a second conductivity type disposed within and completely surrounded by the first conductivity type well region.
2. The power semiconductor device of claim 1, wherein a doping concentration of the first conductivity type well region is greater than the first conductivity type well regionA doping concentration of the first conductive type semiconductor layer; preferably, the doping concentration of the first conductivity type well region is 1 × 1016cm-3—5×1017cm-3The doping concentration of the first conductivity type semiconductor layer is 1 × 1014cm-3—5×1017cm-3。
3. The power semiconductor device according to claim 1 or 2, wherein the first conductivity type semiconductor layer comprises at least two drift layers sequentially stacked, and the first conductivity type well region is disposed in a first drift layer closest to the first conductivity type well region and overlaps with a second drift layer adjacent to the first drift layer to form an overlapping region; preferably, the doping concentration of the first drift layer is less than that of the second drift layer, and the doping concentration of the second drift layer is greater than that of other drift layers far away from the first conductivity type well region relative to the second drift layer;
preferably, the first drift layer is a first wide band gap drift layer, the second drift layer is a second wide band gap drift layer, the first conductivity type semiconductor layer is composed of a first wide band gap drift layer and a second wide band gap drift layer which are sequentially stacked, the doping concentration of the first wide band gap drift layer is less than that of the second wide band gap drift layer, and the first conductivity type well region at least partially overlaps the second wide band gap drift layer to form an overlap region.
4. The power semiconductor device according to any one of claims 1 to 3, wherein a doping concentration of the second conductivity type well region becomes smaller along a depth direction of the second conductivity type well region; preferably tapered.
5. The power semiconductor device according to claim 4, wherein the second conductivity type well region includes a first well section, a second well section and a third well section connected in sequence in a direction of a depth thereof, and a doping concentration of the first well section is not less than that of the first well section1×1019cm-3The doping concentration of the second well section is 1 × 1017cm-3—5×1018cm-3The doping concentration of the third well section is not less than 1 x 1016cm-3Preferably 1X 1016cm-3—5×1017cm-3。
6. The power semiconductor device according to any of claims 3-5, wherein the wall thickness H1 of the first conductivity type well region is not more than 2 μm.
7. The power semiconductor device of any of claims 3-6, wherein the first wide band gap drift layer has a doping concentration of 1 x 1014cm-3—5×1017cm-3；
The second wide band gap drift layer has a doping concentration of 1 × 1014cm-3—5×1017cm-3；
The depth d of the second conductivity type well region is 1-2 μm.
8. The power semiconductor device of claim 7, wherein there are at least two of said well region elements, adjacent well region elements being spaced apart, a wide band-gap JFET region between adjacent well region elements, said wide band-gap JFET region having a first conductivity type;
the wide band gap JFET device further comprises a gate oxide layer and a gate electrode, wherein the gate oxide layer is located on the adjacent well region assemblies and the wide band gap JFET regions between the adjacent well region assemblies, and the gate electrode is located on the gate oxide layer.
9. The power semiconductor device of claim 8, wherein the power semiconductor device comprises a MOSFET, comprising,
a wide band-gap source region located within the second conductivity type well region and having a first conductivity type;
a wide band gap drain region having a second conductivity type.
10. The power semiconductor device of claim 9, wherein the drift layer comprises an n-type silicon carbide drift layer, wherein the first conductivity type well region comprises an n-type silicon carbide n-well and the second conductivity type well region comprises a p-type silicon carbide p-well;
the wide bandgap source region comprises an n-type silicon carbide source region;
the wide bandgap drain region comprises a p-type silicon carbide drain region;
the wide bandgap JFET region includes an n-type silicon carbide JFET region.
11. The power semiconductor device of claim 8, wherein the power semiconductor device comprises a silicon carbide insulated gate bipolar junction transistor.
12. The power semiconductor device of claim 11, further comprising an n-type silicon carbide substrate and an n-type well region formed in the second conductivity type well region+A silicon carbide emitter region, and wherein the first conductivity type semiconductor layer comprises a p-type silicon carbide drift layer, wherein the second conductivity type well region comprises an n-type silicon carbide n-well;
further comprising a collector disposed on a side of the n-type silicon carbide substrate remote from the second conductivity type well region, the collector being a p-type silicon carbide collector, and wherein the wide band-gap JFET region comprises a p-type silicon carbide JFET region.
13. The power semiconductor device of claim 12, further comprising a p-type silicon carbide current spreading layer, wherein the p-type silicon carbide JFET region is part of the p-type silicon carbide current spreading layer.
14. An insulated gate bipolar junction transistor, comprising: a first conductive type semiconductor layer having a first conductive type on a wide band gap substrate having a second conductive type opposite to the first conductive type;
a well region component comprising a first conductivity type well region and a second conductivity type well region; a first conductivity type well region having the first conductivity type and disposed within the first conductivity type semiconductor layer; a second conductivity type well region having a second conductivity type, disposed within and completely surrounded by the first conductivity type well region;
a wide band-gap emitter region located within the second conductivity type well region and having a first conductivity type;
a wide band-gap collector region having the second conductivity type and located on the second conductivity type well region;
a wide band-gap JFET region having the first conductivity type and located between adjacent well region components.
15. The insulated gate bipolar junction transistor according to claim 14, wherein a doping concentration of the first conductivity type well region is greater than a doping concentration of the first conductivity type semiconductor layer; preferably, the doping concentration of the first conductivity type well region is 1 × 1016cm-3—5×1017cm-3The doping concentration of the first conductivity type semiconductor layer is 1 × 1014cm-3—5×1017cm-3。
16. The insulated gate bipolar junction transistor of claim 15 further comprising a gate oxide layer over adjacent well region components and the wide band-gap JFET region therebetween and a gate electrode over said gate oxide layer;
the first conductivity type is p-type and the second conductivity type is n-type.
17. A process for preparing a power semiconductor device, comprising:
forming a first conductive type semiconductor layer;
forming a first conductive type well region in the first conductive type semiconductor layer;
a second conductivity type well region is formed within the first conductivity type well region and is completely surrounded by the first conductivity type well region.
18. The process of claim 17, wherein forming a first conductivity type well region in the first conductivity type semiconductor layer comprises:
forming a first mask layer on the first conductive type semiconductor layer, etching the first mask layer through a dry etching process or a wet etching process to form a first opening to expose a part of the first conductive type semiconductor layer, and injecting a dopant with a second conductive type into the first conductive type semiconductor layer through the first opening by using an ion injection or inclined ion injection mode to form a second conductive type well region.
19. The process of claim 18, wherein forming a first conductivity type well region in the first conductivity type semiconductor layer comprises:
forming a second conductivity type well region within the first conductivity type well region, comprising:
and etching the first mask layer near the first opening through a dry etching process or a wet etching process, and injecting a dopant with the first conductivity type into the first conductivity type semiconductor layer on which the first mask layer is etched through a self-alignment process to form the first conductivity type well region.
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