JP2004253510A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with high breakdown voltage which can control increase in leak current. <P>SOLUTION: The semiconductor device comprises an n<SP>-</SP>type SiC epitaxial layer 2, a first junction (hetero junction) formed of an n<SP>-</SP>type polysilicon layer 3 which is different in the band gap from the n<SP>-</SP>type SiC epitaxial layer 2, and a second junction (Schottky junction) formed of the n<SP>-</SP>type polysilicon layer 3 and a Schottky electrode 4. Moreover, the semiconductor device also includes a thin film semiconductor region in which the thickness of the n<SP>-</SP>type polysilicon layer 3 is set smaller than the sum of the distance in which the built-in electric field extends to the n<SP>-</SP>type polysilicon layer 3 at least from the first junction and the distance in which the built-in electric field extends to the n<SP>-</SP>type polysilicon layer 3 from the second junction. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device such as a diode and a switch element.
[0002]
[Prior art]
[Non-Patent Document] "Power Device / Power IC Handbook, The Institute of Electrical Engineers of Japan, Special Committee for Investigating High-Performance and High-Performance Power Devices / Power ICs, Corona, pp. 12-21"
[0003]
As a conventional junction for obtaining a high breakdown voltage diode using silicon carbide, there are a PN junction and a Schottky junction described in the above-mentioned non-patent document. In the non-patent literature, these junctions are described based on silicon, but are widely applied to silicon carbide.
[0004]
[Problems to be solved by the invention]
In order to apply a PN junction to silicon carbide and obtain a high breakdown voltage, it is necessary to form a deep diffusion layer, and for that reason, impurity introduction by ion implantation is indispensable. When ion implantation is performed, a crystal defect is introduced into silicon carbide, which causes a problem that a leak current increases.
An object of the present invention is to solve the above problems and to provide a high withstand voltage semiconductor device capable of suppressing an increase in leakage current.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has a first junction formed by a first semiconductor material layer and a second semiconductor material layer having a different band gap from the first semiconductor material layer. The semiconductor device has a thin-film semiconductor region formed so that the thickness is smaller than the distance that the built-in electric field reaches from the first junction to the second semiconductor material layer.
[0006]
【The invention's effect】
According to the present invention, a high-breakdown-voltage semiconductor device capable of suppressing an increase in leak current can be provided.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
Embodiment 1
First, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a sectional view of a silicon carbide semiconductor device according to the first embodiment of the present invention.
In FIG. 1, N ⁺ N-type SiC substrate 1 ⁻ By forming SiC epitaxial layer 2 of the type, an N-type silicon carbide semiconductor substrate of the first conductivity type is formed. That is, the silicon carbide semiconductor substrate is composed of SiC substrate 1 and SiC epitaxial layer 2. On the silicon carbide semiconductor substrate, on the first principal surface side, that is, on the SiC epitaxial layer 2 side, as a first conductivity type semiconductor material layer having a band gap different from that of the silicon carbide semiconductor substrate, N ⁻ N of polycrystalline silicon (hereinafter referred to as polysilicon) ⁻ Type polysilicon layer 3 is formed, and SiC epitaxial layer 2 and N ⁻ A first junction (hereinafter, referred to as a hetero junction) is formed between the polysilicon layer 3 and the mold polysilicon layer 3. N ⁻ A Schottky electrode 4 made of a metal that makes Schottky contact with polysilicon is formed on the upper surface of the mold polysilicon layer 3 as a conductor. ⁻ A second junction (hereinafter, referred to as a Schottky junction) is formed between the polysilicon layer 3 and the Schottky electrode 4. As can be seen from FIG. 1, the heterojunction and the Schottky junction are the semiconductor layers N ⁻ They are arranged to face each other with the mold polysilicon layer 3 interposed therebetween. The Schottky electrode 4 also has a function as the anode electrode 30. On the back surface of the SiC substrate 1, a cathode electrode 31 is formed of a conductive material such as a metal.
[0008]
Hereinafter, a specific structure and operation of the silicon carbide semiconductor device according to the first embodiment will be described using an energy band structure from point a to point b in FIG.
FIG. 2A shows an energy band structure in a thermal equilibrium state, that is, a state where both the Schottky electrode 4 and the cathode electrode 31 are grounded. Note that FIG. ⁻ The thickness of the polysilicon layer 3 is N ⁻ (Hereinafter referred to as Xh) that the built-in electric field reaches the polysilicon layer 3 and the distance from the Schottky junction to N ⁻ FIG. 4 shows an energy band structure in a case where the thickness is larger than the sum (Xh + Xs) of a distance (hereinafter, referred to as Xs) that a built-in electric field reaches the type polysilicon layer 3.
Due to the difference between the electron affinity of SiC and polysilicon, χSiC, χPoly, and the work function φ of Schottky metal, N at the heterojunction interface under thermal equilibrium condition ⁻ Storage layer on the side of the polysilicon layer 3 and N at the Schottky junction interface. ⁻ A depletion layer is formed on the type polysilicon layer 3 side, and a barrier φh50 is formed at the heterojunction interface, and a barrier φbn51 is formed at the Schottky junction interface.
In the case of the structure according to the first embodiment, the diode formed by the hetero junction and the diode formed by the Schottky junction are connected in the same pole direction and in series. Therefore, when an appropriate voltage is applied to the Schottky electrode 4 and the cathode electrode 31 is grounded, electrons are transferred from the cathode electrode 31 to the SiC substrate 1, SiC epitaxial layer 2, N ⁻ It flows to the Schottky electrode 4 through the mold polysilicon layer 3. That is, it shows the forward characteristics of the diode.
Next, when the Schottky electrode 4 is grounded and a high voltage is applied to the cathode electrode 31, that is, when a reverse voltage is applied, the energy band structure changes as shown in FIG. At this time, the electrons 80 are blocked by the barrier φh50 generated at the heterojunction interface, and the cutoff state is maintained. Further, the electric field is shielded by the electrons 80 accumulated at the heterojunction interface. ⁻ The electric field hardly reaches the type polysilicon layer 3. That is, N ⁻ The potential of the mold polysilicon layer 3 becomes infinitely equal to the potential of the Schottky electrode 4, and is in a state close to ground. Therefore, N ⁻ The energy band structure of the polysilicon layer 3 and the Schottky electrode 4 is almost the same as the thermal equilibrium state shown in FIG. Therefore, even if a high voltage is applied to the device in the reverse direction, N ⁻ The mold polysilicon layer 3 maintains the cutoff state without causing breakdown. In this cut-off state, a part of the accumulated electrons 80 tunnels or overcomes the barrier φh50 generated at the heterojunction interface, and the N 80 ⁻ Move from the polysilicon layer 3 to the SiC epitaxial layer 2, but due to φbn51 in the Schottky junction, N ⁻ Since the supply of electrons to the polysilicon layer 3 is interrupted, the diode formed by the heterojunction enters a pseudo open state, ⁻ Almost no electrons flow from type polysilicon layer 3 to SiC epitaxial layer 2. As described above, even when a high voltage is applied in the reverse direction, N ⁻ Since the electric field hardly reaches the type polysilicon layer 3, a sufficiently high withstand voltage can be obtained even with a diode with a predetermined Schottky junction.
Where N ⁻ When the thickness of the polysilicon layer 3 is (Xh + Xs) or less, the energy band structure in the thermal equilibrium state is as shown in FIG. 2C, a thin film semiconductor region is formed, and the barrier φh50 at the heterojunction interface becomes As shown in the drawing, due to the influence of the Schottky junction as the second junction, the height is increased by Δφh52 as compared with the band structure of FIG. Along with this, the width of the depletion layer formed on the SiC epitaxial layer 2 side is widened, and when a reverse voltage is applied as shown in FIG. 2D, electrons are more difficult to tunnel or cross the heterojunction interface. That is, by forming the thin film semiconductor region, the blocking property is further improved and a high breakdown voltage can be obtained. The operation in the forward direction shows the same characteristics as when the thin film semiconductor region is not formed.
As described above, in order to apply a PN junction to silicon carbide and obtain a high breakdown voltage, it is necessary to form a deep diffusion layer, and for this reason, impurity introduction by ion implantation has been indispensable. When ion implantation is performed, a crystal defect is introduced into silicon carbide, which causes a problem that a leak current increases. In order to apply a Schottky junction to silicon carbide and to realize a diode with a high breakdown voltage, a diffusion layer is formed at the end of the Schottky electrode as an electric field relaxation region in order to reduce electric field concentration at the end of the Schottky electrode. There is a need. In forming this diffusion layer, ion implantation is also used. However, in the case of silicon carbide, the active heat treatment after implantation requires a high temperature of 1500 ° C. or more, so that the surface of the silicon carbide substrate deteriorates during the heat treatment. In addition, a good Schottky junction cannot be formed on the surface of the deteriorated silicon carbide substrate, and there is a problem that it is difficult to realize a diode with high breakdown voltage. In the first embodiment, since it is not necessary to introduce impurities by high-energy ion implantation, such a problem can be solved and a high-breakdown-voltage semiconductor device capable of suppressing an increase in leak current can be provided.
That is, the semiconductor device according to the first embodiment has N ⁻ Type SiC epitaxial layer 2 and N ⁻ N having a band gap different from that of the SiC epitaxial layer 2 ⁻ Junction (heterojunction) formed by the polysilicon layer 3 and N ⁻ Having a second junction (Schottky junction) formed by the type polysilicon layer 3 and the Schottky electrode 4, ⁻ The thickness of the polysilicon layer 3 is at least N ⁻ Distance of the built-in electric field to the polysilicon layer 3 and N from the second junction ⁻ And a thin-film semiconductor region formed so as to be smaller than the sum of the distance over which the built-in electric field reaches the type polysilicon layer 3.
The N-type in the first embodiment corresponds to the first conductivity type in the claims, and the P-type corresponds to the second conductivity type. Also, N in FIG. ⁻ -Type SiC epitaxial layer 2 is formed in the first semiconductor material layer of claim 1 by N ⁻ The type polysilicon layer 3 corresponds to a second semiconductor material layer, and the Schottky electrode 4 corresponds to a conductor.
Also, N ⁻ Type SiC epitaxial layer 2 is of the first conductivity type (N type in the first embodiment), ⁻ Type polysilicon layer 3 is of the first conductivity type, and N-type ⁻ It has a thin film semiconductor region formed such that a depletion layer is formed in type polysilicon layer 3.
Further, in the first embodiment, the conductor is metal, and the second semiconductor material layer N 2 ⁻ Metal in Schottky contact with the mold polysilicon layer 3. The metal material as the conductor is not necessarily N ⁻ It is not necessary for the metal to be in Schottky contact with the mold polysilicon layer 3, but since the barrier φbn in the Schottky junction affects Δφh52, it is possible to increase Δφh52 by using a metal that makes Schottky contact. As a result, a diode having a high blocking property can be obtained.
In the first embodiment, the Schottky electrode 4 is formed as the second junction. ⁻ The thickness of the polysilicon layer 3 from the hetero junction to N ⁻ If the distance over which the built-in electric field reaches the type polysilicon layer 3, that is, is smaller than Xh, a thin film semiconductor region is formed, and as shown in FIG. ⁻ In comparison with the case where the thickness of the mold polysilicon layer 3 is larger than Xh, the height is increased by Δφh52, and the same effect as in the case where the second junction is provided can be obtained.
That is, in the first embodiment, N ⁻ Type SiC epitaxial layer 2 and N ⁻ N having a band gap different from that of the SiC epitaxial layer 2 ⁻ Junction (heterojunction) formed by the polysilicon layer 3 and N ⁻ The thickness of the polysilicon layer 3 is at least N ⁻ It has a thin film semiconductor region formed so as to be smaller than the distance over which the built-in electric field reaches the mold polysilicon layer 3.
Note that the N where the thin film semiconductor region is formed ⁻ The specific thickness of the polysilicon layer 3 depends on the material of the Schottky ⁻ It changes depending on the impurity concentration of the type polysilicon layer 3 and the concentration of the SiC epitaxial layer 2. For example, if the concentration of the SiC epitaxial layer 2 is 1 × 10 ¹⁶ cm ^-3 , N ⁻ The concentration of the polysilicon layer 3 is 1 × 10 ¹⁶ cm ^-3 , When the material of the Schottky electrode 4 is Ti, ⁻ A sufficient effect can be obtained when the thickness of the mold polysilicon layer 3 is 1000 °.
Further, by using SiC, that is, silicon carbide for the first semiconductor material layer, a semiconductor device with higher withstand voltage can be provided.
Furthermore, by using polysilicon for the second semiconductor material layer, processes such as etching and conductivity control during device manufacturing can be simplified. Note that the same effect can be obtained by forming the second semiconductor material layer with at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon.
[0009]
Embodiment 2
Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 3 is a sectional view of a silicon carbide semiconductor device according to the second embodiment of the present invention.
In FIG. 3, N ⁺ N-type SiC substrate 1 ⁻ By forming SiC epitaxial layer 2 of the type, an N-type silicon carbide semiconductor substrate of the first conductivity type is formed. On the silicon carbide semiconductor substrate, on the first principal surface side, that is, on the SiC epitaxial layer 2 side, as a first conductivity type semiconductor material layer having a band gap different from that of the silicon carbide semiconductor substrate, N ⁻ N made of mold polysilicon ⁻ Type polysilicon layer 3 is formed, and SiC epitaxial layer 2 and N ⁻ A heterojunction is formed between the polysilicon layer 3 and the mold polysilicon layer 3. N ⁻ On the upper surface of the polysilicon layer 3, a semiconductor material of P ⁺ P made of mold polysilicon ⁺ Type polysilicon layer 5 is formed and N ⁻ Type polysilicon layer 3 and P ⁺ A second junction (hereinafter, referred to as a PN junction) is formed between the second polysilicon layer 5 and the mold polysilicon layer 5. As can be seen from the figure, the hetero junction and the PN junction are the semiconductor layers N ⁻ They are arranged to face each other with the mold polysilicon layer 3 interposed therebetween. P ⁺ An anode electrode 30 is formed so as to be in contact with the first main surface side of mold polysilicon layer 5. On the back surface of the SiC substrate 1, a cathode electrode 31 is formed of a conductive material such as a metal.
[0010]
Hereinafter, a specific operation of the silicon carbide semiconductor device in the second embodiment will be described.
First, N in Embodiment 2 ⁻ The thickness of the polysilicon layer 3 is N ⁻ The built-in electric field reaches to the polysilicon layer 3, ie, from the PN junction of Xh and polysilicon to N ⁻ A case where the thickness is larger than the sum (Xh + Xp) of the distance (hereinafter, referred to as Xp) that the built-in electric field reaches the type polysilicon layer 3 will be described.
In the case of the structure according to the second embodiment, N ⁻ A storage layer on the SiC epitaxial layer 2 side of the p-type polysilicon layer 3; ⁺ A depletion layer is formed on the side of the polysilicon layer 5. Also, the diode formed by the hetero junction and the diode formed by the PN junction of polysilicon are connected in the same pole direction and in series. Therefore, when an appropriate voltage is applied to the anode electrode 30 and the cathode electrode 31 is grounded, electrons are transferred from the cathode electrode 31 to the SiC substrate 1, SiC epitaxial layer 2, N ⁻ Type polysilicon layer 3, P ⁺ It flows to the anode electrode 30 via the mold polysilicon layer 5. That is, it shows the forward characteristics of the diode.
Next, when the anode electrode 30 is grounded and a high voltage is applied to the cathode electrode 31, that is, when a reverse voltage is applied, electrons are blocked by the barrier φh generated at the heterojunction interface, and the cutoff state is maintained. Further, since the electric field is shielded by the electrons accumulated at the heterojunction interface, the electric field is shielded compared to the SiC epitaxial layer 2. ⁻ Type polysilicon layer 3 and P ⁺ The electric field hardly reaches the type polysilicon layer 5. That is, N ⁻ Potential of the polysilicon layer 3 is P ⁺ The potentials of the mold polysilicon layer 5 and the anode electrode 30 become infinitely equal to a state close to the ground. Therefore, even if a high voltage is applied to the element in the reverse direction, N ⁻ Type polysilicon layer 3 and P ⁺ The mold polysilicon layer 5 maintains the cutoff state without causing breakdown. In this cut-off state, a part of the accumulated electrons tunnels through or passes over the barrier φh generated at the heterojunction interface, so that N ⁻ To move from the polysilicon layer 3 to the SiC epitaxial layer 2, ⁻ Since there is no supply source of electrons to the polysilicon layer 3, the diode formed by the heterojunction is in a pseudo open state, ⁻ Almost no electrons flow from type polysilicon layer 3 to SiC epitaxial layer 2. As described above, even when a high voltage is applied in the reverse direction, N ⁻ Type polysilicon layer 3 and P ⁺ Since the electric field hardly reaches the type polysilicon layer 5, a sufficiently high withstand voltage can be obtained even with a diode with a predetermined PN junction.
Where N ⁻ When the thickness of the type polysilicon layer 3 is set to (Xh + Xp) or less, a thin film semiconductor region is formed, and the barrier φh50 at the heterojunction interface becomes N ⁻ In comparison with the case where the thickness of the mold polysilicon layer 3 is (Xh + Xp) or more, the thickness is increased by Δφh52. Along with this, the width of the depletion layer formed on the SiC epitaxial layer 2 side is widened, and it becomes difficult for the electrons 80 to tunnel or cross the heterojunction interface when a reverse voltage is applied. That is, by forming the thin film semiconductor region, the blocking property is further improved and a high breakdown voltage can be obtained. The operation in the forward direction shows the same characteristics as when the thin film semiconductor region is not formed.
[0011]
Here, N ⁻ P-type semiconductor material of the second conductivity type instead of the polysilicon layer 3 ⁻ Similar effects can be obtained by using a second conductivity type semiconductor material having a larger band gap than polysilicon for the mold polysilicon layer and the conductor. That is, the first semiconductor material layer N ⁻ Type SiC epitaxial layer 2 is of the first conductivity type, not shown, but the second semiconductor material layer is of the second conductivity type and accumulated in the second semiconductor material layer by a built-in electric field due to the second junction. A configuration having a thin film semiconductor region formed such that a layer is formed is also possible.
[0012]
Embodiment 3
Next, a third embodiment of the present invention will be described with reference to FIG.
FIG. 4 is a sectional view of a silicon carbide semiconductor device according to the third embodiment of the present invention.
In FIG. ⁺ N-type SiC substrate 1 ⁻ By forming SiC epitaxial layer 2 of the type, an N-type silicon carbide semiconductor substrate of the first conductivity type is formed. On the silicon carbide semiconductor substrate, on the first main surface side, that is, on the SiC epitaxial layer 2 side, as a first conductivity type semiconductor material having a band gap different from that of the silicon carbide semiconductor substrate, N ⁻ Type polysilicon layer 3 is formed in an annular shape at a predetermined position, and SiC epitaxial layer 2 and N ⁻ A heterojunction is formed between the polysilicon layer 3 and the mold polysilicon layer 3. N ⁻ N on the upper surface of the polysilicon layer 3 ⁻ N-type polysilicon layer 3 and N ⁻ As a conductor, N is provided so as to be in contact with the exposed first main surface of the SiC epitaxial layer 2 inside the polysilicon layer 3. ⁻ A Schottky electrode 4 made of a metal that makes Schottky contact with the mold polysilicon layer 3 is formed, and a Schottky junction is formed. Note that the Schottky electrode 4 also has a function as the anode electrode 30 as can be seen from the drawing. That is, the diode according to the first embodiment is formed in a ring shape in contact with the outer peripheral portion of anode electrode 30 formed so as to be in contact with SiC epitaxial layer 2. On the back surface of the SiC substrate 1, a cathode electrode 31 is formed of a conductive material such as a metal.
[0013]
Hereinafter, a specific operation of the silicon carbide semiconductor device in the third embodiment will be described.
Here, N ⁻ The thickness of the type polysilicon layer 3 is smaller than a thickness at which a thin film semiconductor region is formed, that is, (Xh + Xs) or less.
Also, N ⁺ Type SiC substrate 1 and N ⁻ A semiconductor substrate composed of the SiC epitaxial layer 2 of the type, an anode electrode 30 and a cathode electrode 31 formed so as to be in contact with the semiconductor substrate, and having the thin film semiconductor region between the anode electrode 30 and the semiconductor substrate. The Schottky electrode 4 and the anode electrode 30, which are conductors in contact with the thin film semiconductor region, have the same potential. Although it has been described that the Schottky electrode 4 also has a function as the anode electrode 30, the Schottky electrode 4 which is a conductor is connected to the anode electrode 30 and has the same potential.
First, when an appropriate voltage is applied to the anode electrode 30 and the cathode electrode 31 is grounded, electrons flow from the cathode electrode 31 to the anode electrode 30 via the SiC substrate 1 and the SiC epitaxial layer 2, and a forward direction of the diode is generated. Show characteristics.
Next, when the anode electrode 30 is grounded and a high voltage is applied to the cathode electrode 31, that is, when a reverse voltage is applied, the thin film semiconductor region is arranged on the outer periphery of the anode electrode 30 where the electric field is concentrated most. And has a higher blocking property than a Schottky diode composed of only the anode electrode 30. Further, the structure of this element is a Schottky diode structure in which a thin-film semiconductor region is provided with an edge termination region arranged annularly on the outer periphery of the anode electrode 30, but unlike the conventional edge termination, ion implantation is performed. And a high-temperature activation anneal can be used, and a good Schottky junction can be formed on the SiC epitaxial layer 2 because the SiC epitaxial layer 2 does not deteriorate. A Schottky diode can be formed.
[0014]
Embodiment 4
Next, a fourth embodiment of the present invention will be described with reference to FIG.
FIG. 5 is a sectional view of a silicon carbide semiconductor device according to the fourth embodiment of the present invention.
In FIG. ⁺ N-type SiC substrate 1 ⁻ By forming SiC epitaxial layer 2 of the type, an N-type silicon carbide semiconductor substrate of the first conductivity type is formed. On the silicon carbide semiconductor substrate, on the first main surface side, that is, on the SiC epitaxial layer 2 side, as a first conductivity type semiconductor material having a band gap different from that of the silicon carbide semiconductor substrate, N ⁻ Type polysilicon layer 3 is formed at a predetermined position, and SiC epitaxial layer 2 and N ⁻ A heterojunction is formed between the polysilicon layer 3 and the mold polysilicon layer 3. N ⁻ N inside the upper surface of the polysilicon layer 3 except for the peripheral portion, ⁺ A mold polysilicon layer 15 is formed. And N ⁻ Type polysilicon layer 3 and N ⁺ N type as a conductor so as to be in contact with ⁻ Type polysilicon layer 3 and N ⁺ A Schottky electrode 4 made of a metal that makes Schottky contact with the mold polysilicon layer 15 is formed, and a Schottky junction is formed. The Schottky electrode 4 also has a function as the anode electrode 30. That is, N ⁻ Type polysilicon layer 3 and N ⁺ The structure is such that only the peripheral portion of the polysilicon layer composed of the mold polysilicon layer 15 is formed to be thin. On the back surface of the SiC substrate 1, a cathode electrode 31 is formed of a conductive material such as a metal. N ⁻ The thickness of the polysilicon layer 3 is N ⁻ Xh of the built-in electric field reaching the polysilicon layer 3 and N from the Schottky junction ⁻ It is smaller than the sum (Xh + Xs) of the distance Xs over which the built-in electric field reaches the type polysilicon layer 3. Thus N ⁻ Type polysilicon layer 3 and N ⁺ The effect of the interface between the polysilicon layer and the Schottky electrode 4 extends to the polysilicon / SiC heterojunction interface by reducing the thickness only in the peripheral portion of the polysilicon layer composed of the type polysilicon layer 15. The barrier height at the heterojunction interface increases.
[0015]
Hereinafter, a specific operation of the silicon carbide semiconductor device according to the fourth embodiment will be described.
First, when an appropriate voltage is applied to the anode electrode 30 and the cathode electrode 31 is grounded, electrons flow from the cathode electrode 31 to the anode electrode 30 via the SiC substrate 1 and the SiC epitaxial layer 2, and a forward direction of the diode is generated. Show characteristics.
Next, when the anode electrode 30 is grounded and a high voltage is applied to the cathode electrode 31, that is, when a reverse voltage is applied, the thin film semiconductor region is arranged on the outer periphery of the anode electrode 30 where the electric field is concentrated most. And has a higher blocking property than a Schottky diode composed of only the anode electrode 30. Further, the structure of this element is a Schottky diode structure in which a thin-film semiconductor region is provided with an edge termination region arranged annularly on the outer periphery of the anode electrode 30, but unlike the conventional edge termination, ion implantation is performed. And a high-temperature activation anneal can be used, and a good Schottky junction can be formed on the SiC epitaxial layer 2 because the SiC epitaxial layer 2 does not deteriorate. A Schottky diode can be formed.
[0016]
Embodiment 5
Next, a fifth embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a sectional view of the silicon carbide semiconductor device according to the fifth embodiment of the present invention.
In FIG. 6, N ⁺ N-type SiC substrate 1 ⁻ By forming SiC epitaxial layer 2 of the type, an N-type silicon carbide semiconductor substrate of the first conductivity type is formed. On the first main surface side, that is, on the SiC epitaxial layer 2 side, a groove 40 (hereinafter, referred to as a trench) having a predetermined depth and a predetermined distance is formed at a predetermined position on the silicon carbide semiconductor substrate. . On the side of the exposed SiC epitaxial layer 2 inside the trench 40, as a first conductivity type semiconductor material having a band gap different from that of the silicon carbide semiconductor substrate, N ⁻ Type polysilicon layer 3 is formed, and SiC epitaxial layer 2 and N ⁻ A heterojunction is formed between the polysilicon layer 3 and the mold polysilicon layer 3. N ⁻ N on the upper surface of the polysilicon layer 3 ⁻ N2 as a conductor so as to be in contact with type polysilicon layer 3 and with the exposed first main surface of SiC epitaxial layer 2 between trenches 40. ⁻ A Schottky electrode 4 made of a metal that makes Schottky contact with the mold polysilicon layer 3 is formed, and a Schottky junction is formed. Note that the Schottky electrode 4 also has a function as the anode electrode 30 as can be seen from the drawing. That is, the diode according to the first embodiment is formed inside the anode electrode 30 at a predetermined interval. On the back surface of the SiC substrate 1, a cathode electrode 31 is formed of a conductive material such as a metal.
Further, the diode according to the first embodiment is annularly arranged on the outer peripheral portion of the anode electrode 30 as in the case of the third embodiment.
[0017]
Hereinafter, a specific operation of the silicon carbide semiconductor device in the fifth embodiment will be described.
Here, N ⁻ The thickness of the type polysilicon layer 3 is smaller than a thickness at which a thin film semiconductor region is formed, that is, (Xh + Xs) or less.
In the silicon carbide semiconductor device according to the fifth embodiment, in addition to the effects of the third embodiment, the thin film semiconductor regions are arranged at predetermined intervals inside anode electrode 30, so that the thin film semiconductor regions The electric field is alleviated by the depletion layer formed on the SiC epitaxial layer 2 side, so that the blocking property can be further improved. In addition, since the thin film semiconductor region is formed inside the trench 40 formed at a predetermined interval, it has an extremely high blocking property.
In this element, a region where the anode electrode 30 and the semiconductor substrate are in contact with each other and a thin film semiconductor region are arranged adjacent to each other at a predetermined interval, and a trench 40 having a predetermined depth is provided at a predetermined position on the semiconductor substrate. And a thin film semiconductor region is formed so as to be in contact with the semiconductor substrate inside the trench 40. In other words, although it has a JBS (Junction Barrier-controlled Schottky-diode) structure, unlike the conventional JBS, it can be formed without using ion implantation and high-temperature activation annealing, and the SiC epitaxial layer 2 can be formed. Since there is no deterioration, a good Schottky junction can be formed on the SiC epitaxial layer 2, and a Schottky diode with a high breakdown voltage can be formed.
[0018]
Embodiment 6
First, a sixth embodiment of the present invention will be described with reference to FIG.
FIG. 7 is a sectional view of the silicon carbide semiconductor device according to the sixth embodiment of the present invention. FIG. 7 shows a cross-sectional structure of an outer peripheral portion of a large number of arranged unit cells, and shows a structure in which two unit cells are continuous.
In FIG. 7, N ⁺ N-type SiC substrate 1 ⁻ By forming SiC epitaxial layer 2 of the type, an N-type silicon carbide semiconductor substrate of the first conductivity type is formed. On this silicon carbide semiconductor substrate, trenches 60 are formed at predetermined intervals on the first main surface side, that is, on the SiC epitaxial layer 2 side. At a predetermined position on the first main surface side of SiC epitaxial layer 2, as a semiconductor material having a band gap different from that of the silicon carbide semiconductor substrate, N ⁻ A mold polysilicon layer 3 is formed. N ⁻ At a predetermined position on the first main surface side of the polysilicon layer 3, N ⁻ N so that it contacts the polysilicon layer 3 ⁺ A mold polysilicon layer 6 is formed. SiC epitaxial layer 2 on the side wall of trench 60 and N ⁻ Type polysilicon layer 3 and N ⁺ A gate electrode 8 is formed adjacent to the mold polysilicon layer 6 via a gate insulating film 7. N to be the source area ⁺ Ohmic contact with the polysilicon layer 6 and N ⁻ A source electrode 9 made of a metal forming a Schottky junction is formed with the mold polysilicon layer 3, and a drain electrode 10 is formed on the second main surface side of the SiC substrate 1. Gate electrode 8 and source electrode 9 are electrically insulated by interlayer insulating film 11.
Here, N ⁻ The thickness of the type polysilicon layer 3 is smaller than a thickness at which a thin film semiconductor region is formed, that is, (Xh + Xs) or less.
[0019]
Hereinafter, a specific operation of the silicon carbide semiconductor device according to the sixth embodiment will be described.
This device is used by grounding the source electrode 9 and applying a positive drain voltage to the drain electrode 10.
At this time, when the gate electrode 8 is grounded, the characteristics of the element show the same characteristics as the reverse characteristics of the diode in the first embodiment. That is, no current flows between the source electrode 9 and the drain electrode 10, and the state is cut off. Also, N ⁻ Since the thickness of the mold polysilicon layer 3 is not more than (Xh + Xs), it has a high blocking property.
Next, when an appropriate positive voltage is applied to the gate electrode 8, N ⁻ Electrons are accumulated in the type polysilicon layer 3 and the SiC epitaxial layer 2, and the electrons tunnel or pass over the barrier φh50 formed at the heterojunction interface. As a result, a current flows between the source electrode 9 and the drain electrode 10 at a predetermined drain voltage. That is, it becomes conductive.
Further, when the positive voltage applied to the gate electrode 8 is removed, the N ⁻ There is no electron accumulation layer in the type polysilicon layer 3 and the SiC epitaxial layer 2 and the layer is cut off by the barrier φh50 at the heterojunction interface.
In the sixth embodiment, the semiconductor device is an N-type source region formed at a predetermined position on a semiconductor substrate made of the first semiconductor material layer. ⁺ Type polysilicon layer 6 and N which is a drain region ⁻ Element comprising a SiC epitaxial layer 2, a channel region as a driving region, and an active region composed of these three regions, wherein the thin-film semiconductor region is annularly disposed on the outer periphery of the active region, The source electrode 9 which is a conductor in contact with the semiconductor region and the source region or the drive region have the same potential. Note that at least one thin film semiconductor region is disposed inside the active region.
Further, the present switch element has a second semiconductor material having a band gap different from that of a semiconductor substrate made of a first semiconductor material layer of the first conductivity type and a first semiconductor material layer formed on a first main surface of the semiconductor substrate. A channel region formed of a semiconductor material layer, a source region formed to be in contact with the first main surface side of the channel region, and a semiconductor substrate, a channel region, and a gate insulating film 7 interposed between the source region and the source region. The semiconductor device includes a gate electrode 8, a drain region formed at a predetermined position on the semiconductor substrate, a source electrode 9 formed to be in contact with the source region, and a drain electrode 10 formed to be in contact with the drain region.
This element has a thin-film semiconductor region similar to that in Embodiment 3 as an edge termination at the outer peripheral portion of a unit cell array in which a large number of unit cells are most likely to concentrate when a drain voltage is applied. Can alleviate the electric field in the outer peripheral portion and have a high drain withstand voltage.
In this element, the region serving as a channel during conduction is N ⁻ Type polysilicon layer 3, N ⁻ Since the thickness of the mold polysilicon layer 3 is extremely thin (Xh + Xs) or less, the channel resistance can be reduced, and a low on-resistance can be realized.
A groove 60 is formed at a predetermined position on the first main surface of the semiconductor substrate. Thereby, a switch element advantageous for integration can be formed.
In the sixth embodiment, a vertical MOSFET has been described as an example of a switch element. However, any switch element having an active region including a source region, a drain region, and a drive region may be used. It is not limited to only 6.
For example, the same effect can be obtained in any of unipolar devices such as MOSFETs and JFETs, bipolar devices typified by IGBTs, and lateral switch devices such as MOSFETs having a RESURF structure.
In each of the embodiments of the present invention, the first conductivity type is described as N type and the second conductivity type is described as P type. However, the first conductivity type is described as P type, and the second conductivity type is described as N type. Can achieve the same effect.
Furthermore, in any of the embodiments of the present invention, the first semiconductor material is described as silicon carbide, and the second semiconductor material is described as polysilicon, but none of them is limited to the above-described semiconductor material. .
For example, the same effect can be obtained with any semiconductor material such as germanium, gallium arsenide, and indium nitride, as a matter of course, with wide gap semiconductors represented by gallium nitride, diamond, zinc oxide, and the like.
Needless to say, the present invention includes modifications within a range not departing from the gist of the present invention.
[Brief description of the drawings]
FIG. 1 shows a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment of the present invention.
FIGS. 2A to 2D show energy band structures in the silicon carbide semiconductor device according to the first embodiment.
FIG. 3 shows a cross-sectional view of a silicon carbide semiconductor device according to a second embodiment of the present invention.
FIG. 4 shows a cross-sectional view of a silicon carbide semiconductor device according to a third embodiment of the present invention.
FIG. 5 shows a cross-sectional view of a silicon carbide semiconductor device according to a fourth embodiment of the present invention.
FIG. 6 shows a cross-sectional view of a silicon carbide semiconductor device according to a fifth embodiment of the present invention.
FIG. 7 shows a cross-sectional view of a silicon carbide semiconductor device according to a sixth embodiment of the present invention.
[Explanation of symbols]
1 ... N ⁺ Type SiC substrate, 2 ... N ⁻ Type SiC epitaxial layer, 3 ... N ⁻ Type polysilicon layer, 4 ... Schottky electrode, 5 ... P ⁻ Type polysilicon layer, 6 ... N ⁺ Type polysilicon layer, 7 gate insulating film, 8 gate electrode, 9 source electrode, 10 drain electrode, 11 interlayer insulating film, 12 groove (trench), 30 anode electrode, 31 cathode electrode, 50 ... Hetero barrier φh, 51 ... Schottky barrier φbn, 52 ... Barrier difference Δφh, 60 ... Trench (groove), 80 ... Electron.

Claims (17)

A first semiconductor material layer and the first semiconductor material layer have a first junction formed by a second semiconductor material layer having a different band gap,
It has a thin film semiconductor region formed such that the thickness of the second semiconductor material layer is at least smaller than the distance that a built-in electric field reaches from the first junction to the second semiconductor material layer. Semiconductor device. A first junction formed by a first semiconductor material layer and a second semiconductor material layer having a different band gap from the first semiconductor material layer,
Having a second junction formed by the second semiconductor material layer and a conductor,
And the thickness of the second semiconductor material layer is at least the distance over which the built-in electric field extends from the first junction to the second semiconductor material layer, and the built-in electric field from the second junction to the second semiconductor material layer. A semiconductor device having a thin film semiconductor region formed so as to be smaller than a sum of a distance to which an electric field reaches. The first semiconductor material layer is of a first conductivity type, the second semiconductor material layer is of a first conductivity type, and a depletion layer is formed in the second semiconductor material layer by a built-in electric field due to the second junction. 3. The semiconductor device according to claim 2, comprising the thin-film semiconductor region formed so as to form a thin film semiconductor region. The first semiconductor material layer is of a first conductivity type, the second semiconductor material layer is of a second conductivity type, and a built-in electric field due to the second junction has an accumulation layer on the second semiconductor material layer. 3. The semiconductor device according to claim 2, comprising the thin-film semiconductor region formed so as to form a thin film semiconductor region. The semiconductor device according to claim 2, wherein the conductor is a metal. The semiconductor device according to claim 5, wherein the metal is a metal that makes a Schottky contact with the second semiconductor material layer. 5. The semiconductor device according to claim 2, wherein said conductor comprises a semiconductor material layer. A semiconductor substrate made of a first semiconductor material layer of a first conductivity type;
In a semiconductor device having an anode electrode and a cathode electrode formed to be in contact with the semiconductor substrate,
Having the thin film semiconductor region between the anode electrode and the semiconductor substrate,
8. The semiconductor device according to claim 1, wherein a conductor in contact with said thin film semiconductor region and said anode electrode have the same potential. 9. The semiconductor device according to claim 8, wherein the thin-film semiconductor region is annularly arranged on an outer peripheral portion of the anode electrode. The semiconductor device according to claim 8, wherein a region where the anode electrode and the semiconductor substrate are in contact with each other and the thin film semiconductor region are arranged adjacent to each other with a predetermined interval. A groove having a predetermined depth at a predetermined position of the semiconductor substrate,
11. The semiconductor device according to claim 8, wherein the thin-film semiconductor region is formed so as to be in contact with a semiconductor substrate inside the trench. The semiconductor device is a switch element having a source region, a drain region, a drive region, and an active region formed of the three regions formed at predetermined positions of a semiconductor substrate made of a first semiconductor material layer. Yes,
The thin-film semiconductor region is disposed in an annular shape on an outer peripheral portion of the active region,
8. The semiconductor device according to claim 1, wherein a conductor in contact with said thin film semiconductor region and said source region or said driving region have the same potential. 13. The semiconductor device according to claim 12, wherein at least one of said thin film semiconductor regions is arranged inside said active region. The switch element, a semiconductor substrate consisting of a first semiconductor material layer of the first conductivity type,
A channel region formed of a second semiconductor material layer having a different band gap from the first semiconductor material layer formed on the first main surface of the semiconductor substrate,
A source region formed to be in contact with the first main surface side of the channel region;
A gate electrode disposed via an insulating film adjacent to the semiconductor substrate, the channel region, and the source region;
A drain region formed at a predetermined position of the semiconductor substrate,
A source electrode formed to be in contact with the source region;
14. The semiconductor device according to claim 12, wherein the switching device has a drain element formed to be in contact with the drain region. The semiconductor device according to claim 14, wherein a groove is formed at a predetermined position on the first main surface of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 15, wherein the first semiconductor material layer is silicon carbide. 17. The semiconductor device according to claim 1, wherein the second semiconductor material layer is at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon.

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