JP2004247490A - Silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high breakdown voltage silicon carbide semiconductor device exhibiting excellent current amplification factor h<SB>FE</SB>. <P>SOLUTION: The silicon carbide semiconductor device has a first conductivity type collector region, i.e. an N<SP>-</SP>-type SiC epitaxial region 20, a second conductivity type base region, i.e. a P<SP>-</SP>-type polysilicon base region 30, being formed on the N<SP>-</SP>-type SiC epitaxial region 20, a first conductivity type emitter region, i.e. an N<SP>+</SP>-type polysilicon emitter region 40, being formed on the P<SP>-</SP>-type polysilicon base region 30, a collector electrode 90 being connected with the first conductivity type collector region, i.e. the N<SP>-</SP>-type SiC epitaxial region 20, a base electrode 80 being connected with the P<SP>-</SP>-type polysilicon base region 30, and an emitter electrode 70 being connected with the N<SP>+</SP>-type polysilicon emitter region 40. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device.
[0002]
[Prior art]
[Non-Patent Document] "Paper: Yi Tang, Jeffery B. Fedison and T. Paul Chow, Materials Science Forum Vols. 389-393 (2002) pp. 1329-1332."
[0003]
2. Description of the Related Art In recent years, studies on semiconductor elements utilizing the extremely stable properties of silicon carbide (SiC), which are extremely thermally and chemically stable, have been actively conducted. Silicon carbide has a larger energy gap (forbidden band width) Eg than silicon. For example, since 4g type crystal has Eg = 3.3 eV, it has excellent electric breakdown voltage characteristics and is suitable for power devices such as power control elements. The application of is expected. As an example, as exemplified in the above-mentioned non-patent literature, there is a vertical bipolar transistor for high withstand voltage and large current, which has a feature that the on-resistance of the element can be reduced.
[0004]
[Problems to be solved by the invention]
However, the SiC high breakdown voltage bipolar transistor has the following problems. That is, a phenomenon in which a depletion layer spreads in the base region due to a reverse voltage applied to the collector electrode and reaches the emitter region is called punch-through. However, in order to obtain a high breakdown voltage, this punch-through must not be caused. For this purpose, it is necessary to increase the impurity concentration in the base region and increase the base length. However, in that case, the emitter injection efficiency is lowered and the current amplification factor h _FE Becomes smaller. That is, the breakdown voltage of the element and the current amplification factor h _FE There is a problem that there is a trade-off relationship.
[0005]
The present invention has been made to solve the problems of the prior art as described above, and has a current amplification factor h. _FE It is an object of the present invention to provide a high breakdown voltage silicon carbide semiconductor device excellent in performance.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, in the present invention, a collector region made of a first conductivity type silicon carbide semiconductor, a base region made of a second conductivity type semiconductor material forming a heterojunction with the silicon carbide semiconductor, and A silicon carbide semiconductor device having a collector region of one conductivity type is formed.
[0007]
【The invention's effect】
By implementing the present invention, the current amplification factor h _FE It is possible to provide a silicon carbide semiconductor device having a high withstand voltage excellent in quality.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings by way of examples.
[0009]
The polytype of silicon carbide (SiC) used in the following examples is typically 4H, but other polytypes such as 6H and 3C may be used. In addition, although an example in which polycrystalline silicon is used as a semiconductor material for forming a heterojunction with a silicon carbide semiconductor has been described, such a semiconductor material is also more suitable than a silicon carbide semiconductor such as single crystal silicon or amorphous silicon. Any semiconductor material having a small energy gap Eg can be used.
[0010]
Further, in the following examples, a silicon carbide semiconductor device having a structure in which a collector electrode is formed on the back surface of a semiconductor substrate, an emitter electrode is arranged on the substrate surface, and a current flows in the device in a vertical direction has been described. The present invention is also applicable to a semiconductor device having a structure in which a collector electrode is arranged on the substrate surface in the same manner as an emitter electrode and a current flows in a lateral direction.
[0011]
Further, in the following embodiment, for example, a configuration is described in which the collector region (20 in the following embodiment) is N-type and the base region (30 in the following embodiment) is P-type. The combination of types is not limited to this, and for example, a configuration may be adopted in which the collector region is P-type and the base region is N-type.
[0012]
Needless to say, the present invention includes modifications without departing from the gist of the present invention.
[0013]
(Example 1)
FIG. 1 shows a first embodiment of a silicon carbide semiconductor device according to the present invention.
[0014]
N serving as a collector region of the first conductivity type ⁻ Type SiC epitaxial region 20 is N ⁺ It is laminated on the type SiC substrate 10. A predetermined region on the epitaxial region 20 has a P-type base region of the second conductivity type. ⁻ A type polycrystalline silicon base region 30 is formed. In this case, the semiconductor material forming a heterojunction with the silicon carbide semiconductor is polycrystalline silicon, and P ⁻ Type polycrystalline silicon base region 30 and N ⁻ Heterojunction with type SiC epitaxial region 20. As shown in the energy band diagram of FIG. 15, a heterojunction barrier 210 as an energy barrier exists at the heterojunction interface.
[0015]
Also, P ⁻ In a predetermined region of the surface layer of the base type polycrystalline silicon base region 30, an N-type emitter region of the first conductivity type is provided. ⁺ Type polysilicon emitter region 40 and P ⁺ Form polycrystalline silicon contact region 50 is formed.
[0016]
N ⁺ Type polysilicon emitter region 40 is connected to emitter electrode 70, ⁻ Type polycrystalline silicon base region 30 is P ⁺ It is connected to base electrode 80 via type polycrystalline silicon contact region 50. N ⁺ A collector electrode 90 is formed on the back surface of the type SiC substrate 10, and the collector region 90 is a first conductivity type collector region. ⁻ Type SiC epitaxial region 20 is N ⁺ It is connected to the collector electrode 90 via the mold SiC substrate 10.
[0017]
Reference numeral 60 denotes an interlayer insulating film, which functions to protect and stabilize a semiconductor surface and a bonding surface.
[0018]
The silicon carbide semiconductor device (FIG. 1) in the present embodiment is used by grounding the emitter electrode 70 and applying a positive voltage Vc to the collector electrode 90. At this time, if no voltage is applied to the base electrode 80, the characteristics of the device become P ⁻ Type polycrystalline silicon base region 30 and N ⁻ Reverse bias characteristics of the heterojunction diode with the SiC epitaxial region 20.
[0019]
That is, a depletion layer extends toward the epitaxial region 20 according to the collector voltage Vc. Meanwhile P ⁻ In the polycrystalline silicon base region 30, electrons cannot accumulate at the energy barrier 210 and accumulate at the junction interface. FIG. 16 shows this state (electrons are shown by black circles in the figure). The lines of electric force corresponding to the depletion layer extending to the epitaxial region 20 end at this electron accumulation layer, and P ⁻ The electric field is shielded on the type polycrystalline silicon base region 30 side. Therefore, P first ⁻ The type polycrystalline silicon base region 30 does not cause breakdown, and a current starts to flow rapidly from the collector electrode 90 to the emitter electrode 70 only when the collector voltage Vc becomes the breakdown voltage Vb.
[0020]
In the reverse bias characteristics of the heterojunction diode as described above, P ⁻ Experiments have confirmed that a withstand voltage of 300 V or more can be ensured even if the thickness of the mold polycrystalline silicon base region 30 is reduced to, for example, about 20 nm (200 Å). Therefore, in the silicon carbide semiconductor device using the structure of the present invention, even if the thickness of hetero semiconductor region 30 is reduced, the above P ⁻ There is no possibility of punch-through due to the effect of shielding the electric field on the side of the base polycrystalline silicon base region 30, and the base length is at least P ⁻ Since the thickness of the polycrystalline silicon base region 30 can be reduced to, for example, about 20 nm (200 angstroms), the base resistance can be significantly reduced.
[0021]
On the other hand, when a positive voltage is applied to the base electrode 80 in a state where a voltage is applied between the collector and the emitter, as shown in the energy band diagram of FIG. ⁻ Since the energy level of the base type polycrystalline silicon base region 30 is lowered, P ⁻ Holes are injected into type polycrystalline silicon base region 30 (base current starts to flow). At the same time, N ⁺ Type polysilicon emitter region 40 to P ⁻ A large amount of electrons move to the type polycrystalline silicon base region 30. The electrons reach and accumulate at the junction interface, of which a significant amount migrates over the energy barrier 210 and down a steep energy potential slope in the SiC epitaxial region 20. As a result, even when the collector voltage Vc is equal to or lower than the breakdown voltage Vb, current starts to flow.
[0022]
That is, the silicon carbide semiconductor device according to the present invention controls the current between collector electrode 90 and emitter electrode 70 by maintaining collector voltage Vc at Vb or lower and changing the voltage applied to base electrode 80 in this state. Is what you do.
[0023]
Next, an example of a method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described with reference to the cross-sectional views of FIGS.
[0024]
First, in the step of FIG. ⁺ The impurity concentration is, for example, 1 × 10 ¹⁴ ~ 1 × 10 ¹⁸ cm ^-3 , N having a thickness of 1 to 100 μm ⁻ Type SiC epitaxial region 20 is formed.
[0025]
In the step of FIG. 7, after the sacrificial oxidation is performed on the epitaxial region 20 and the sacrificial oxide film is removed, the polycrystalline silicon which becomes the polycrystalline silicon base region 30 is reduced in pressure from, for example, about 5 nm (50 angstroms) to about 10 μm. Deposition is performed using a CVD method, and then, a desired impurity (for example, boron or the like) is introduced into the polycrystalline silicon to form P ⁻ Type polycrystalline silicon base region 30. As a method for introducing impurities, a heavily doped deposition film is deposited further on the deposited polycrystalline silicon base region 30, and impurities in the deposited film are removed by heat treatment at about 600 to 1000 ° C. Impurities may be introduced directly into polycrystalline silicon base region 30 by thermal diffusion into region 30 or by ion implantation.
[0026]
In the process of FIG. ⁻ A desired impurity (for example, phosphorus) is introduced into ⁺ Forming a polycrystalline silicon emitter region 40. As a method for introducing impurities, a heavily doped deposition film is deposited thereon by using a mask material 190 having a predetermined region opened, and the impurities in the deposition film are removed by heat treatment at about 600 to 1000 ° C. Thermal diffusion into polycrystalline silicon base region 30 or introduction of impurities directly into polycrystalline silicon base region 30 by ion implantation ⁺ The polycrystalline silicon emitter region 40 may be formed.
[0027]
In the process of FIG. ⁻ A desired impurity (for example, boron or the like) is introduced into ⁺ Form a polycrystalline silicon contact region 50. As a method for introducing impurities, a heavily doped deposition film is deposited thereon by using a mask material 191 having a predetermined region opened, and the impurities in the deposition film are removed by heat treatment at about 600 to 1000 ° C. Thermal diffusion into the polycrystalline silicon base region 30 or introduction of impurities directly into the polycrystalline silicon base region 30 by ion implantation ⁺ Form polycrystalline silicon contact region 50 may be formed.
[0028]
In the step of FIG. 10, after removing the mask material 191, a heat treatment at, for example, about 1000 ° C. is performed to activate the impurities introduced into the polycrystalline silicon base region 30 in the steps of FIGS. In addition, in order to improve the mobility of carriers in the polycrystalline silicon base region 30, for example, the polycrystalline silicon base region 30 may be annealed to increase the single crystal or polycrystalline grain size. Crystallization may be performed by irradiating the polycrystalline silicon base region 30 with laser light.
[0029]
In the step of FIG. 11, an interlayer insulating film 60 is deposited using a CVD method.
[0030]
Thereafter, although not specifically shown, a predetermined region of the interlayer insulating film 60 is opened, and N ⁺ Emitter electrode 70 so as to be in contact with ⁺ Base electrodes 80 are respectively formed so as to be in contact with type polycrystalline silicon contact region 50. Furthermore, N ⁺ A metal film is deposited as a collector electrode 90 on the back surface of the SiC substrate 10 and heat-treated at, for example, about 600 to 1200 ° C. to form an ohmic electrode.
[0031]
Thus, the silicon carbide semiconductor device shown in FIG. 1 is completed.
[0032]
As exemplified in this embodiment and the following embodiments, by implementing the present invention, it is possible to use a heterojunction with a semiconductor (polycrystalline silicon in each embodiment) forming a heterojunction with a silicon carbide semiconductor. , Element breakdown voltage and current amplification factor h _FE A silicon carbide semiconductor device which is a low-resistance / high-withstand-voltage high-speed switching element with an improved trade-off can be manufactured with a simple configuration.
[0033]
Hereinafter, taking the silicon carbide semiconductor device shown in FIG. 1 as an example, the element withstand voltage and the current amplification factor h in the silicon carbide semiconductor device according to the present invention will be described. _FE The improvement of the trade-off will be described in detail.
[0034]
First, when a positive voltage is applied to the base electrode 80 with the collector voltage Vc applied, P ⁻ Holes are injected into the type polycrystalline silicon base region 30. The injected holes are N ⁺ It moves to the polycrystalline silicon emitter region 40. On the other hand, holes are blocked by the energy barrier 210 formed at the hetero junction and cannot enter the SiC epitaxial region 20. Therefore, even under the condition that the collector current becomes large, the amount of holes injected from the base electrode 80 does not increase and the high current amplification factor h _FE Can be held.
[0035]
Also, P ⁻ Even when the impurity concentration of the base polycrystalline silicon base region 30 is reduced, electrons accumulate at the heterojunction interface when a high collector voltage is applied and the electric field is shielded, so that a high breakdown voltage element can be obtained without punch-through. . That is, while maintaining a high breakdown voltage, the base region P ⁻ Since the impurity concentration of the base type polycrystalline silicon base region 30 can be reduced, the emitter injection efficiency is high and the current amplification factor h _FE Is big.
[0036]
In the silicon carbide semiconductor device according to the present invention, as described above, by utilizing the hetero junction of silicon carbide and the semiconductor material, the element breakdown voltage and the current amplification factor h _FE Can be improved.
[0037]
In general, when the concentration of the base region is reduced, the base resistance increases and the avalanche withstand capability decreases, but in the present silicon carbide semiconductor device, the base region P ⁻ Even if the thickness of the polycrystalline silicon base region 30 is reduced, electrons are still accumulated at the heterojunction interface and the electric field is shielded. Therefore, the base length (the thickness of the polycrystalline silicon base region 30) can be reduced to, for example, 20 nm (200 Å). As a result, the base resistance can be significantly reduced, so that the avalanche withstand capability can be maintained sufficiently large. Furthermore, the fact that the base thickness can be reduced has the effect of shortening the traveling time of carriers in the base region, increasing the response speed, and enabling operation in a high-frequency region.
[0038]
Further, in the present silicon carbide semiconductor device, in the step of manufacturing the basic element structure, it is not necessary to introduce impurities by ion implantation into the silicon carbide semiconductor. As a result, an impurity activation annealing at 1500 ° C. or higher for recovery of crystallinity is not required, so that the manufacturing process is easy and deterioration of surface morphology caused by high-temperature annealing can be avoided.
[0039]
Further, in this embodiment, P ⁻ Polycrystalline silicon was used as a semiconductor material for forming the type polycrystalline silicon base region 30. Since polycrystalline silicon can be easily deposited on a silicon carbide substrate, or oxidized, patterned, selectively etched, selectively controlled in conductivity, and the like, the manufacturing process of the present silicon carbide semiconductor device can be simplified.
[0040]
In the embodiment shown in FIG. ⁻ P on the SiC epitaxial region 20 ⁻ Type polycrystalline silicon base region 30 is deposited and its P ⁻ N-type polycrystalline silicon base region 30 ⁺ Type polysilicon emitter region 40 and P ⁺ An example of a bipolar transistor for high breakdown voltage forming the polysilicon contact region 50 is shown in FIG. ⁻ When the base electrode 80 directly becomes an ohmic electrode with respect to the type polycrystalline silicon base region 30, P ⁺ The type polycrystalline silicon contact region 50 may not be provided. Also N ⁺ Type polysilicon emitter region 40 and P ⁺ The formation of the polycrystalline silicon contact region 50 is based on P ⁻ In the example described above, a desired impurity is introduced into base type polycrystalline silicon base region 30. ⁻ Type polycrystalline silicon base region 30 is formed, and N ⁺ Type polysilicon emitter region 40 and P ⁺ The polycrystalline silicon contact region 50 may be formed by deposition.
[0041]
As exemplified in this embodiment, a collector region of the first conductivity type, a base region of the second conductivity type formed on the collector region, and an emitter region of the first conductivity type formed on the base region A collector electrode connected to the collector region, a base electrode connected to the base region, and an emitter electrode connected to the emitter region, wherein the collector region is made of a silicon carbide semiconductor; When a silicon carbide semiconductor device is characterized in that the base region is made of a semiconductor material that forms a heterojunction with a silicon carbide semiconductor, the device withstand voltage can be improved by utilizing the heterojunction between silicon carbide and the semiconductor material. Current amplification factor h _FE And a high-speed switching element with low resistance / high withstand voltage that has improved the trade-off can be realized with a simple configuration.
[0042]
In the present silicon carbide semiconductor device, carriers injected from the base electrode into the base region made of the semiconductor material can move to the emitter region, but are blocked by the energy barrier formed at the hetero junction, and the collector made of silicon carbide You cannot enter the area. Therefore, even under the condition that the collector current becomes large, the carrier injected from the base electrode into the base region does not increase, and the high current amplification factor h _FE Can be held.
[0043]
Even when the impurity concentration in the base region made of the semiconductor material is reduced, electrons (generally, carriers) accumulate at the heterojunction interface when a high collector voltage is applied, and the electric field is shielded. A high breakdown voltage element can be obtained. That is, since the impurity concentration in the base region can be reduced while maintaining a high breakdown voltage, the emitter injection efficiency is high and the current amplification factor h is high. _FE Is big.
[0044]
In the present silicon carbide semiconductor device, by utilizing the heterojunction between silicon carbide and the heterojunction semiconductor material, element breakdown voltage and current amplification factor h _FE Can be improved.
[0045]
In general, when the concentration of the base region is reduced, the base resistance is increased and the avalanche withstand capability is reduced. However, in the present silicon carbide semiconductor device, even when the thickness of the base region is reduced, electrons still remain at the heterojunction interface. The accumulated electric field is shielded. Therefore, the base length (base region (P in each embodiment) ⁻ The thickness of the polycrystalline silicon base region 30) can be reduced to, for example, 20 nm (200 angstroms). As a result, the base resistance can be significantly reduced, so that the avalanche withstand capability can be maintained sufficiently large. Furthermore, the fact that the base thickness can be made thinner has the effect of shortening the traveling time of carriers in the base region, increasing the response speed, and enabling operation in the high frequency region.
[0046]
Further, in the present silicon carbide semiconductor device, in the manufacturing process of the basic element structure, it is not necessary to introduce impurities by ion implantation into the silicon carbide semiconductor. As a result, annealing for impurity activation at 1500 ° C. or higher that also serves to recover crystallinity is unnecessary, so that the manufacturing process is easy and deterioration of surface morphology caused by high-temperature annealing can be avoided.
[0047]
(Example 2)
FIG. 2 shows a second embodiment of the silicon carbide semiconductor device according to the present invention. The difference from the configuration shown in FIG. ⁻ N, which is a collector region of the first conductivity type, under the base type polysilicon base region 30 ⁻ N-type SiC epitaxial region 20 ⁻ N, which is a first conductivity type high impurity concentration semiconductor region having an impurity concentration higher than that of the SiC epitaxial region 20 ⁺ That is, the type SiC region 100 is formed. N ⁺ Type SiC region 100 is P ⁻ It contacts the type polycrystalline silicon base region 30 to form a heterojunction.
[0048]
P ⁻ Type polycrystalline silicon base region 30 ⁺ Heterojunction with the SiC region 100 ⁺ Since a large amount of carriers exist in the type SiC region 100, the depletion layer does not expand, and the thickness of the energy barrier is formed to be extremely thin. FIG. 18 shows this state. The energy level shown by the dotted line on the SiC side is N in the first embodiment. ⁻ The solid line at the right end and the steep slope is N in the present embodiment. ⁺ 1 shows a state in the type SiC region 100. As described above, when the energy barrier becomes extremely thin, when a positive voltage is applied to the base electrode 80 with a voltage applied between the collector and the emitter, N ⁺ Type polysilicon emitter region 40 to P ⁻ A large amount of electrons traveling to the type polycrystalline silicon base region 30 can pass through the ultra-thin energy barrier. This eliminates electrons that cannot be accumulated at the junction interface without crossing the barrier. _FE Is improved.
[0049]
That is, in this embodiment, in addition to the effects described in the first embodiment, the controllability of the element main current by the base current is improved, and the current amplification factor h _FE Is improved.
[0050]
Then P ⁻ Type polycrystalline silicon base region 30 and N ⁺ Pressure resistance with the SiC region 100 is low, ⁺ P where the SiC region 100 is not formed ⁻ Type polycrystalline silicon base region 30 and N ⁻ P-type SiC epitaxial region 20 junction ⁻ N from the lower part of the polycrystalline silicon base region 30 ⁻ Since a depletion layer extends in the p-type epitaxial region 20, P ⁻ Type polycrystalline silicon base region 30 and N ⁺ Since the electric field applied to the junction with the type SiC region 100 is shielded, a decrease in the collector breakdown voltage can be prevented.
[0051]
As exemplified in the present embodiment, a first conductivity type high impurity concentration semiconductor region having an impurity concentration higher than at least the collector region is formed in a part of the collector region surface layer below the base region, When the silicon carbide semiconductor device is characterized in that the high impurity concentration semiconductor region is in contact with the base region, the extension of the depletion layer to the high concentration semiconductor region is reduced, and the thickness of the energy barrier is reduced. Is done. As a result, in the present silicon carbide semiconductor device, in addition to the effects of the invention exemplified in the first embodiment, carriers easily pass through the energy barrier, and control of the main current by the base current becomes easy (current amplification factor h _FE Becomes higher).
[0052]
(Example 3)
FIG. 3 shows a third embodiment of the silicon carbide semiconductor device according to the present invention. The difference from the configuration shown in FIG. 2 is that the NC of the surface layer of the SiC epitaxial region 20 which is the collector region of the first conductivity type. ⁺ This is that a P-type SiC electric field relaxation region 110, which is a second conductivity type electric field relaxation region, connected to the emitter electrode 70 is disposed in a portion where the type SiC region 100 is not formed.
[0053]
In the present embodiment, when a voltage is applied to the collector electrode 90, the N-type ⁻ The depletion layer can be extended to the type epitaxial region 20. And the depletion layer is P ⁻ Type polycrystalline silicon base region 30 and N ⁺ Since the electric field applied to the junction with the type SiC region 100 can be more effectively shielded as compared with the second embodiment, it is possible to reduce the leak current and prevent the collector breakdown voltage from lowering.
[0054]
In the present embodiment, the example in which the P-type SiC electric field relaxation region 110 is connected to the emitter electrode 70 has been described.
[0055]
As exemplified in the present embodiment, a second conductivity type electric field relaxation region is formed in a part of the collector region surface layer below the base region, thereby configuring a silicon carbide semiconductor device. In addition to the effects of the above-described invention, since the withstand voltage of the element can be designed so as to be determined by the reverse withstand voltage of the diode between this region and the collector region by the electric field relaxation region of the second conductivity type, a high withstand voltage element can be obtained. Further, the electric field applied to the heterojunction between the base region and the collector region (or the high-concentration semiconductor region) is relaxed by the depletion layer extending from the junction interface between the second conductivity type electric field relaxation region and the collector region to the collector region. Thus, the leakage current can be reduced.
[0056]
(Example 4)
FIG. 4 shows a fourth embodiment of the silicon carbide semiconductor device according to the present invention. The difference from the configuration shown in FIG. 3 is that instead of the P-type SiC electric field relaxation region 110, N ⁻ The point is that an insulating film 120 which is an insulating electric field relaxation layer is formed in a groove 201 formed in a predetermined region of the surface layer of the SiC epitaxial region 20.
[0057]
By applying this embodiment, N ⁺ The depletion layer can be extended from a deeper position with respect to the ⁻ Type polycrystalline silicon base region 30 and N ⁺ The electric field applied to the junction with the type SiC region 100 is easily shielded. As a result, it is possible to effectively reduce the leak current and prevent a decrease in the collector breakdown voltage.
[0058]
Further, in the manufacturing process of the present embodiment, unlike the third embodiment, it is not necessary to form the P-type SiC electric field relaxation region 110, so that it is not necessary to introduce impurities by ion implantation into the silicon carbide semiconductor. As a result, the impurity activation annealing at 1500 ° C. or higher, which also serves as the recovery of the crystallinity, is unnecessary, and the load on the manufacturing process can be reduced, and the deterioration of the surface morphology caused by the high-temperature annealing can be avoided.
[0059]
FIG. 4 illustrates an example in which the groove 201 is formed and the insulating film 120 is formed therein. However, no separate groove is formed, and N ⁻ Even if an insulating film is formed directly on the surface of the type SiC epitaxial region 20, the effect of preventing a decrease in collector withstand voltage can be obtained.
[0060]
As exemplified in the present embodiment, a silicon carbide semiconductor device in which an insulating electric field relaxation layer is formed instead of the second conductivity type electric field relaxation area, provides a base region and a collector. Since the electric field applied to the heterojunction with the region (or the high-concentration semiconductor region) is alleviated by the insulating electric field relaxation layer, the withstand voltage of the element can be increased and the leak current can be reduced. Furthermore, in the present silicon carbide semiconductor device, since the electric field relaxation region of the second conductivity type need not be formed, it is not necessary to introduce impurities by ion implantation into the silicon carbide semiconductor. As a result, annealing for impurity activation at 1500 ° C. or higher that also serves to recover crystallinity is unnecessary, so that the manufacturing process is easy and deterioration of surface morphology caused by high-temperature annealing can be avoided.
[0061]
(Example 5)
FIG. 5 shows a fifth embodiment of the silicon carbide semiconductor device according to the present invention. N serving as a collector region of the first conductivity type ⁻ Type epitaxial region 20 is N ⁺ It is laminated on the type SiC substrate 10. A groove 200 having a predetermined depth is formed in a predetermined region on the surface of the epitaxial region 20. Along the trench 200, a predetermined region on the epitaxial region 20 is provided with a P-type base region of the second conductivity type. ⁻ A type polycrystalline silicon base region 30 is formed. At least a part of the groove 200 is P ⁻ It is in contact with the mold polycrystalline silicon 30.
[0062]
P ⁻ The type polycrystalline silicon base region 30 and the SiC epitaxial region 20 have a heterojunction, and an energy barrier 210 exists at the junction interface as shown in the energy band diagram of FIG. Also, along the groove 200, N ⁺ Type polysilicon emitter region 40 is P ⁻ Formed on the type polycrystalline silicon base region 30. A gate electrode 160 is formed in the trench 200 via a gate insulating film 170. P ⁻ P-type polycrystalline silicon base region 30 ⁺ Form polycrystalline silicon contact region 50 is formed.
[0063]
And N ⁺ An emitter electrode 70 is formed in the p-type polysilicon emitter region 40, ⁺ A base electrode 80 is provided in the ⁺ Collector electrodes 90 are respectively connected to the back surface of the type SiC substrate 10.
[0064]
Reference numeral 60 denotes an interlayer insulating film, which functions to protect and stabilize a semiconductor surface and a bonding surface. Reference numeral 180 denotes a P-type SiC electric field alleviation region, which alleviates the electric field applied to the gate insulating film 170 at the bottom of the groove 200 with respect to the collector electric field.
[0065]
The difference from the first embodiment in configuration is that N ⁺ Type polysilicon emitter region 40 and P ⁻ N through the polycrystalline silicon base region 30 in the depth direction. ⁻ That is, a groove 200 reaching the type epitaxial region 20 is provided, and a gate electrode 160 is provided in the groove 200 via a gate insulating film 170. In order to reduce the electric field applied to the gate insulating film 170 at the bottom of the groove 200, a P-type SiC electric field relaxation region 180, which is a second conductivity type electric field relaxation region, is provided. The P-type SiC electric field relaxation region 180 has the same effect as the third embodiment.
[0066]
In this embodiment, the emitter electrode 70 is grounded, and the collector electrode 90 is applied with a positive voltage Vc. At this time, if no voltage is applied to the base electrode 80, the characteristics of the device become P ⁻ Type polycrystalline silicon base region 30 and N ⁻ Reverse bias characteristics of the heterojunction diode with the SiC epitaxial region 20.
[0067]
The reverse bias characteristics of this heterojunction diode are the same as those described in the first embodiment.
[0068]
Next, the forward characteristics in the fifth embodiment will be described.
[0069]
When a predetermined positive voltage is applied to each of the base electrode 80 and the gate electrode 160 with the voltage Vc applied between the collector and the emitter, as in the first embodiment, as shown in FIG. ⁻ Since the energy level of the base type polycrystalline silicon base region 30 is lowered, P ⁻ Holes are injected into type polycrystalline silicon base region 30 (base current starts to flow). At the same time, N ⁺ Type polysilicon emitter region 40 to P ⁻ A large amount of electrons move to the type polycrystalline silicon base region 30.
[0070]
At this time, the positive voltage applied to the gate electrode 160 causes N ⁻ Type epitaxial region 20 is in an accumulation state, and N ⁺ A mold layer is formed. Furthermore, this positive voltage allows P ⁻ Type polycrystalline silicon base region 30 and N ⁻ An electric field acts on the heterojunction interface with the type SiC epitaxial region 20, and the thickness of the energy barrier formed by the heterojunction surface is reduced. This results in a band structure similar to that of the heterojunction interface shown in the second embodiment, which can also be explained with reference to FIG. That is, the energy level indicated by the steep dotted line at the right end in FIG. 18 is before the gate voltage is applied, and the solid line at the right end is steep after the gate voltage is applied.
[0071]
As a result, N ⁺ Type polysilicon emitter region 40 to P ⁻ A large amount of electrons traveling to the type polysilicon base region 30 can pass through the thinned energy barrier. This eliminates electrons that cannot be accumulated at the junction interface without crossing the barrier. _FE Is greatly improved as compared with the first embodiment.
[0072]
That is, in the silicon carbide semiconductor device of Example 5, in addition to the effects described in Example 1, the controllability of the element main current by the base current is improved, and the current amplification factor h _FE Is improved.
[0073]
At this time, the electric field applied to the gate insulating film at the bottom of the trench 200 due to the high collector electric field is alleviated by the P-type SiC electric field alleviating region 180, so that a decrease in collector breakdown voltage can be prevented.
[0074]
Next, an example of a method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described with reference to the cross-sectional views of FIGS. 6 to 10 and FIGS.
[0075]
The steps in FIGS. 6 to 10 are the same as the steps described in the first embodiment, and a description thereof will be omitted.
[0076]
In the process of FIG. 12, the groove 200 is formed by using the mask material 192 by, for example, a plasma etching method. The groove 200 is N ⁺ Type polysilicon emitter region 40 and P ⁻ N-type polycrystalline silicon base region 30 in the depth direction, ⁻ It has a depth reaching the type SiC epitaxial region 20.
[0077]
In the process of FIG. 13, aluminum ions are multi-stagely implanted at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 keV to 3 MeV, and heat treatment is performed to activate the implanted ions. , A P-type SiC electric field relaxation region 180 is formed. Thereafter, as the gate insulating film 170, for example, a CVD oxide film is deposited to a thickness of about 100 nm (1000 angstroms).
[0078]
In the step of FIG. 14, for example, the trench 200 is filled with polysilicon by LP-CVD (low-pressure CVD) to form the gate electrode 160, and then the interlayer insulating film 60 is deposited by CVD.
[0079]
Thereafter, although not specifically shown, a predetermined region of the interlayer insulating film 60 is opened, and N ⁺ Emitter electrode 70 so as to be in contact with ⁺ Base electrodes 80 are respectively formed so as to be in contact with type polycrystalline silicon contact region 50. Further, a metal film is deposited on the back surface of the SiC substrate 10 as the collector electrode 90, and heat-treated at, for example, about 600 to 1200 ° C. to form an ohmic electrode.
[0080]
Thus, the silicon carbide semiconductor device shown in FIG. 5 is completed.
[0081]
In this silicon carbide semiconductor device, in addition to the effects described in the first embodiment, the controllability of the element main current by the base current is improved, and the current amplification factor h _FE Is improved.
[0082]
In the embodiment of FIG. ⁻ P on the SiC epitaxial region 20 ⁻ Type polycrystalline silicon base region 30 is deposited and its P ⁻ N-type polycrystalline silicon base region 30 ⁺ Type polysilicon emitter region 40 and P ⁺ An example of a bipolar transistor for high breakdown voltage forming the polysilicon contact region 50 is shown in FIG. ⁻ When the base electrode 80 directly becomes an ohmic electrode with respect to the type polycrystalline silicon base region 30, P ⁺ The type polycrystalline silicon contact region 50 may not be provided. Also N ⁺ Type polysilicon emitter region 40 and P ⁺ The formation of the polycrystalline silicon contact region 50 is based on P ⁻ In the example described above, a desired impurity is introduced into base type polycrystalline silicon base region 30. ⁻ Type polycrystalline silicon base region 30 is formed, and N ⁺ Type polysilicon emitter region 40 and P ⁺ The polycrystalline silicon contact region 50 may be formed by deposition.
[0083]
Further, the gate electrode 160 may be connected to the base electrode 80. The P-type SiC electric field relaxation region 180 for protecting the gate insulating film 170 at the bottom of the groove 200 may not be provided. Although the P-type SiC electric field relaxation region has been described by way of example in which aluminum is ion-implanted, it may be manufactured by using boron or gallium, or by using argon or the like without using P-type. It may be a high resistance layer for relaxing the electric field.
[0084]
In general, in the present invention, the same effects as described above can be obtained by providing a gate insulating film and a gate electrode with the same configuration as that of this embodiment.
[0085]
As exemplified in the present embodiment, a silicon carbide semiconductor is characterized in that a gate electrode is formed at a hetero junction between the base region and the collector region (or a high-concentration semiconductor region) via a gate insulating film. If the device is configured, the thickness of the energy barrier formed at the hetero junction can be reduced by applying a voltage to the gate electrode. As a result, carriers easily pass through the energy barrier, and control of the main current by the base current becomes easy (the current amplification factor h _FE Is higher).
[0086]
Further, in a silicon carbide semiconductor device, a second conductivity type electric field relaxation region is formed in a predetermined region of the collector region surface layer below the trench in contact with the gate insulating film. When a reverse voltage is applied to the element, the depletion layer expands from the electric field relaxation region of the second conductivity type to the collector region side, so that the electric field applied to the gate insulating film at the bottom of the groove can be reduced. As a result, breakdown of the gate insulating film before avalanche breakdown occurs inside the silicon carbide semiconductor device can be prevented, and a desired element withstand voltage can be obtained.
[0087]
Further, in the silicon carbide semiconductor device having the gate electrode, if the base electrode is connected to the gate electrode, four power supply terminals are required before the connection, whereas after the connection, the power supply terminal becomes three. That is, the present silicon carbide semiconductor device can be used as a three-terminal element.
[0088]
In each of the above embodiments, polycrystalline silicon is used as a semiconductor material for forming a heterojunction with a silicon carbide semiconductor, but single crystal silicon or amorphous silicon may be used instead of this polycrystalline silicon. These materials, including polycrystalline silicon, have a smaller band gap than silicon carbide, so that the effects of the invention can be easily realized in the silicon carbide semiconductor device according to the present invention. In addition, when single-crystal silicon, amorphous silicon, or polycrystalline silicon is used, deposition on a silicon carbide substrate, and oxidation, patterning, selective etching, and selective conductivity control of the deposited film have been accumulated to date. This can be easily achieved by utilizing the advanced semiconductor technology.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.
FIG. 2 is a sectional view showing a second embodiment of the present invention.
FIG. 3 is a sectional view showing a third embodiment of the present invention.
FIG. 4 is a sectional view showing a fourth embodiment of the present invention.
FIG. 5 is a sectional view showing a fifth embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
FIG. 9 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
FIG. 10 is a sectional view showing a manufacturing process of the first embodiment of the present invention.
FIG. 11 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.
FIG. 12 is a sectional view showing a manufacturing step (part) of a fifth embodiment of the present invention.
FIG. 13 is a sectional view showing a manufacturing step (part) of the fifth embodiment of the present invention.
FIG. 14 is a sectional view showing a manufacturing step (part) of the fifth embodiment of the present invention.
FIG. 15 ⁺ Type Si / P ⁻ It is an energy band figure of type Si / 4H-SiC.
FIG. 16 ⁺ Type Si / P ⁻ FIG. 4 is an energy band diagram of a type Si / 4H—SiC (when a collector voltage is applied and a base voltage is off).
FIG. 17 ⁺ Type Si / P ⁻ FIG. 4 is an energy band diagram of a type Si / 4H—SiC (when a collector voltage is applied and a base voltage is on).
FIG. 18 ⁺ Type Si / P ⁻ FIG. 4 is an energy band diagram of a type Si / 4H—SiC (when a collector voltage is applied and a base voltage is on). In the figure, the solid line at the right end and steep slope is N ⁺ The case where there is the type SiC region 100 or the case where the gate voltage is on with the gate electrode 160 is shown.
[Explanation of symbols]
10 ... N ⁺ Type SiC substrate, 20 ... N ⁻ Type SiC epitaxial region, 30 ... P ⁻ Type polycrystalline silicon base region, 40 ... N ⁺ Type polycrystalline silicon emitter region, 50 ... P ⁺ Type polycrystalline silicon contact region, 60 ... interlayer insulating film, 70 ... emitter electrode, 80 ... base electrode, 90 ... collector electrode, 100 ... N ⁺ -Type SiC region, 110: P-type SiC electric field relaxation region, 120: insulating film, 130: P ⁻ Type SiC base region, 140 ... N ⁺ SiC emitter region, 150 ... P ⁺ Type SiC contact region, 160 gate electrode, 170 gate insulating film, 180 P-type SiC electric field relaxation region, 190, 191, 192 mask material, 200, 201 groove, 210 hetero heterojunction barrier.

Claims (8)

A collector region of the first conductivity type, a base region of the second conductivity type formed on the collector region, an emitter region of the first conductivity type formed on the base region, and a collector connected to the collector region An electrode, a base electrode connected to the base region, and an emitter electrode connected to the emitter region;
The collector region is made of a silicon carbide semiconductor;
A silicon carbide semiconductor device, wherein the base region is made of a semiconductor material forming a heterojunction with the silicon carbide semiconductor. A first conductivity type high impurity concentration semiconductor region having an impurity concentration higher than at least the collector region is formed in a part of the collector region surface layer below the base region, and the high impurity concentration semiconductor region is formed in the base region. 2. The silicon carbide semiconductor device according to claim 1, wherein said silicon carbide semiconductor device is in contact with said silicon carbide semiconductor device. The silicon carbide semiconductor device according to claim 1, wherein a second conductivity type electric field relaxation region is formed in a part of the collector region surface layer below the base region. 3. The silicon carbide semiconductor device according to claim 1, wherein an insulating electric field relaxation layer is formed on a part of the collector region surface layer below the base region. 4. A groove having a predetermined depth is formed in a predetermined region of a surface portion of the collector region, at least a part of the groove is in contact with the base region, and a gate electrode is formed in the groove via a gate insulating film. The silicon carbide semiconductor device according to claim 1, 2, 3, or 4, wherein: 6. The silicon carbide semiconductor device according to claim 5, wherein a second conductivity type electric field relaxation region is formed in contact with said gate insulating film in a predetermined region of said collector region surface layer below said trench. 7. The silicon carbide semiconductor device according to claim 5, wherein said gate electrode is connected to said base electrode. 8. The silicon carbide semiconductor device according to claim 1, wherein a semiconductor material forming a heterojunction with said silicon carbide semiconductor is at least one of single crystal silicon, amorphous silicon, and polycrystalline silicon. .

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