WO2010024239A1 - Junction semiconductor device and method for manufacturing same - Google Patents

Junction semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2010024239A1
WO2010024239A1 PCT/JP2009/064769 JP2009064769W WO2010024239A1 WO 2010024239 A1 WO2010024239 A1 WO 2010024239A1 JP 2009064769 W JP2009064769 W JP 2009064769W WO 2010024239 A1 WO2010024239 A1 WO 2010024239A1
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Prior art keywords
region
base
resistance layer
layer
high resistance
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PCT/JP2009/064769
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French (fr)
Japanese (ja)
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賢一 野中
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本田技研工業株式会社
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Priority to JP2010526711A priority Critical patent/JP5470254B2/en
Publication of WO2010024239A1 publication Critical patent/WO2010024239A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a junction type semiconductor device and a manufacturing method thereof, and more particularly to a junction type semiconductor device suitable for suppressing recombination of electrons and holes in the region of a base layer and increasing a current gain. About.
  • SiC Silicon carbide
  • the junction type SiC power device includes an electrostatic induction transistor (Static Induction Transistor, hereinafter referred to as “SIT”), a junction field effect transistor (Junction Field Effect Transistor, hereinafter referred to as “JFET”), or bipolar.
  • SIT Static Induction Transistor
  • JFET Junction Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • SIT, JFET, and BJT are collectively referred to as “junction transistors”.
  • Patent Document 1 As an example of a conventional SIT, for example, one having a structure disclosed in Patent Document 1 is known.
  • the SIT disclosed in Patent Document 1 has an n + type first high resistance layer, a p type channel doped layer, an n ⁇ type on the n + type 4H—SiC (0001) plane substrate serving as a drain region from below.
  • the second high resistance layer and the n + type source region are stacked in this order.
  • the source region thereof, n + -type source region from the top surface in the laminated structure, and the n - by being etched in a predetermined planar pattern shape to the middle of the mold the second high-resistance layer is separated form Is done.
  • the SIT has a plurality of source regions separated on the upper surface based on a predetermined pattern shape. In the region between the plurality of separated source regions, an Al ion implantation process is subsequently performed to form a p-type gate region. Accordingly, each of the plurality of separated source regions is surrounded by a p-type gate region when viewed in a planar shape of the SIT.
  • the SIT disclosed in Patent Document 1 has a structure in which the SiC surface in the SIT is covered with a surface recombination suppressing semiconductor layer between the source region and the gate region.
  • This surface recombination suppressing semiconductor layer has a function of suppressing recombination of electrons flowing out from the source region (n + type source region and n ⁇ type second high resistance layer) and holes flowing out from the gate region. Yes. As a result, recombination of electrons from the source region and holes from the gate region is suppressed, and an improvement in the current amplification factor of the junction type semiconductor layer device is achieved.
  • BJT is stacked on the low resistance n + -type 4H-SiC (0001) plane 8 degree off substrate in the order of n ⁇ -type high resistance region, p-type base region, and n + -type emitter region from the bottom. It is formed.
  • the emitter region is composed of a number of elongated regions. Electrodes for establishing electrical connection to the outside are formed in the emitter region, base region, and collector region.
  • FIG. 10 shows a cross-sectional structure diagram of the BJT disclosed in Non-Patent Document 1.
  • the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region.
  • the base contact region 505 of the p-type low resistance region is formed.
  • a collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503, and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.
  • a control electrode portion called a gate or base (base contact region) is formed by a pn junction.
  • main current Id the current flowing between main electrodes
  • control current Ig the ratio of both currents (Id / Ig) is called “current amplification factor”.
  • recombination of holes flowing from the control electrode carrier of control current Ig
  • electrons flowing between the main electrodes carrier of main current Id
  • the value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.
  • the SiC surface is known as a site where recombination is likely to occur.
  • various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1.
  • Patent Document 1 in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface.
  • a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered.
  • the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration.
  • a surface recombination suppressing semiconductor layer By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.
  • junction transistor many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface.
  • the recombination probability of electrons and holes is high even in the channel doped layer near the p-type gate region of SIT.
  • the above-mentioned problem relating to SIT is a problem that also occurs in the BJT having a base region corresponding to the channel dope layer.
  • the object of the present invention is to reduce the recombination probability of electrons and holes in the vicinity of the channel doped layer and the base region around the p-type gate region of the SIT and the p-type base contact region of the BJT.
  • An object of the present invention is to provide a junction type semiconductor device capable of suppressing recombination of a main current flowing through a control electrode and a control current flowing through a control electrode and improving a current gain, and a method for manufacturing the same.
  • a junction type semiconductor device includes a first main electrode region (a first region corresponding to one main electrode), which is a substrate made of a silicon carbide semiconductor crystal, and one surface of the substrate.
  • a second main electrode region (second region corresponding to the other main electrode) formed on the side, a high resistance layer formed between the first and second main electrode regions, and a second Cover the control electrode region formed around the main electrode region, the intermediate layer formed in the high resistance layer and in contact with the control electrode region, and the portion in contact with the control electrode region in the intermediate layer And a recombination suppression region formed on the substrate.
  • the first main electrode region is a drain region or a collector region
  • the second main electrode region is a source region or an emitter region
  • the control electrode according to SIT or BJT is a gate region or a base contact region.
  • the intermediate layer means a layer or region existing between the first and second main electrode regions.
  • the intermediate layer is a base region in the case of BJT, and a channel dope layer in the case of SIT. Since the recombination suppression region is provided so as to cover the portion in contact with the adjacent region for the control electrode in the intermediate layer or the adjacent portion, in the conventional structure, in the region where the density of holes and electrons is high and recombination occurs frequently.
  • a junction type semiconductor device includes a first main electrode region which is a substrate made of a silicon carbide semiconductor crystal, and a second main electrode formed on one surface side of the substrate. Formed in the high resistance layer, a high resistance layer formed between the first and second main electrode regions, a control electrode region formed around the second main electrode region, A first intermediate layer that is in contact with the control electrode region and has a low resistance, and is formed in the high resistance layer, is connected to the first intermediate layer, and is between the first and second main electrode regions. And a second intermediate layer disposed on the substrate.
  • the first main electrode region is a drain region or a collector region
  • the second main electrode region is a source region or an emitter region according to SIT or BJT.
  • the electrode region is a gate region or a base contact region.
  • the intermediate layer is a base region in the case of BJT and a channel dope layer in the case of SIT.
  • a method for manufacturing a junction type semiconductor device comprising: a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region; A second step of forming an intermediate layer in the layer, a third step of forming a low-resistance layer serving as a second main electrode region on the high-resistance layer, and control on the surface side of the high-resistance layer A fourth step of forming a recombination suppression region by ion implantation so as to be in contact with the upper and lower surfaces of the intermediate layer in the vicinity of the predetermined region where the electrode region is to be formed; and a predetermined region on the surface side of the high resistance layer. And a fifth step of forming the control electrode region in contact with the intermediate layer by ion implantation.
  • a method of manufacturing a junction type semiconductor device including a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystal and serving as a first main electrode region; A second step of forming an intermediate layer therein, a third step of forming a low-resistance layer serving as a second main electrode region on the high-resistance layer, and a control electrode on the surface side of the high-resistance layer A fourth step of reducing the resistance of a part of the intermediate layer by ion implantation in the vicinity of a predetermined region where the formation of the control region is planned, and a control electrode region by ion implantation in the predetermined region on the surface side of the high resistance layer And a fifth step of forming so as to contact the low resistance portion of the intermediate layer.
  • junction type semiconductor device has the following effects.
  • a recombination suppression region is provided in the intermediate layer that contacts the control electrode region so as to cover a portion that contacts the control electrode region. Electrons can be prevented from flowing into the intermediate layer, and recombination in the intermediate layer can be suppressed, whereby the current gain can be increased.
  • the first and second intermediate layers disposed between the first and second main electrode regions, and in particular, the first and second layers which are in contact with or adjacent to the control electrode region Since the resistance of the intermediate layer is further lowered, the hole current flowing from the control electrode hardly flows in the vicinity of the SiC surface, and the current amplification factor can be increased.
  • the junction type semiconductor device according to the present invention can be manufactured by a simple manufacturing procedure.
  • 1 is a partial longitudinal sectional view of a junction type semiconductor device (BJT) according to a first embodiment of the present invention.
  • 1 is a plan view of a part of a junction type semiconductor device (BJT) according to a first embodiment. It is a fragmentary longitudinal cross-section explaining the problem of operation
  • 3 is a flowchart showing a method for manufacturing a junction type semiconductor device according to the first embodiment. It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the junction type semiconductor device which concerns on 1st Embodiment.
  • junction type semiconductor device BJT
  • 2nd Example of this invention It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 2nd Example of this invention. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 3rd Example of this invention. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 4th Example of this invention. It is a fragmentary longitudinal cross-section explaining the structure of the conventional junction type semiconductor device (BJT).
  • FIG. 1 shows a unit structure of a junction type semiconductor device according to the first embodiment
  • FIG. 2 is a plan view of the junction type semiconductor device.
  • FIG. 1 is a vertical cross-sectional view of a portion including at least one emitter electrode in a cross section taken along line AA in FIG.
  • This junction type semiconductor device shows an example of BJT (bipolar transistor).
  • BJT bipolar transistor
  • the SIT electrostatic induction transistor
  • the SIT electrostatic induction transistor
  • the BJT 10 includes, for example, five emitter electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device. These emitter electrodes 19 are surrounded by a base electrode 20.
  • the BJT 10 has a collector region 11 formed of an n-type low resistance layer (n + layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal.
  • An emitter region 12 made of an n-type low resistance layer (n + layer) formed on the upper side surface portion is provided.
  • a layer forming the collector region 11 is a substrate.
  • a base electrode 20 is formed around each of the plurality of emitter electrodes 19 so as to surround the emitter electrode 19 in the positional relationship of the plan view. This means that the periphery of the emitter region 12 located below the emitter electrode 19 is surrounded by the p-type base contact region 13 located below the base electrode 20.
  • the base contact region 13 is formed up to a predetermined depth position.
  • a first n-type high resistance layer (n ⁇ layer) 14 A, a p-type base region 15, and a second n-type high resistance layer are disposed between the upper emitter region 12 and the lower collector region 11.
  • (N ⁇ layer) 14B is laminated.
  • the base region 15 of the BJT 10 corresponds to the channel doped layer of SIT.
  • the base region 15 is formed so as to be in contact with and electrically connected to the base contact region 13.
  • n-type is “first conductivity type” and the “p-type” is “second conductivity type”.
  • the p + type base contact region 13 and the layered p type base region 15 that is in contact with or adjacent to the base contact region 13 are covered above and below the portion.
  • a recombination suppression region 16 is provided.
  • the recombination suppression region 16 covers the upper and lower surfaces of a predetermined portion of the base region 15 in layers.
  • the recombination suppression region 16 has the same conductivity type as that of the base region 15 and a p ⁇ semiconductor having the higher resistivity than the base region 15 or the same conductivity type as that of the first and second n-type high resistance layers 14A and 14B. rate the first and second n-type high-resistance layer 14A, higher n than 14B - a semiconductor.
  • the base contact region 13 is formed so as to be in contact with the upper surface of the base region 15 and further enter the base region 15 from the upper surface.
  • the collector electrode 18 is bonded to the lower surface of the collector region 11
  • the emitter electrode 19 is bonded to the upper surface of the emitter region 12
  • the base contact region 13 A base electrode 20 is joined to the upper surface.
  • the exposed surface between the emitter electrode 19 and the base electrode 20 is covered with a surface protective film 17 and is protected thereby.
  • an upper layer electrode 21 is provided above each of the emitter electrode 19 and the base electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.
  • the main current is an electron flow that flows from the emitter region 12 (or the emitter electrode 19) to the collector region 11 (or the collector electrode 18).
  • the emitter region 12 and the collector region 11 are main electrode regions for flowing a main current.
  • Energization (ON) and non-energization (OFF) of the main current are based on a base voltage applied to the base electrode 20, that is, a control signal applied between the base contact region 13 and the base region 15 and the emitter region 12. Be controlled.
  • the base contact region 13 and the base region 15 are control electrode regions.
  • the BJT 10 When a voltage of a certain level or higher is applied between the base and the emitter, the BJT 10 is turned on due to the main current flowing. In the ON state, the pn junction formed between the gate region 13 and the source region 12 is forward-biased, and a hole current that is a control current flows from the gate region 13 to the source region 12.
  • BJT 10 the characteristic structure of BJT 10 will be described while comparing the conventional BJT structure and the BJT structure according to the present embodiment.
  • FIG. 3 shows a BJT 10A having a conventional structure.
  • a hole current that is a control current flows into the emitter region 12 via the base electrode 20, the base contact region 13, and the base region 15.
  • an electron current 12 which is a main current flows from the emitter region 12 to the collector region. Since holes exist at a high density in the base region 15, the holes 32 flow from the emitter region 12 and the electrons 33 existing in the vicinity of the base region 15 are actively recombined.
  • the base region immediately below the base contact region 13 and the base region between the base contact region 13 and the emitter region 12 are regions in which recombination of electrons and holes is active even though the main current does not flow. This greatly affects the decrease in amplification factor.
  • the layered recombination suppression regions 16 are formed on the upper and lower surfaces of the base region 15 in contact with or adjacent to the base contact region 13. It is formed.
  • the recombination suppression region 16 is formed by, for example, ion implantation in a region portion located between two adjacent emitter regions 12.
  • the resistivity of the same conductivity type as the base region 15 is higher than the base region 15 p - semiconductor or the first and second n-type high-resistance layer 14A, the resistivity is the same conductivity type as 14B first and second n-type high-resistance layer 14A, higher n than 14B - is composed of a semiconductor.
  • the recombination suppression region 16 When the recombination suppression region 16 is made of a p ⁇ semiconductor, it is formed of the “p ⁇ ” region, and the hole density in the recombination suppression region 16 is suppressed to be lower than that of the base region 15. In addition, since a potential barrier against electrons due to a pn junction is formed between the recombination suppression region 16 and the n ⁇ high resistance layers 14A and 14B, the entry of electrons into the base region 15 is suppressed. This is a high electron barrier against the electrons 33. Therefore, the presence of the recombination suppression region 16 causes the holes 32 flowing from the base contact region 13 to the base region 15 to move to the right in FIG.
  • the base region 15 is not attracted to the vicinity of the base contact region. As shown in FIG. 4, the recombination of electrons and holes in the vicinity of the base region 15 is suppressed, and the current amplification factor of the BJT 10 can be improved.
  • the electron density in the recombination suppression region 16 is suppressed to be lower than that of the n ⁇ high resistance layers 14A and 14B, and the base region Since a potential barrier against holes due to a pn junction is formed between 15 and the recombination suppression region 16, penetration of holes from the base region 15 into the recombination suppression region 16 is suppressed. As a result, the current amplification factor of the BJT 10 can be improved.
  • the recombination suppression region 16 When forming the recombination suppression region 16, an ion implantation method of Al or the like is used as in the case of forming the base contact region 13. In this case, since the implantation depth is shallow and the implantation concentration is low, no new recombination level is generated when the recombination suppression region 16 is formed.
  • FIG. 5 is a flowchart showing each step of the manufacturing method.
  • 6 (a) to 6 (d) are longitudinal sectional views showing the structure manufactured in each step.
  • the manufacturing method of the BJT 10 includes the following processes (1) to (11) (steps S11 to S21). As shown in FIG. 5, the process is executed in the order from step S11 to step S21.
  • step S11 High resistance layer forming process
  • step S12 Base region formation process
  • step S13 High resistance layer formation process
  • step S14 Low resistance layer formation process
  • Emitter etching process step S15
  • step S16 Recombination suppression region formation process
  • step S17 Base contact region formation process
  • step S18 Ion implantation layer activation process
  • step S19 Surface protective film formation process
  • the structure shown in FIG. 6A is formed by performing the above steps S11 to S14.
  • step S11 a high resistance in which nitrogen having a thickness of 10 ⁇ m and a concentration of 1 ⁇ 10 16 cm ⁇ 3 is doped as an impurity on an n-type substrate 40 formed of SiC by an epitaxial growth method. Layer 41 is grown. “4H—SiC (0001) 8 ° off” is used for the substrate 40. The substrate 40 becomes the collector region 11 of the n-type low resistance layer described above.
  • step S12 0.1 to a concentration of 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 with aluminum (Al) as an impurity is formed on the n-type high resistance layer 41 by epitaxial growth. A 0.5 ⁇ m p-type base region 42 is grown.
  • step S13 nitrogen having a thickness of 0.1 to 0.4 ⁇ m and a concentration of 5 ⁇ 10 15 to 5 ⁇ 10 17 cm ⁇ 3 is then formed on the base region 42 by an epitaxial growth method.
  • An n-type high resistance layer 43 doped as an impurity is grown.
  • step S14 nitrogen is doped on the n-type high resistance layer 43 by an epitaxial growth method with a thickness of 0.5 to 2.0 ⁇ m and a concentration of 1 to 5 ⁇ 10 19 cm ⁇ 3.
  • An n-type low resistance layer 44 doped as follows is grown.
  • the low resistance layer 44 is a portion for forming the emitter region 12 described above.
  • a silicon oxide film 51 is deposited on the upper surface of the structure shown in FIG. 6A by CVD, photolithography is performed, and then silicon oxide is oxidized by RIE. The film 51 is etched. Thus, a mask is formed. Then, using this silicon oxide film 51, SiC etching is performed on the low resistance layer 44 by RIE, and the emitter region 12 is formed using the low resistance layer 44. Etching is performed in a gas atmosphere such as RIE in SF 6 for SiC etching. The resulting structure is shown in FIG. The etching depth is, for example, about 0.5 to 2.3 ⁇ m.
  • a mask 52 for forming the recombination suppression region 16 is formed.
  • a silicon oxide film is deposited by the CVD method, photolithography is performed, and then the silicon oxide film in a portion where the recombination suppression region 16 is to be formed is etched by RIE. Thereafter, ion implantation of aluminum (Al) as an impurity (ion species) is performed.
  • Al aluminum
  • the region to be implanted is a range between two adjacent emitter regions 12.
  • the amount of the impurity to be implanted is preferably the same as or around the n-type impurity concentration of the n ⁇ high resistance layers 14A and 14B from the viewpoint of making the recombination suppression region 16 an n ⁇ or p ⁇ type semiconductor. .
  • the ion implantation amount is in the range of 5 ⁇ 10 15 to 5 ⁇ 10 16 cm ⁇ 3. Is desirable.
  • the implantation energy is set to an appropriate value according to the thickness from the SiC surface to the base region 15.
  • the desired recombination suppression region 16 can be formed by using an implantation energy in the range of 100 to 500 keV. Since the injection amount is small and the injection energy is kept low, no new recombination level is generated in this process.
  • the mask 53 is formed so that the surface portion for forming the base contact region 13 is further exposed.
  • the mask 53 is formed by further depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, the base contact region 13 is formed by ion implantation.
  • the ion to be implanted is aluminum (Al), and the depth of implantation is, for example, 0.1 to 0.3 ⁇ m.
  • the ion implantation amount is 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
  • step S18 In the process of activating the ion implantation layer (step S18), after the ion implantation, the implanted ions are electrically activated in the semiconductor, and a heat treatment is performed to eliminate crystal defects generated by the ion implantation.
  • this activation heat treatment both the implanted ions in the base contact region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time.
  • heat treatment is performed at a high temperature of about 1700 to 1800 ° C. for about 10 minutes.
  • argon gas (Ar) is used as the atmospheric gas.
  • a process of forming a surface protective film (step S19) is performed.
  • sacrificial oxidation is performed to remove the oxide film after thermal oxidation in order to remove the surface layer generated in the ion implantation process and the activation process.
  • heat treatment (POA: Post-Oxidation-Anneal) is performed to reduce the impurity level at the interface of the SiC oxide film.
  • an emitter electrode 19, a base electrode 20, and a collector electrode 18 are formed on the surfaces of the emitter region 12 (low resistance layer 44), the base contact region 13, and the collector region 11 (substrate 40).
  • the emitter electrode 19 and the collector electrode 18 are made of nickel or titanium, and the base electrode 20 is made of a titanium / aluminum laminated film.
  • Each electrode 18, 19, 20 is formed by vapor deposition or sputtering.
  • dry etching, wet etching, lift-off method or the like is used.
  • heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion.
  • the heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.
  • step S21 the process of forming the upper layer electrode.
  • an upper layer wiring for taking out a plurality of separated emitter electrodes 12 to one electrode is formed.
  • the BJT 10 shown in FIGS. 1 and 2 is manufactured.
  • the recombination suppression region 16 shown in FIG. 1 is a p-type region (second conductivity type) has been described, but this is referred to as an n-type region (first conductivity type). You can also
  • the combination of the first and second conductivity types such as the collector region, the emitter region, the high resistance layer, the base region, the base contact region, and the recombination suppression region may be reversed. it can.
  • the combination will be specifically described as follows. This also applies to the following embodiments.
  • the first main electrode region is a collector region made of a low resistance layer of the first conductivity type
  • the second main electrode region is an emitter region made of a low resistance layer of the first conductivity type
  • the control electrode region is a second contact type base contact region (base region)
  • the recombination suppression region is a combination having the same second conductivity type as the base contact region or the same first conductivity type as the emitter region.
  • the first main electrode region is a collector region made of the second conductive type low resistance layer
  • the second main electrode region is made of the second conductive type low resistance layer
  • the control electrode region is a base contact region (base region) of the first conductivity type
  • the recombination suppression region is a combination having the same first conductivity type as the base contact region or the same second conductivity type as the emitter region.
  • the first main electrode region is a drain region made of a low resistance layer of the first conductivity type
  • the second main electrode region is a source region made of a low resistance layer of the first conductivity type
  • the control electrode region has a second conductivity type gate region
  • the recombination suppression region has the same second conductivity type as the gate region or the same first conductivity type as the source region.
  • the first main electrode region is a drain region made of the second conductivity type low resistance layer
  • the second main electrode region is made of the second conductivity type low resistance layer
  • the control electrode region is a combination of the first conductivity type gate region and the recombination suppression region having the same first conductivity type as the gate region or the same second conductivity type as the source region.
  • the channel dope layer corresponds to the base region of BJT
  • the gate region corresponds to the base contact region of BJT.
  • FIG. 7 is a view similar to FIG.
  • the junction type semiconductor device according to the second embodiment is also a BJT.
  • the BJT 100 according to the second embodiment is characterized in that the portion 15A of the base region 15 in the vicinity of the base contact region that is in contact with the base contact region 13 is formed by a p + region having a lower resistivity than other base regions.
  • the base contact region 13 is formed such that the bottom portion thereof is in contact with the low resistance portion 15 ⁇ / b> A of the base region 15. It is also desirable to make the thickness of the low resistance portion 15A larger than that of the other portions of the base region 15.
  • Other configurations are the same as those described in the first embodiment.
  • a hole current that is a control current flows from the base electrode 20 to the emitter region 12 via the base contact region 13, the low resistance portion 15 A, and the base region 15.
  • the control current is concentrated in the low resistance portion 15A as compared with the conventional structure, and the base contact region 13 and the emitter region where many recombination levels exist. It becomes difficult to flow on the SiC surface of the high resistance layer 14B between the twelve. Therefore, recombination on the SiC surface that occurs actively in the conventional structure is suppressed, and as a result, the current amplification factor is improved.
  • the manufacturing method of the BJT 100 according to the second embodiment is the same as the manufacturing method of the BJT 10 according to the first embodiment, except that the predetermined portion 15A of the base region 15 formed in the base region forming process (step S12) is a low resistance portion. It is comprised by providing after that the process for forming.
  • the injection amount and the injection energy may be designed in accordance with the formation of 15A.
  • the implantation energy is substantially the same as that of the first embodiment, and the implantation amount is set so that the impurity concentration of the low resistance portion 15A is higher than that of the base region 15.
  • the impurity concentration is about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the channel dope layer is divided into a channel dope layer portion (first channel dope layer) corresponding to the low resistance portion 15A, and other normal ones. It is comprised from a channel dope layer part (2nd channel dope layer). The first channel dope layer and the second channel dope layer are connected.
  • a third embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG.
  • the junction type semiconductor device of the third embodiment is BJT.
  • the BJT 200 of the third embodiment has a configuration in which the characteristic configuration of the first embodiment and the characteristic configuration of the second embodiment are combined. That is, the low resistance portion 15A is formed in a predetermined region of the base region 15, and the upper and lower surfaces of the low resistance portion 15A are covered with the recombination suppression region 16 described above.
  • Other configurations are the same as those described in the first or second embodiment.
  • the manufacturing method is not complicated, and when performing ion implantation in the recombination suppression region forming process of the first embodiment, a necessary implantation amount is set according to the depth and multistage implantation is performed. Good.
  • a fourth embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG.
  • the junction type semiconductor device of the fourth embodiment shows an example of BJT.
  • a BJT 300 shown in FIG. 9 is a modification of the BJT 10 of the first embodiment described above.
  • the recombination suppression region 16 is formed from the surface of the base contact region to the lower surface side of the base region 15.
  • Other configurations are the same as those described in the first embodiment.
  • the present invention can be used for manufacturing a high performance junction type semiconductor device.

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Abstract

Provided is a junction semiconductor device which achieves an improvement in current amplification factor by reducing the probability of recombination of electrons and holes in a neighboring region including a p-type base layer around a p-type base contact region of a BJT.  A BJT (10) is provided with a high-resistance layer (14A, 14B) formed between a collector region (11) that is a substrate produced from silicon carbide semiconductor crystal and an emitter region (12).  A base contact region (13) is formed around the emitter region.  A base region (15) that is in contact with the base contact region is formed in the high-resistance layer.  A recombination suppression region (16) is formed so as to cover a portion that is in contact with the base contact region of the base region.

Description

接合型半導体装置およびその製造方法Junction type semiconductor device and manufacturing method thereof
　本発明は接合型半導体装置およびその製造方法に関し、特に、ベース層の領域での電子と正孔との再結合を抑制し、電流増幅率を高めるのに好適な接合型半導体装置およびその製造方法に関する。 The present invention relates to a junction type semiconductor device and a manufacturing method thereof, and more particularly to a junction type semiconductor device suitable for suppressing recombination of electrons and holes in the region of a base layer and increasing a current gain. About.
　炭化珪素（シリコン・カーバイド（Silicon Carbide）、以下では「ＳｉＣ」と記す。）は、広く半導体装置に応用されているシリコンと比べて、バンドギャップエネルギが大きいという特性を有する。そのためＳｉＣを利用した半導体装置は、高電圧、大電力、高温動作の条件に適しており、パワーデバイスなどへの適用が期待されている。現在、研究開発されているＳｉＣパワーデバイスの構造は、主に、「ＭＯＳ型」と「接合型」の２つの型に分類されている。 Silicon carbide (Silicon Carbide, hereinafter referred to as “SiC”) has a characteristic that it has a larger band gap energy than silicon that is widely applied to semiconductor devices. Therefore, a semiconductor device using SiC is suitable for high voltage, high power, and high temperature operation conditions, and is expected to be applied to power devices and the like. The structures of SiC power devices currently being researched and developed are mainly classified into two types, “MOS type” and “junction type”.
　ここでは接合型ＳｉＣパワーデバイスの性能向上という観点で説明する。接合型ＳｉＣパワーデバイスには、静電誘導トランジスタ（Static Induction Transistor、以下では「ＳＩＴ」と記す。）や接合型電界効果トランジスタ（Junction Field Effect Transistor、以下では「ＪＦＥＴ」と記す。)、あるいはバイポーラトランジスタ（Bipolar Junction Transistor、以下では「ＢＪＴ」と記す。）などがある。なお以下において、ＳＩＴ、ＪＦＥＴ、ＢＪＴは、総称して、「接合型トランジスタ」と呼ぶこととする。 Here, it demonstrates from a viewpoint of the performance improvement of a junction type SiC power device. The junction type SiC power device includes an electrostatic induction transistor (Static Induction Transistor, hereinafter referred to as “SIT”), a junction field effect transistor (Junction Field Effect Transistor, hereinafter referred to as “JFET”), or bipolar. A transistor (Bipolar Junction Transistor, hereinafter referred to as “BJT”). In the following, SIT, JFET, and BJT are collectively referred to as “junction transistors”.
　従来のＳＩＴの例としては、例えば特許文献１に開示された構造を有するものが知られている。特許文献１に開示されたＳＩＴは、ドレイン領域となるｎ＋型４Ｈ－ＳｉＣ（０００１）面基板上に、下側から、ｎ型第１の高抵抗層、ｐ型チャネルドープ層、ｎ－型第２の高抵抗層、ｎ＋型ソース領域の順序で積層された構造をしている。当該ＳＩＴで、そのソース領域は、当該積層構造において上面からｎ＋型ソース領域、およびｎ－型第２の高抵抗層の途中まで所定の平面パターン形状でエッチングされることにより、分離されて形成される。ＳＩＴは、その上面に、所定のパターン形状に基づいて分離された複数のソース領域を有している。分離された複数のソース領域の間の領域には、その後にＡｌイオン注入の工程が実行され、ｐ型ゲート領域が形成される。従って、分離された複数のソース領域の各々は、ＳＩＴの平面形状で見てみると、その周囲をｐ型ゲート領域で囲まれている。特許文献１に開示されているＳＩＴは、ソース領域とゲート領域との間において、当該ＳＩＴにおけるＳｉＣ表面を表面再結合抑制半導体層で覆うようにした構造を有している。この表面再結合抑制半導体層は、ソース領域（ｎ＋型ソース領域とｎ－型第２の高抵抗層）から流れ出る電子とゲート領域から流れ出る正孔との再結合を抑制する機能を有している。これにより、ソース領域からの電子とゲート領域からの正孔の再結合を抑え、接合型半導体層装置の電流増幅率の向上を達成している。 As an example of a conventional SIT, for example, one having a structure disclosed in Patent Document 1 is known. The SIT disclosed in Patent Document 1 has an n + type first high resistance layer, a p type channel doped layer, an n − type on the n + type 4H—SiC (0001) plane substrate serving as a drain region from below. The second high resistance layer and the n + type source region are stacked in this order. In the SIT, the source region thereof, n + -type source region from the top surface in the laminated structure, and the n - by being etched in a predetermined planar pattern shape to the middle of the mold the second high-resistance layer is separated form Is done. The SIT has a plurality of source regions separated on the upper surface based on a predetermined pattern shape. In the region between the plurality of separated source regions, an Al ion implantation process is subsequently performed to form a p-type gate region. Accordingly, each of the plurality of separated source regions is surrounded by a p-type gate region when viewed in a planar shape of the SIT. The SIT disclosed in Patent Document 1 has a structure in which the SiC surface in the SIT is covered with a surface recombination suppressing semiconductor layer between the source region and the gate region. This surface recombination suppressing semiconductor layer has a function of suppressing recombination of electrons flowing out from the source region (n + type source region and n − type second high resistance layer) and holes flowing out from the gate region. Yes. As a result, recombination of electrons from the source region and holes from the gate region is suppressed, and an improvement in the current amplification factor of the junction type semiconductor layer device is achieved.
　また、従来のＢＪＴの例として例えば非特許文献１あるいは特許文献２に記載された構造を有するものがある。ＢＪＴは、低抵抗のｎ＋型４Ｈ－ＳｉＣ（０００１）面８度オフ基板上に、下側から、ｎ－型高抵抗領域、ｐ型ベース領域、ｎ＋型エミッタ領域の順序に積層されて形成される。エミッタ領域は、多数の細長い形状の領域からなっている。エミッタ領域、ベース領域、コレクタ領域には外部に電気的接続を取るための電極が形成されている。 Further, as an example of a conventional BJT, there is one having a structure described in Non-Patent Document 1 or Patent Document 2, for example. BJT is stacked on the low resistance n + -type 4H-SiC (0001) plane 8 degree off substrate in the order of n − -type high resistance region, p-type base region, and n + -type emitter region from the bottom. It is formed. The emitter region is composed of a number of elongated regions. Electrodes for establishing electrical connection to the outside are formed in the emitter region, base region, and collector region.
　図１０に非特許文献１に開示されたＢＪＴの断面構造図を示す。図１０に示すように、ＢＪＴ５００は、ｎ型低抵抗層であるコレクタ領域５０１、ｎ型高抵抗領域５０２、ｐ型領域のベース領域５０３、ｎ型低抵抗のエミッタ領域５０４、エミッタ領域を囲むように形成されたｐ型低抵抗領域のベースコンタクト領域５０５を備えている。コレクタ領域５０１とベース領域５０３とエミッタ領域のそれぞれの外部には、電気的接続をとるためのコレクタ電極５０６、ベース電極５０７、エミッタ電極５０８が接合されている。さらにＢＪＴ５００の電極以外の露出表面の全体は表面保護膜５０９で覆われている。 FIG. 10 shows a cross-sectional structure diagram of the BJT disclosed in Non-Patent Document 1. As shown in FIG. 10, the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region. The base contact region 505 of the p-type low resistance region is formed. A collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503, and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.
特開２００６－２６９６８１号公報JP 2006-269682 A 特開２００６－３５１６２１号公報JP 2006-351621 A
　ＳＩＴやＢＪＴ等の接合型トランジスタでは、ゲートあるいはベース（ベースコンタクト領域）と呼ばれる制御電極の部分がｐｎ接合で形成されている。ソースとドレインの間、あるいはコレクタとエミッタの間のような主電極間に電流を流すため、当該制御電極に電流を流す必要がある。主電極間に流れる電流を「主電流Ｉｄ」、制御電極に流れる電流を「制御電流Ｉｇ」とするとき、両電流の比（Ｉｄ／Ｉｇ）は「電流増幅率」と呼ばれる。接合型トランジスタの開発では、電流増幅率の値を大きくすることが重要な課題となっている。 In a junction transistor such as SIT or BJT, a control electrode portion called a gate or base (base contact region) is formed by a pn junction. In order to pass a current between main electrodes such as between a source and a drain or between a collector and an emitter, it is necessary to pass a current through the control electrode. When the current flowing between the main electrodes is “main current Id” and the current flowing through the control electrode is “control current Ig”, the ratio of both currents (Id / Ig) is called “current amplification factor”. In the development of junction transistors, increasing the value of the current amplification factor is an important issue.
　上記電流増幅率を低下させる要因としては、制御電極から流れ込む正孔（制御電流Ｉｇのキャリア）と主電極間を流れる電子（主電流Ｉｄのキャリア）との再結合を挙げることができる。再結合電流の値は、電子密度、正孔密度、再結合準位密度に依存し、それぞれの密度が高いほど再結合電流も大きくなる。 As a factor for reducing the current amplification factor, recombination of holes flowing from the control electrode (carrier of control current Ig) and electrons flowing between the main electrodes (carrier of main current Id) can be mentioned. The value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.
　再結合が発生しやすい部位としてはＳｉＣ表面が知られている。ＳｉＣ表面の再結合準位の密度を低減するために、ＳｉＣ表面を酸化して保護膜を形成するプロセスで各種の工夫をなすことが提案されている。この点は特許文献１にも記載されている。さらに特許文献１では、再結合確率を下げるために、ＳｉＣ表面に、濃度の低いｐ型領域からなる表面再結合抑制半導体層を設けるようにしている。このような表面再結合抑制半導体層を形成すると、ＳｉＣ表面に電子に対する電位障壁が形成されるので、ＳｉＣ表面での電子密度を下げることができる。さらに、濃度の低いｐ型領域でＳｉＣ表面に高抵抗層を形成することにより、正孔の密度も低く抑えることができる。かかる表面再結合抑制半導体層を形成することにより、接合型トランジスタのＳｉＣ表面に再結合準位が存在したとしても、再結合確率を低減することができ、接合型トランジスタの電流増幅率を大きくすることができる。 The SiC surface is known as a site where recombination is likely to occur. In order to reduce the density of recombination levels on the SiC surface, various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1. Further, in Patent Document 1, in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface. When such a surface recombination-inhibiting semiconductor layer is formed, a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered. Furthermore, the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration. By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.
　以上のように接合型トランジスタにおいて、ＳｉＣ表面での再結合を抑制して電流増幅率を大きくする試みが多くなされている。しかしながら、ＳＩＴのｐ型ゲート領域の近くのチャネルドープ層でも電子と正孔の再結合確率が高いことが知られている。ところが、従来の接合型トランジスタの開発では、当該チャネルドープ層の近傍領域での再結合を抑制する試みは見当たらない。 As described above, in the junction transistor, many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface. However, it is known that the recombination probability of electrons and holes is high even in the channel doped layer near the p-type gate region of SIT. However, in the development of a conventional junction transistor, there is no attempt to suppress recombination in the vicinity of the channel dope layer.
　ＳＩＴに関する上記の問題は、上記チャネルドープ層に対応するベース領域を備えたＢＪＴでも同様に生じる問題である。 The above-mentioned problem relating to SIT is a problem that also occurs in the BJT having a base region corresponding to the channel dope layer.
　本発明の目的は、ＳＩＴのｐ型ゲート領域、ＢＪＴのｐ型ベースコンタクト領域の周囲のチャネルドープ層やベース領域等の近傍領域での電子と正孔の再結合確率を低減し、主電極間に流れる主電流と制御電極に流れる制御電流の再結合を抑制し、電流増幅率を向上することができる接合型半導体装置およびその製造方法を提供することにある。 The object of the present invention is to reduce the recombination probability of electrons and holes in the vicinity of the channel doped layer and the base region around the p-type gate region of the SIT and the p-type base contact region of the BJT. An object of the present invention is to provide a junction type semiconductor device capable of suppressing recombination of a main current flowing through a control electrode and a control current flowing through a control electrode and improving a current gain, and a method for manufacturing the same.
　本発明の一面による接合型半導体装置は、炭化珪素の半導体結晶で作られた基板である第１の主電極用領域（一方の主電極に対応する第１領域）と、基板の１つの面の側に形成された第２の主電極用領域（他方の主電極に対応する第２領域）と、第１および第２の主電極用領域の間に形成された高抵抗層と、第２の主電極用領域の周囲に形成された制御電極用領域と、高抵抗層内に形成され、制御電極用領域に接触する中間層と、当該中間層における制御電極用領域に接触する部分を覆うように形成された再結合抑制領域とを有するように構成される。 A junction type semiconductor device according to one aspect of the present invention includes a first main electrode region (a first region corresponding to one main electrode), which is a substrate made of a silicon carbide semiconductor crystal, and one surface of the substrate. A second main electrode region (second region corresponding to the other main electrode) formed on the side, a high resistance layer formed between the first and second main electrode regions, and a second Cover the control electrode region formed around the main electrode region, the intermediate layer formed in the high resistance layer and in contact with the control electrode region, and the portion in contact with the control electrode region in the intermediate layer And a recombination suppression region formed on the substrate.
　上記一面による接合型半導体装置において、ＳＩＴまたはＢＪＴに応じて、第１の主電極用領域はドレイン領域またはコレクタ領域であり、第２の主電極用領域はソース領域またはエミッタ領域であり、制御電極用領域はゲート領域またはベースコンタクト領域である。また上記の中間層は、第１および第２の主電極用領域の間に存する層または領域という意味である。当該中間層は、ＢＪＴの場合にはベース領域であり、ＳＩＴの場合にはチャネルドープ層である。中間層における制御電極用領域に接触する部分あるいは隣接する部分を覆うように再結合抑制領域を設けるようにしたため、従来構造であれば正孔と電子の密度が高く再結合がさかんに生じる領域に、電子等に対する電位障壁が設けられることにより、ソース領域等から中間層へ流れ込む電子等を、電位障壁である再結合抑制領域によって遠ざけることができる。これにより、この領域の電子の密度を低減でき、電流増幅率を高めることができる。 In the junction type semiconductor device according to the one aspect, the first main electrode region is a drain region or a collector region, the second main electrode region is a source region or an emitter region, and the control electrode according to SIT or BJT. The use region is a gate region or a base contact region. The intermediate layer means a layer or region existing between the first and second main electrode regions. The intermediate layer is a base region in the case of BJT, and a channel dope layer in the case of SIT. Since the recombination suppression region is provided so as to cover the portion in contact with the adjacent region for the control electrode in the intermediate layer or the adjacent portion, in the conventional structure, in the region where the density of holes and electrons is high and recombination occurs frequently. By providing a potential barrier against electrons or the like, electrons or the like flowing from the source region or the like to the intermediate layer can be kept away by the recombination suppression region that is a potential barrier. Thereby, the density of electrons in this region can be reduced, and the current amplification factor can be increased.
　本発明の他の面による接合型半導体装置は、炭化珪素の半導体結晶で作られた基板である第１の主電極用領域と、基板の１つの面の側に形成された第２の主電極用領域と、第１および第２の主電極用領域の間に形成された高抵抗層と、第２の主電極用領域の周囲に形成された制御電極用領域と、高抵抗層内に形成され、制御電極用領域に接触し、かつ低抵抗である第１中間層と、高抵抗層内に形成され、第１中間層に連接し、かつ第１および第２の主電極用領域の間に配置される第２中間層とを有するように構成される。 A junction type semiconductor device according to another aspect of the present invention includes a first main electrode region which is a substrate made of a silicon carbide semiconductor crystal, and a second main electrode formed on one surface side of the substrate. Formed in the high resistance layer, a high resistance layer formed between the first and second main electrode regions, a control electrode region formed around the second main electrode region, A first intermediate layer that is in contact with the control electrode region and has a low resistance, and is formed in the high resistance layer, is connected to the first intermediate layer, and is between the first and second main electrode regions. And a second intermediate layer disposed on the substrate.
　他の面による接合型半導体装置において、ＳＩＴまたはＢＪＴに応じて、第１の主電極用領域はドレイン領域またはコレクタ領域であり、第２の主電極用領域はソース領域またはエミッタ領域であり、制御電極用領域はゲート領域またはベースコンタクト領域である。また中間層については、前述した通り、ＢＪＴの場合にはベース領域であり、ＳＩＴの場合にはチャネルドープ層である。制御電極用領域に接触または隣接する第１中間層の抵抗を下げることによって、制御電極から流れる正孔電流が第１中間層を流れ易くなりＳｉＣ表面付近を流れにくくなるために、再結合準位が多く存在するＳｉＣ表面での再結合を抑制することができ電流増幅率を高めることが可能となる。 In the junction type semiconductor device according to another aspect, the first main electrode region is a drain region or a collector region, and the second main electrode region is a source region or an emitter region according to SIT or BJT. The electrode region is a gate region or a base contact region. As described above, the intermediate layer is a base region in the case of BJT and a channel dope layer in the case of SIT. By reducing the resistance of the first intermediate layer that is in contact with or adjacent to the control electrode region, the hole current flowing from the control electrode is likely to flow through the first intermediate layer and is difficult to flow in the vicinity of the SiC surface. It is possible to suppress recombination on the SiC surface where a large amount of is present, and to increase the current amplification factor.
　本発明の一面による接合型半導体装置の製造方法は、炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、高抵抗層の中に中間層を形成する第２の工程と、高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第３の工程と、高抵抗層の表面側における制御電極用領域の形成を予定する所定領域の近傍で、中間層の上下の面に接するようにイオン注入により再結合抑制領域を形成する第４の工程と、高抵抗層の表面側における所定領域にイオン注入により制御電極用領域を中間層に接触するように形成する第５の工程とを含む。 According to one aspect of the present invention, there is provided a method for manufacturing a junction type semiconductor device, comprising: a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region; A second step of forming an intermediate layer in the layer, a third step of forming a low-resistance layer serving as a second main electrode region on the high-resistance layer, and control on the surface side of the high-resistance layer A fourth step of forming a recombination suppression region by ion implantation so as to be in contact with the upper and lower surfaces of the intermediate layer in the vicinity of the predetermined region where the electrode region is to be formed; and a predetermined region on the surface side of the high resistance layer. And a fifth step of forming the control electrode region in contact with the intermediate layer by ion implantation.
　他の面による接合型半導体装置の製造方法は、炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、高抵抗層の中に中間層を形成する第２の工程と、高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第３の工程と、高抵抗層の表面側における制御電極用領域の形成を予定する所定領域の近傍で、中間層の一部をイオン注入により低抵抗とする第４の工程と、高抵抗層の表面側における所定領域にイオン注入により制御電極用領域を中間層の低抵抗部分に接触するように形成する第５の工程とを含む。 According to another aspect of the present invention, there is provided a method of manufacturing a junction type semiconductor device including a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystal and serving as a first main electrode region; A second step of forming an intermediate layer therein, a third step of forming a low-resistance layer serving as a second main electrode region on the high-resistance layer, and a control electrode on the surface side of the high-resistance layer A fourth step of reducing the resistance of a part of the intermediate layer by ion implantation in the vicinity of a predetermined region where the formation of the control region is planned, and a control electrode region by ion implantation in the predetermined region on the surface side of the high resistance layer And a fifth step of forming so as to contact the low resistance portion of the intermediate layer.
　本発明に係る接合型半導体装置によれば次の効果を奏する。
　第１に、ＢＪＴやＳＩＴ等の接合型半導体装置において、制御電極用領域に接触する中間層において当該制御電極用領域に接触する部分を覆う再結合抑制領域を設けたため、エミッタ領域またはソース領域から中間層に電子が流れ込むことを防止し、中間層での再結合を抑制することができ、これにより電流増幅率を高めることができる。 The junction type semiconductor device according to the present invention has the following effects.
First, in a junction semiconductor device such as BJT or SIT, a recombination suppression region is provided in the intermediate layer that contacts the control electrode region so as to cover a portion that contacts the control electrode region. Electrons can be prevented from flowing into the intermediate layer, and recombination in the intermediate layer can be suppressed, whereby the current gain can be increased.
　第２に、上記接合型半導体装置において、第１および第２の主電極領域の間に配置される第１および第２の中間層であって、特に制御電極用領域に接触または隣接する第１中間層の抵抗をより下げるようにしたため、制御電極から流れる正孔電流がＳｉＣ表面付近を流れにくくなり、電流増幅率を高めることができる。 Second, in the junction type semiconductor device, the first and second intermediate layers disposed between the first and second main electrode regions, and in particular, the first and second layers which are in contact with or adjacent to the control electrode region. Since the resistance of the intermediate layer is further lowered, the hole current flowing from the control electrode hardly flows in the vicinity of the SiC surface, and the current amplification factor can be increased.
　また本発明に係る接合型半導体装置の製造方法によれば、簡単な製造手順で本発明に係る接合型半導体装置を製造することができる。 Further, according to the method for manufacturing a junction type semiconductor device according to the present invention, the junction type semiconductor device according to the present invention can be manufactured by a simple manufacturing procedure.
本発明の第１実施例による接合型半導体装置（ＢＪＴ）の部分縦断面図である。1 is a partial longitudinal sectional view of a junction type semiconductor device (BJT) according to a first embodiment of the present invention. 第１実施例による接合型半導体装置（ＢＪＴ）の一部の平面図である。1 is a plan view of a part of a junction type semiconductor device (BJT) according to a first embodiment. 従来の接合型半導体装置（ＢＪＴ）の動作の問題を説明する部分縦断面図である。It is a fragmentary longitudinal cross-section explaining the problem of operation | movement of the conventional junction type semiconductor device (BJT). 第１実施例による接合型半導体装置の動作を説明する部分縦断面図である。It is a fragmentary longitudinal cross-section explaining operation | movement of the junction type semiconductor device by 1st Example. 第１実施例による接合型半導体装置の製造方法を示したフローチャートである。3 is a flowchart showing a method for manufacturing a junction type semiconductor device according to the first embodiment. 第１実施形態に係る接合型半導体装置の製造方法の各プロセスに対応するデバイス構造を示す部分縦断面図である。It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the junction type semiconductor device which concerns on 1st Embodiment. 本発明の第２実施例による接合型半導体装置（ＢＪＴ）の部分縦断面図である。It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 2nd Example of this invention. 本発明の第３実施例による接合型半導体装置（ＢＪＴ）の部分縦断面図である。It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 3rd Example of this invention. 本発明の第４実施例による接合型半導体装置（ＢＪＴ）の部分縦断面図である。It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 4th Example of this invention. 従来の接合型半導体装置（ＢＪＴ）の構造を説明する部分縦断面図である。It is a fragmentary longitudinal cross-section explaining the structure of the conventional junction type semiconductor device (BJT).
　以下に、本発明の好適な幾つかの実施例を添付図面に基づいて説明する。 Hereinafter, some preferred embodiments of the present invention will be described with reference to the accompanying drawings.
　＜第１実施例＞
　図１～図６を参照して本発明に係る接合型半導体装置の第１実施例を説明する。図１は第１実施例による接合型半導体装置の単位構造を示し、図２は当該接合型半導体装置の平面図である。図１は、図２におけるＡ－Ａ線断面における少なくとも１つのエミッタ電極を含む部分の縦断面図を示している。この接合型半導体装置はＢＪＴ（バイポーラトランジスタ）の例を示している。なおＳＩＴ（静電誘導トランジスタ）であっても、ＳＩＴのチャネルドープ層がＢＪＴのベース領域に対応し、かつＳＩＴのゲート領域の深さがＢＪＴのベースコンタクト領域の深さよりも深くなる点が異なるが、その他の基本的な構造部分については実質的に同じ構造を有している。図１と図２は、ＢＪＴの単位となる素子部分の縦断面図および平面図を示す。 <First embodiment>
A first embodiment of a junction type semiconductor device according to the present invention will be described with reference to FIGS. FIG. 1 shows a unit structure of a junction type semiconductor device according to the first embodiment, and FIG. 2 is a plan view of the junction type semiconductor device. FIG. 1 is a vertical cross-sectional view of a portion including at least one emitter electrode in a cross section taken along line AA in FIG. This junction type semiconductor device shows an example of BJT (bipolar transistor). Note that the SIT (electrostatic induction transistor) is different in that the channel doped layer of the SIT corresponds to the base region of the BJT and the depth of the gate region of the SIT is deeper than the depth of the base contact region of the BJT. However, the other basic structural parts have substantially the same structure. 1 and 2 are a longitudinal sectional view and a plan view of an element portion as a unit of BJT.
　図２に示すように、ＢＪＴ１０は、そのデバイス上面の特定な単位領域に、並列に配列された例えば５本のエミッタ電極１９を備えている。これらのエミッタ電極１９は、ベース電極２０によって囲まれている。 As shown in FIG. 2, the BJT 10 includes, for example, five emitter electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device. These emitter electrodes 19 are surrounded by a base electrode 20.
　図１に示す縦断面構造において、ＢＪＴ１０は、ＳｉＣ（炭化珪素）結晶を有する下側面部分に形成されたｎ型の低抵抗層（ｎ＋層）からなるコレクタ領域１１と、当該ＳｉＣ結晶を有する上側面部分に形成されたｎ型の低抵抗層（ｎ＋層）からなるエミッタ領域１２を備えている。コレクタ領域１１を形成する層が基板となっている。 In the longitudinal cross-sectional structure shown in FIG. 1, the BJT 10 has a collector region 11 formed of an n-type low resistance layer (n + layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal. An emitter region 12 made of an n-type low resistance layer (n + layer) formed on the upper side surface portion is provided. A layer forming the collector region 11 is a substrate.
　図２に示すように、平面図の位置関係において、複数のエミッタ電極１９の各々の周囲には、当該エミッタ電極１９を囲むようにベース電極２０が形成されている。この意味は、エミッタ電極１９の下側に位置するエミッタ領域１２の周囲は、ベース電極２０の下側に位置するｐ型のベースコンタクト領域１３によって囲まれているということである。ベースコンタクト領域１３は所定の深さ位置まで形成されている。さらにＢＪＴ１０において、上側のエミッタ領域１２と下側のコレクタ領域１１の間には第１のｎ型高抵抗層（ｎ－層）１４Ａとｐ型のベース領域１５と第２のｎ型高抵抗層（ｎ－層）１４Ｂとが積層されて形成されている。ＢＪＴ１０のベース領域１５はＳＩＴのチャネルドープ層に対応している。ベース領域１５は、ベースコンタクト領域１３と接触して電気的に接続されるように形成されている。 As shown in FIG. 2, a base electrode 20 is formed around each of the plurality of emitter electrodes 19 so as to surround the emitter electrode 19 in the positional relationship of the plan view. This means that the periphery of the emitter region 12 located below the emitter electrode 19 is surrounded by the p-type base contact region 13 located below the base electrode 20. The base contact region 13 is formed up to a predetermined depth position. Further, in the BJT 10, a first n-type high resistance layer (n − layer) 14 A, a p-type base region 15, and a second n-type high resistance layer are disposed between the upper emitter region 12 and the lower collector region 11. (N − layer) 14B is laminated. The base region 15 of the BJT 10 corresponds to the channel doped layer of SIT. The base region 15 is formed so as to be in contact with and electrically connected to the base contact region 13.
　本実施例において、上記の「ｎ型」は「第１の導電型」であり、上記の「ｐ型」は「第２の導電型」であるとする。 In this embodiment, it is assumed that the “n-type” is “first conductivity type” and the “p-type” is “second conductivity type”.
　本実施例によるＢＪＴ１０では、さらに、ｐ＋型のベースコンタクト領域１３と、当該ベースコンタクト領域１３に接触するまたは隣接する層状のｐ型ベース領域１５の部分の上下に、当該部分を覆うようにした再結合抑制領域１６とを設けている。再結合抑制領域１６はベース領域１５の所定部分の上下面を層状に覆っている。上記の再結合抑制領域１６は、ベース領域１５と同じ導電型で抵抗率がベース領域１５よりも高いｐ－半導体か第１および第２のｎ型高抵抗層１４Ａ，１４Ｂと同じ導電型で抵抗率が第１および第２のｎ型高抵抗層１４Ａ，１４Ｂよりも高いｎ－半導体である。ベースコンタクト領域１３はベース領域１５の上面に接触し、さらに上面より当該ベース領域１５の内部に侵入するように形成されている。 In the BJT 10 according to the present embodiment, the p + type base contact region 13 and the layered p type base region 15 that is in contact with or adjacent to the base contact region 13 are covered above and below the portion. A recombination suppression region 16 is provided. The recombination suppression region 16 covers the upper and lower surfaces of a predetermined portion of the base region 15 in layers. The recombination suppression region 16 has the same conductivity type as that of the base region 15 and a p − semiconductor having the higher resistivity than the base region 15 or the same conductivity type as that of the first and second n-type high resistance layers 14A and 14B. rate the first and second n-type high-resistance layer 14A, higher n than 14B - a semiconductor. The base contact region 13 is formed so as to be in contact with the upper surface of the base region 15 and further enter the base region 15 from the upper surface.
　上記のＢＪＴ１０の構造において、図１に示すように、コレクタ領域１１の下側表面にはコレクタ電極１８が接合され、エミッタ領域１２の上側表面にはエミッタ電極１９が接合され、ベースコンタクト領域１３の上側表面にはベース電極２０が接合されている。ＢＪＴ１０の上面において、エミッタ電極１９とベース電極２０の間における露出表面は、表面保護膜１７によって覆われており、これにより保護されている。 In the structure of the BJT 10 described above, as shown in FIG. 1, the collector electrode 18 is bonded to the lower surface of the collector region 11, the emitter electrode 19 is bonded to the upper surface of the emitter region 12, and the base contact region 13 A base electrode 20 is joined to the upper surface. On the upper surface of the BJT 10, the exposed surface between the emitter electrode 19 and the base electrode 20 is covered with a surface protective film 17 and is protected thereby.
　図２に示すように、エミッタ電極１９およびベース電極２０の各々の上側には上層電極２１が設けられている。図１において、上層電極２１の図示は省略されている。 As shown in FIG. 2, an upper layer electrode 21 is provided above each of the emitter electrode 19 and the base electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.
　上記ＢＪＴ１０において、主電流は、エミッタ領域１２（またはエミッタ電極１９）からコレクタ領域１１（またはコレクタ電極１８）に流れる電子流である。エミッタ領域１２とコレクタ領域１１は主電流を流すための主電極用領域である。主電流の通電（オン）と非通電（オフ）は、ベース電極２０に印加されるベース電圧、すなわち、ベースコンタクト領域１３およびベース領域１５とエミッタ領域１２との間に加えられる制御信号に基づいて制御される。ベースコンタクト領域１３およびベース領域１５は制御電極用領域である。ベース・エミッタ間の印加電圧が０Ｖ以下であるときにはＢＪＴ１０は主電流が流れず、オフ状態になる。ベース・エミッタ間に一定以上の電圧が印加されると、ＢＪＴ１０は主電流が流れてオン状態に移行する。また、オン状態では、ゲート領域１３とソース領域１２の間に形成されているｐｎ接合が順バイアスされて、ゲート領域１３からソース領域１２に制御電流である正孔電流が流れる。 In the BJT 10, the main current is an electron flow that flows from the emitter region 12 (or the emitter electrode 19) to the collector region 11 (or the collector electrode 18). The emitter region 12 and the collector region 11 are main electrode regions for flowing a main current. Energization (ON) and non-energization (OFF) of the main current are based on a base voltage applied to the base electrode 20, that is, a control signal applied between the base contact region 13 and the base region 15 and the emitter region 12. Be controlled. The base contact region 13 and the base region 15 are control electrode regions. When the applied voltage between the base and the emitter is 0 V or less, the BJT 10 does not flow main current and is turned off. When a voltage of a certain level or higher is applied between the base and the emitter, the BJT 10 is turned on due to the main current flowing. In the ON state, the pn junction formed between the gate region 13 and the source region 12 is forward-biased, and a hole current that is a control current flows from the gate region 13 to the source region 12.
　図３と図４を参照し、従来のＢＪＴ構造と本実施形態に係るＢＪＴ構造とを対比しながら、ＢＪＴ１０の特徴的構造を説明する。 Referring to FIGS. 3 and 4, the characteristic structure of BJT 10 will be described while comparing the conventional BJT structure and the BJT structure according to the present embodiment.
　図３は従来の構造を有するＢＪＴ１０Ａを示す。図３において、上記の図１で説明した要素と同一の要素には同一の符号を付している。ＢＪＴ １０Ａがオンの状態では、制御電流である正孔電流が、ベース電極２０、ベースコンタクト領域１３、ベース領域１５を経由してエミッタ領域１２に流れ込む。一方、エミッタ領域１２からコレクタ領域には主電流である電子電流１２が流れる。ベース領域１５内には高い密度で正孔が存在するためにエミッタ領域１２から流れ込みベース領域１５の近傍に存在する正孔３２と電子３３とが活発に再結合することになる。特にベースコンタクト領域１３の直下のベース領域、ベースコンタクト領域１３とエミッタ領域１２の間のベース領域は主電流が流れないにも関わらず電子と正孔の再結合が活発な領域であるため、電流増幅率の低下に大きな影響を与えている。 FIG. 3 shows a BJT 10A having a conventional structure. In FIG. 3, the same elements as those described in FIG. When the BJT 10A is on, a hole current that is a control current flows into the emitter region 12 via the base electrode 20, the base contact region 13, and the base region 15. On the other hand, an electron current 12 which is a main current flows from the emitter region 12 to the collector region. Since holes exist at a high density in the base region 15, the holes 32 flow from the emitter region 12 and the electrons 33 existing in the vicinity of the base region 15 are actively recombined. In particular, the base region immediately below the base contact region 13 and the base region between the base contact region 13 and the emitter region 12 are regions in which recombination of electrons and holes is active even though the main current does not flow. This greatly affects the decrease in amplification factor.
　従来構造を有するＢＪＴ１０Ａに対して、本実施例によるＢＪＴ１０では、図４に示すように、ベース領域１５におけるベースコンタクト領域１３に接触するまたは隣接する部分の上下面に層状の再結合抑制領域１６が形成される。当該再結合抑制領域１６は、隣り合う２つのエミッタ領域１２の間に位置する領域部分に例えばイオン注入を行うことにより形成される。再結合抑制領域１６は、ベース領域１５と同じ導電型で抵抗率がベース領域１５よりも高いｐ－半導体か第１および第２のｎ型高抵抗層１４Ａ，１４Ｂと同じ導電型で抵抗率が第１および第２のｎ型高抵抗層１４Ａ，１４Ｂよりも高いｎ－半導体で構成されている。 In contrast to the BJT 10A having the conventional structure, in the BJT 10 according to the present embodiment, as shown in FIG. 4, the layered recombination suppression regions 16 are formed on the upper and lower surfaces of the base region 15 in contact with or adjacent to the base contact region 13. It is formed. The recombination suppression region 16 is formed by, for example, ion implantation in a region portion located between two adjacent emitter regions 12. Recombination-inhibiting region 16, the resistivity of the same conductivity type as the base region 15 is higher than the base region 15 p - semiconductor or the first and second n-type high-resistance layer 14A, the resistivity is the same conductivity type as 14B first and second n-type high-resistance layer 14A, higher n than 14B - is composed of a semiconductor.
　再結合抑制領域１６がｐ－半導体で構成されている場合には、「ｐ－」の領域で形成されており、再結合抑制領域１６内の正孔密度がベース領域１５と比較して低く抑えられている上に、再結合抑制領域１６とｎ－高抵抗層１４Ａ，１４Ｂとの間にｐｎ接合による電子に対する電位障壁が形成されるためにベース領域１５への電子の侵入が抑制される。電子３３に対する高い電子障壁となっている。そのため、この再結合抑制領域１６が存在することによって、ベースコンタクト領域１３からベース領域１５に流れた正孔３２は図４中右方へ移動し、エミッタ領域１２から流れ込む一部の主電流Ｉ２は、ベース領域１５のベースコンタクト領域近傍の部分に引き寄せられなくなる。図４に示すように、ベース領域１５近傍での電子と正孔の再結合が抑制され、ＢＪＴ１０の電流増幅率を向上させることができる。 When the recombination suppression region 16 is made of a p − semiconductor, it is formed of the “p − ” region, and the hole density in the recombination suppression region 16 is suppressed to be lower than that of the base region 15. In addition, since a potential barrier against electrons due to a pn junction is formed between the recombination suppression region 16 and the n − high resistance layers 14A and 14B, the entry of electrons into the base region 15 is suppressed. This is a high electron barrier against the electrons 33. Therefore, the presence of the recombination suppression region 16 causes the holes 32 flowing from the base contact region 13 to the base region 15 to move to the right in FIG. 4, and a part of the main current I2 flowing from the emitter region 12 is The base region 15 is not attracted to the vicinity of the base contact region. As shown in FIG. 4, the recombination of electrons and holes in the vicinity of the base region 15 is suppressed, and the current amplification factor of the BJT 10 can be improved.
　再結合抑制領域１６がｎ－半導体で構成されている場合には、再結合抑制領域１６内の電子密度がｎ－高抵抗層１４Ａ，１４Ｂと比較して低く抑えられている上に、ベース領域１５と再結合抑制領域１６との間にｐｎ接合による正孔に対する電位障壁が形成されるためにベース領域１５から再結合抑制領域１６への正孔の侵入が抑制される。その結果、ＢＪＴ１０の電流増幅率を向上させることができる。 When the recombination suppression region 16 is made of an n − semiconductor, the electron density in the recombination suppression region 16 is suppressed to be lower than that of the n− high resistance layers 14A and 14B, and the base region Since a potential barrier against holes due to a pn junction is formed between 15 and the recombination suppression region 16, penetration of holes from the base region 15 into the recombination suppression region 16 is suppressed. As a result, the current amplification factor of the BJT 10 can be improved.
　再結合抑制領域１６を形成する際、ベースコンタクト領域１３を作る場合と同様に、Ａｌ等のイオン注入法を用いる。この場合、注入深さが浅く注入濃度も低いことから、再結合抑制領域１６を形成する際に新たな再結合準位は生成されることはない。 When forming the recombination suppression region 16, an ion implantation method of Al or the like is used as in the case of forming the base contact region 13. In this case, since the implantation depth is shallow and the implantation concentration is low, no new recombination level is generated when the recombination suppression region 16 is formed.
　次に、図５と図６を参照してＢＪＴ１０の製造方法を説明する。図５は製造方法の各ステップを示すフローチャートである。図６の（ａ）～（ｄ）は各ステップで製作される構造を示す縦断面図である。 Next, a method for manufacturing the BJT 10 will be described with reference to FIGS. FIG. 5 is a flowchart showing each step of the manufacturing method. 6 (a) to 6 (d) are longitudinal sectional views showing the structure manufactured in each step.
　ＢＪＴ１０の製造方法は、次のプロセス（１）～（１１）（ステップＳ１１～Ｓ２１）から成っている。図５に示されるようにステップＳ１１からステップＳ２１に到る順序で実行される。 The manufacturing method of the BJT 10 includes the following processes (1) to (11) (steps S11 to S21). As shown in FIG. 5, the process is executed in the order from step S11 to step S21.
　（１）高抵抗層形成プロセス（ステップＳ１１）
　（２）ベース領域形成プロセス（ステップＳ１２）
　（３）高抵抗層形成プロセス（ステップＳ１３）
　（４）低抵抗層形成プロセス（ステップＳ１４）
　（５）エミッタエッチングプロセス（ステップＳ１５）
　（６）再結合抑制領域形成プロセス（ステップＳ１６）
　（７）ベースコンタクト領域形成プロセス（ステップＳ１７）
　（８）イオン注入層活性化プロセス（ステップＳ１８）
　（９）表面保護膜形成プロセス（ステップＳ１９）
　（１０）電極形成プロセス（ステップＳ２０）
　（１１）上層電極形成プロセス（ステップＳ２１） (1) High resistance layer forming process (step S11)
(2) Base region formation process (step S12)
(3) High resistance layer formation process (step S13)
(4) Low resistance layer formation process (step S14)
(5) Emitter etching process (step S15)
(6) Recombination suppression region formation process (step S16)
(7) Base contact region formation process (step S17)
(8) Ion implantation layer activation process (step S18)
(9) Surface protective film formation process (step S19)
(10) Electrode formation process (step S20)
(11) Upper layer electrode formation process (step S21)
　上記のステップＳ１１～Ｓ１４を実施することによって図６の（ａ）に示される構造が形成される。 The structure shown in FIG. 6A is formed by performing the above steps S11 to S14.
　高抵抗層形成プロセス（ステップＳ１１）では、ＳｉＣで形成されたｎ型基板４０の上に、エピタキシャル成長法により、厚さ１０μｍで、濃度１×１０１６ｃｍ－３の窒素を不純物としてドープした高抵抗層４１を成長させる。基板４０には「４Ｈ－ＳｉＣ（0001）８°off」が用いられている。また基板４０は、前述したｎ型低抵抗層のコレクタ領域１１となる。 In the high resistance layer formation process (step S11), a high resistance in which nitrogen having a thickness of 10 μm and a concentration of 1 × 10 16 cm −3 is doped as an impurity on an n-type substrate 40 formed of SiC by an epitaxial growth method. Layer 41 is grown. “4H—SiC (0001) 8 ° off” is used for the substrate 40. The substrate 40 becomes the collector region 11 of the n-type low resistance layer described above.
　ベース領域形成プロセス（ステップＳ１２）では、ｎ型高抵抗層４１の上に、エピタキシャル成長法により、アルミニウム（Ａｌ）を不純物として４×１０１７～２×１０１８ｃｍ－３の濃度で０．１～０．５μｍのｐ型のベース領域４２を成長させる。 In the base region formation process (step S12), 0.1 to a concentration of 4 × 10 17 to 2 × 10 18 cm −3 with aluminum (Al) as an impurity is formed on the n-type high resistance layer 41 by epitaxial growth. A 0.5 μm p-type base region 42 is grown.
　高抵抗層形成プロセス（ステップＳ１３）では、その後、ベース領域４２の上に、エピタキシャル成長法により、厚さ０．１～０．４μｍで濃度５×１０１５～５×１０１７ｃｍ－３の窒素を不純物としてドープしたｎ型の高抵抗層４３を成長させる。 In the high resistance layer formation process (step S13), nitrogen having a thickness of 0.1 to 0.4 μm and a concentration of 5 × 10 15 to 5 × 10 17 cm −3 is then formed on the base region 42 by an epitaxial growth method. An n-type high resistance layer 43 doped as an impurity is grown.
　低抵抗層形成プロセス（ステップＳ１４）では、ｎ型の高抵抗層４３の上に、エピタキシャル成長法により、厚さ０．５～２．０μｍで濃度１～５×１０１９ｃｍ－３の窒素を不純物としてドープしたｎ型の低抵抗層４４を成長させる。この低抵抗層４４は、前述したエミッタ領域１２を形成する部分である。 In the low resistance layer formation process (step S14), nitrogen is doped on the n-type high resistance layer 43 by an epitaxial growth method with a thickness of 0.5 to 2.0 μm and a concentration of 1 to 5 × 10 19 cm −3. An n-type low resistance layer 44 doped as follows is grown. The low resistance layer 44 is a portion for forming the emitter region 12 described above.
　次のエミッタエッチングプロセス（ステップＳ１５）では、図６の（ａ）に示された構造において、その上面に、ＣＶＤ法によりシリコン酸化膜５１を堆積させ、フォトリソグラフィーを行い、その後にＲＩＥによりシリコン酸化膜５１をエッチングする。こうしてマスクが形成される。このシリコン酸化膜５１を用いて、その後、ＲＩＥにより低抵抗層４４についてＳｉＣエッチングを行い、低抵抗層４４を利用して前述したエミッタ領域１２を形成する。ＳｉＣエッチングのＲＩＥではＳＦ６などのガス雰囲気中でエッチングが行われる。その結果得られた構造を図６の（ｂ）に示す。なおエッチング深さは例えば約０．５～２．３μｍである。 In the next emitter etching process (step S15), a silicon oxide film 51 is deposited on the upper surface of the structure shown in FIG. 6A by CVD, photolithography is performed, and then silicon oxide is oxidized by RIE. The film 51 is etched. Thus, a mask is formed. Then, using this silicon oxide film 51, SiC etching is performed on the low resistance layer 44 by RIE, and the emitter region 12 is formed using the low resistance layer 44. Etching is performed in a gas atmosphere such as RIE in SF 6 for SiC etching. The resulting structure is shown in FIG. The etching depth is, for example, about 0.5 to 2.3 μm.
　再結合抑制領域を形成するプロセス（Ｓ１６）では、図６の（ｃ）に示されるように、再結合抑制領域１６を形成するためのマスク５２が形成される。このマスク形成では、ＣＶＤ法によりシリコン酸化膜を堆積し、フォトリソグラフィーを行い、その後にＲＩＥにより再結合抑制領域１６を形成する部分のシリコン酸化膜をエッチングする。その後に、不純物（イオン種）としてアルミニウム（Ａｌ）のイオン注入を行う。注入する領域は、隣り合う２つのエミッタ領域１２の間の範囲である。 In the process (S16) for forming the recombination suppression region, as shown in FIG. 6C, a mask 52 for forming the recombination suppression region 16 is formed. In this mask formation, a silicon oxide film is deposited by the CVD method, photolithography is performed, and then the silicon oxide film in a portion where the recombination suppression region 16 is to be formed is etched by RIE. Thereafter, ion implantation of aluminum (Al) as an impurity (ion species) is performed. The region to be implanted is a range between two adjacent emitter regions 12.
　注入する不純物の量は、再結合抑制領域１６をｎ－型あるいはｐ－型の半導体にするという観点からｎ－高抵抗層１４Ａ，１４Ｂのｎ型不純物濃度と同程度かその前後の値が望ましい。例えばｎ－高抵抗層１４Ａ，１４Ｂのｎ型不純物濃度が１×１０１６ｃｍ－３である場合には、イオン注入量が５×１０１５～５×１０１６ｃｍ－３の範囲内であることが望ましい。一方、注入エネルギーはＳｉＣ表面からベース領域１５までの厚さに応じて適切な値が設定される。例えば、１００～５００ｋｅＶの範囲の注入エネルギーを用いることで所望の再結合抑制領域１６を形成することができる。注入量が少なく注入エネルギーも低く抑えられることから、このプロセスで新たな再結合準位が生成されることはない。 The amount of the impurity to be implanted is preferably the same as or around the n-type impurity concentration of the n − high resistance layers 14A and 14B from the viewpoint of making the recombination suppression region 16 an n − or p − type semiconductor. . For example, when the n-type impurity concentration of the n − high resistance layers 14A and 14B is 1 × 10 16 cm −3 , the ion implantation amount is in the range of 5 × 10 15 to 5 × 10 16 cm −3. Is desirable. On the other hand, the implantation energy is set to an appropriate value according to the thickness from the SiC surface to the base region 15. For example, the desired recombination suppression region 16 can be formed by using an implantation energy in the range of 100 to 500 keV. Since the injection amount is small and the injection energy is kept low, no new recombination level is generated in this process.
　ベースコンタクト領域形成プロセス（ステップＳ１７）では、図６の（ｄ）に示すように、さらにベースコンタクト領域１３を形成するための表面部分が露出するように、マスク５３が形成される。マスク５３は、さらにＣＶＤ法によりシリコン酸化膜を堆積し、フォトリソグラフィーを行い、その後にＲＩＥによりシリコン酸化膜をエッチングすることにより形成される。その後、イオン注入してベースコンタクト領域１３を形成する。注入されるイオンはアルミニウム（Ａｌ）であり、注入の深さは例えば０．１～０．３μｍである。イオン注入量は１×１０１８～１×１０１９ｃｍ－３である。 In the base contact region forming process (step S17), as shown in FIG. 6D, the mask 53 is formed so that the surface portion for forming the base contact region 13 is further exposed. The mask 53 is formed by further depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, the base contact region 13 is formed by ion implantation. The ion to be implanted is aluminum (Al), and the depth of implantation is, for example, 0.1 to 0.3 μm. The ion implantation amount is 1 × 10 18 to 1 × 10 19 cm −3 .
　イオン注入層を活性化するプロセス（ステップＳ１８）では、イオン注入後に、注入イオンを半導体中で電気的に活性化すると共に、イオン注入で発生した結晶欠陥を消すための熱処理を行う。この活性化の熱処理では、ベースコンタクト領域１３の注入イオンと再結合抑制領域１６の注入イオンの両方の活性化を同時に行っている。高周波熱処理炉などを用い、１７００～１８００℃程度の高温下で約１０分程度の熱処理を行う。雰囲気ガスには例えばアルゴンガス（Ａｒ）を用いる。 In the process of activating the ion implantation layer (step S18), after the ion implantation, the implanted ions are electrically activated in the semiconductor, and a heat treatment is performed to eliminate crystal defects generated by the ion implantation. In this activation heat treatment, both the implanted ions in the base contact region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time. Using a high-frequency heat treatment furnace or the like, heat treatment is performed at a high temperature of about 1700 to 1800 ° C. for about 10 minutes. For example, argon gas (Ar) is used as the atmospheric gas.
　その後、表面保護膜を形成するプロセス（ステップＳ１９）が実施される。このプロセスでは、初めに、イオン注入プロセスと活性化プロセスで生じた表面層を取り除くために、熱酸化後に酸化膜を取り除く犠牲酸化を行う。その後に、ＳｉＣ酸化膜界面の不純物準位を低減するための熱処理（ＰＯＡ：Post Oxidation Anneal)を行う。 Thereafter, a process of forming a surface protective film (step S19) is performed. In this process, first, sacrificial oxidation is performed to remove the oxide film after thermal oxidation in order to remove the surface layer generated in the ion implantation process and the activation process. Thereafter, heat treatment (POA: Post-Oxidation-Anneal) is performed to reduce the impurity level at the interface of the SiC oxide film.
　次に電極を形成するプロセス（ステップＳ２０）が行われる。このプロセスでは、エミッタ領域１２（低抵抗層４４）、ベースコンタクト領域１３、コレクタ領域１１（基板４０）の各々の表面にエミッタ電極１９、ベース電極２０、コレクタ電極１８を形成する。エミッタ電極１９、コレクタ電極１８にはニッケルやチタンを用い、ベース電極２０にはチタン／アルミニウムの積層膜などを用いる。各電極１８，１９，２０は、蒸着やスパッタリングなどで形成する。電極パターンの形成には、ドライエッチング、ウェットエッチング、リフトオフ法などが利用される。また電極１８～２０を形成した後には、金属部分と半導体部分との間の接触抵抗を低減するために熱処理を行う。当該熱処理の条件は、温度条件が８００～１０００℃、時間条件が１０～３０分程度である。 Next, a process for forming an electrode (step S20) is performed. In this process, an emitter electrode 19, a base electrode 20, and a collector electrode 18 are formed on the surfaces of the emitter region 12 (low resistance layer 44), the base contact region 13, and the collector region 11 (substrate 40). The emitter electrode 19 and the collector electrode 18 are made of nickel or titanium, and the base electrode 20 is made of a titanium / aluminum laminated film. Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used. Further, after the electrodes 18 to 20 are formed, heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion. The heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.
　最後に上層電極を形成するプロセス（ステップＳ２１）が実行される。このプロセスでは、分離されている複数のエミッタ電極１２を１つの電極に取り出すための上層配線を形成する。 Finally, the process of forming the upper layer electrode (step S21) is executed. In this process, an upper layer wiring for taking out a plurality of separated emitter electrodes 12 to one electrode is formed.
　以上のようにして、図１と図２で示したＢＪＴ１０が作製される。 As described above, the BJT 10 shown in FIGS. 1 and 2 is manufactured.
　上記の第１実施例では、図１に示した再結合抑制領域１６がｐ型領域（第２の導電型）である例を説明したが、これをｎ型領域（第１の導電型）とすることもできる。 In the first embodiment described above, the example in which the recombination suppression region 16 shown in FIG. 1 is a p-type region (second conductivity type) has been described, but this is referred to as an n-type region (first conductivity type). You can also
　上記の第１実施例において、コレクタ領域、エミッタ領域、高抵抗層、ベース領域、ベースコンタクト領域、再結合抑制領域等の第１および第２の導電型の組合せをすべて逆にして構成することもできる。当該組合せを具体的に説明すると、次の通りになる。この点については、以下の実施例においても同様である。 In the first embodiment, the combination of the first and second conductivity types such as the collector region, the emitter region, the high resistance layer, the base region, the base contact region, and the recombination suppression region may be reversed. it can. The combination will be specifically described as follows. This also applies to the following embodiments.
　主電流を流す２つの領域を第１および第２の主電極用領域とするとき、ＢＪＴの場合には次の通りとなる。 When the two regions through which the main current flows are used as the first and second main electrode regions, in the case of BJT, the following occurs.
　第１の組合せは、第１の主電極用領域が第１の導電型の低抵抗層からなるコレクタ領域、第２の主電極用領域が第１の導電型の低抵抗層からなるエミッタ領域、制御電極用領域が第２の導電型のベースコンタクト領域（ベース領域）、および再結合抑制領域がベースコンタクト領域と同じ第２の導電型かエミッタ領域と同じ第１の導電型を有する組合せである。 In the first combination, the first main electrode region is a collector region made of a low resistance layer of the first conductivity type, the second main electrode region is an emitter region made of a low resistance layer of the first conductivity type, The control electrode region is a second contact type base contact region (base region), and the recombination suppression region is a combination having the same second conductivity type as the base contact region or the same first conductivity type as the emitter region. .
　第２の組合せは、第１の主電極用領域が第２の導電型の低抵抗層からなるコレクタ領域、第２の主電極用領域が第２の導電型の低抵抗層からなるエミッタ領域、制御電極用領域が第１の導電型のベースコンタクト領域（ベース領域）、および再結合抑制領域がベースコンタクト領域と同じ第１の導電型かエミッタ領域と同じ第２の導電型を有する組合せである。 In the second combination, the first main electrode region is a collector region made of the second conductive type low resistance layer, the second main electrode region is made of the second conductive type low resistance layer, The control electrode region is a base contact region (base region) of the first conductivity type, and the recombination suppression region is a combination having the same first conductivity type as the base contact region or the same second conductivity type as the emitter region. .
　主電流を流す２つの領域を第１および第２の主電極用領域とするとき、ＳＩＴの場合には次の通りである。 In the case of SIT, when the two regions through which the main current flows are used as the first and second main electrode regions, it is as follows.
　第１の組合せは、第１の主電極用領域が第１の導電型の低抵抗層からなるドレイン領域、第２の主電極用領域が第１の導電型の低抵抗層からなるソース領域、制御電極用領域が第２の導電型のゲート領域、および再結合抑制領域がゲート領域と同じ第２の導電型かソース領域と同じ第１の導電型を有する組合せである。 In the first combination, the first main electrode region is a drain region made of a low resistance layer of the first conductivity type, the second main electrode region is a source region made of a low resistance layer of the first conductivity type, The control electrode region has a second conductivity type gate region, and the recombination suppression region has the same second conductivity type as the gate region or the same first conductivity type as the source region.
　第２の組合せは、第１の主電極用領域が第２の導電型の低抵抗層からなるドレイン領域、第２の主電極用領域が第２の導電型の低抵抗層からなるソース領域、制御電極用領域が第１の導電型のゲート領域、および再結合抑制領域がゲート領域と同じ第１の導電型かソース領域と同じ第２の導電型を有する組合せである。 In the second combination, the first main electrode region is a drain region made of the second conductivity type low resistance layer, the second main electrode region is made of the second conductivity type low resistance layer, The control electrode region is a combination of the first conductivity type gate region and the recombination suppression region having the same first conductivity type as the gate region or the same second conductivity type as the source region.
　ＳＩＴの場合には、そのチャネルドープ層がＢＪＴのベース領域に対応し、そのゲート領域がＢＪＴのベースコンタクト領域に対応する。 In the case of SIT, the channel dope layer corresponds to the base region of BJT, and the gate region corresponds to the base contact region of BJT.
　＜第２実施例＞
　図７を参照して本発明による接合型半導体装置の第２実施例を説明する。図７は図１と同様な図である。第２実施例による接合型半導体装置も同様にまたＢＪＴである。図７において、図１で説明した要素と実質的に同一の要素には同一の符号を付している。第２実施例によるＢＪＴ１００では、ベースコンタクト領域１３に接触するベースコンタクト領域近傍のベース領域１５の部分１５Ａを他のベース領域と比較して抵抗率の小さいｐ＋領域で形成している点に特徴がある。またこの実施例では、ベースコンタクト領域１３は、その底面部分がベース領域１５の低抵抗部分１５Ａと接触するように形成されている。なお低抵抗部分１５Ａの厚みを、ベース領域１５のその他の部分よりもより大きな厚みで作ることも望ましい。その他の構成については第１実施例で説明した構成と同じである。 <Second embodiment>
A second embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. FIG. 7 is a view similar to FIG. The junction type semiconductor device according to the second embodiment is also a BJT. In FIG. 7, elements that are substantially the same as those described in FIG. 1 are given the same reference numerals. The BJT 100 according to the second embodiment is characterized in that the portion 15A of the base region 15 in the vicinity of the base contact region that is in contact with the base contact region 13 is formed by a p + region having a lower resistivity than other base regions. There is. Further, in this embodiment, the base contact region 13 is formed such that the bottom portion thereof is in contact with the low resistance portion 15 </ b> A of the base region 15. It is also desirable to make the thickness of the low resistance portion 15A larger than that of the other portions of the base region 15. Other configurations are the same as those described in the first embodiment.
　ＢＪＴ１００がオン状態にある場合、制御電流である正孔電流はベース電極２０からベースコンタクト領域１３、低抵抗部分１５Ａ、ベース領域１５を経由してエミッタ領域１２に流れる。本実施例では、ベース領域１５の一部を低抵抗としているために従来構造と比較して制御電流が低抵抗部分１５Ａに集中し、再結合準位が多く存在するベースコンタクト領域１３とエミッタ領域１２間の高抵抗層１４ＢのＳｉＣ表面には流れにくくなる。そのため、従来構造では活発に起きるＳｉＣ表面での再結合が抑制され、その結果電流増幅率が向上する。 When the BJT 100 is in the ON state, a hole current that is a control current flows from the base electrode 20 to the emitter region 12 via the base contact region 13, the low resistance portion 15 A, and the base region 15. In this embodiment, since a part of the base region 15 has a low resistance, the control current is concentrated in the low resistance portion 15A as compared with the conventional structure, and the base contact region 13 and the emitter region where many recombination levels exist. It becomes difficult to flow on the SiC surface of the high resistance layer 14B between the twelve. Therefore, recombination on the SiC surface that occurs actively in the conventional structure is suppressed, and as a result, the current amplification factor is improved.
　第２実施例によるＢＪＴ１００の製造方法は、第１実施例によるＢＪＴ１０の製造方法において、前述のベース領域形成プロセス（ステップＳ１２）で、形成したベース領域１５に対して所定の部分１５Ａについて低抵抗部分を形成するための工程をその後に設けることにより構成される。第１実施例における再結合抑制領域形成プロセス（ステップＳ１６）において注入量と注入エネルギーを１５Ａの形成に合わせて設計すれば良い。注入エネルギーは第１実施例とほぼ同程度であり、注入量は低抵抗部分１５Ａの不純物濃度がベース領域１５よりも高くなるように設定する。例えば、１×１０１８～１×１０１９ｃｍ－３程度の不純物濃度とする。 The manufacturing method of the BJT 100 according to the second embodiment is the same as the manufacturing method of the BJT 10 according to the first embodiment, except that the predetermined portion 15A of the base region 15 formed in the base region forming process (step S12) is a low resistance portion. It is comprised by providing after that the process for forming. In the recombination suppression region forming process (step S16) in the first embodiment, the injection amount and the injection energy may be designed in accordance with the formation of 15A. The implantation energy is substantially the same as that of the first embodiment, and the implantation amount is set so that the impurity concentration of the low resistance portion 15A is higher than that of the base region 15. For example, the impurity concentration is about 1 × 10 18 to 1 × 10 19 cm −3 .
　上記の第２実施例の構成をＳＩＴに適用する場合には、そのチャネルドープ層が、上記の低抵抗部分１５Ａに相当するチャネルドープ層部分（第１チャネルドープ層）と、その他の通常的なチャネルドープ層部分（第２チャネルドープ層）とから構成されることになる。第１チャネルドープ層と第２チャネルドープ層は連接している。 When the configuration of the second embodiment is applied to SIT, the channel dope layer is divided into a channel dope layer portion (first channel dope layer) corresponding to the low resistance portion 15A, and other normal ones. It is comprised from a channel dope layer part (2nd channel dope layer). The first channel dope layer and the second channel dope layer are connected.
　＜第３実施例＞
　図８を参照して本発明による接合型半導体装置の第３の実施例を説明する。第３実施例の接合型半導体装置はＢＪＴである。図８において、図１で説明した要素と実質的に同一の要素には同一の符号を付している。第３実施例のＢＪＴ２００では、第１実施例の特徴的構成と第２実施例の特徴的構成を組み合わせた構成を備えている。すなわち、ベース領域１５の所定領域に低抵抗部分１５Ａを形成すると共に、当該低抵抗部分１５Ａの上下面に前述した再結合抑制領域１６で覆うように構成されている。その他の構成については第１または第２の実施例で説明した構成と同じである。第３実施例のＢＪＴ２００においては、再結合抑制領域１６によりベース領域での再結合が抑制できる上にＳｉＣ表面での再結合も抑制できるために、極めて高い電流増幅率を実現することができる。また、製造方法も複雑になることはなく、第１実施例の再結合抑制領域形成プロセスにおいてイオン注入を行う際に深さに応じて必要な注入量を設定して多段階の注入を行えばよい。 <Third embodiment>
A third embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device of the third embodiment is BJT. In FIG. 8, elements that are substantially the same as those described in FIG. The BJT 200 of the third embodiment has a configuration in which the characteristic configuration of the first embodiment and the characteristic configuration of the second embodiment are combined. That is, the low resistance portion 15A is formed in a predetermined region of the base region 15, and the upper and lower surfaces of the low resistance portion 15A are covered with the recombination suppression region 16 described above. Other configurations are the same as those described in the first or second embodiment. In the BJT 200 of the third embodiment, since recombination in the base region can be suppressed by the recombination suppression region 16 and recombination on the SiC surface can also be suppressed, an extremely high current amplification factor can be realized. Also, the manufacturing method is not complicated, and when performing ion implantation in the recombination suppression region forming process of the first embodiment, a necessary implantation amount is set according to the depth and multistage implantation is performed. Good.
　＜第４実施例＞
　図９を参照して本発明による接合型半導体装置の第４実施例を説明する。第４実施例の接合型半導体装置はＢＪＴの例を示している。図９に示したＢＪＴ３００は、前述した第１実施例のＢＪＴ１０の変形例である。本実施例のＢＪＴ３００では、再結合抑制領域１６は、ベースコンタクト領域の表面からベース領域１５の下面側まで形成されている。その他の構成については第１の実施例で説明した構成と同じである。第４実施例のＢＪＴ３００においては、ベース領域１５よりも高抵抗のｐ－半導体あるいはｎ－高抵抗層１４Ａ，１４Ｂよりも高抵抗のｎ－半導体でＳｉＣ表面からベース領域１５を覆うことにより、ベース領域１５近傍とＳｉＣ表面の両方での再結合を抑制することができる。 <Fourth embodiment>
A fourth embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device of the fourth embodiment shows an example of BJT. A BJT 300 shown in FIG. 9 is a modification of the BJT 10 of the first embodiment described above. In the BJT 300 of the present embodiment, the recombination suppression region 16 is formed from the surface of the base contact region to the lower surface side of the base region 15. Other configurations are the same as those described in the first embodiment. In BJT300 the fourth embodiment, p of higher resistance than the base region 15 - semiconductor or n - high resistance layer 14A, the high resistance of the n than 14B - by the SiC surface covering base region 15 in the semiconductor base Recombination in both the vicinity of the region 15 and the SiC surface can be suppressed.
　以上、各実施例で説明された構成、形状、大きさおよび配置関係については本発明が理解・実施できる程度に概略的に示したものにすぎず、また数値および各構成の組成（材質）等については例示にすぎない。従って本発明は、説明された実施形態に限定されるものではなく、特許請求の範囲に示される技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。 The configurations, shapes, sizes, and arrangement relationships described in the embodiments are merely shown to the extent that the present invention can be understood and implemented, and numerical values and compositions (materials) of the respective configurations Is merely an example. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.
　本発明は、高性能の接合型半導体装置とそれを製造するために利用することができる。 The present invention can be used for manufacturing a high performance junction type semiconductor device.
　１０　接合型半導体装置（ＢＪＴ）
　１１　コレクタ領域
　１２　エミッタ領域
　１３　ベースコンタクト領域
　１４　高抵抗層
　１５　ベース領域
　１５Ａ　低抵抗部分
　１６　再結合抑制領域
　１７　表面保護膜
　１８　コレクタ電極
　１９　エミッタ電極
　２０　ベース電極
　２１　上層電極
　４０　基板
　４１，４３　高抵抗層
　４２　ベース領域
　４４　低抵抗層
　１００　接合型半導体装置（ＢＪＴ）
　２００　接合型半導体装置（ＢＪＴ）
　３００　接合型半導体装置（ＢＪＴ） 10 Junction semiconductor devices (BJT)
DESCRIPTION OF SYMBOLS 11 Collector area | region 12 Emitter area | region 13 Base contact area | region 14 High resistance layer 15 Base area | region 15A Low resistance part 16 Recombination suppression area | region 17 Surface protective film 18 Collector electrode 19 Emitter electrode 20 Base electrode 21 Upper layer electrode 40 Substrate 41, 43 High resistance layer 42 Base region 44 Low resistance layer 100 Junction semiconductor device (BJT)
200 Junction semiconductor devices (BJT)
300 Junction semiconductor device (BJT)

Claims (4)

  1. 　炭化珪素の半導体結晶で作られた基板である第１の主電極用領域と、
    　前記基板の１つの面の側に形成された第２の主電極用領域と、
    　前記の第１および第２の主電極用領域の間に形成された高抵抗層と、
    　前記第２の主電極用領域の周囲に形成された制御電極用領域と、
    　前記高抵抗層内に形成され、前記制御電極用領域に接触する中間層と、
    　前記中間層における前記制御電極用領域に接触する部分を覆うように形成された再結合抑制領域と、
    　を有する接合型半導体装置。     A first main electrode region which is a substrate made of a silicon carbide semiconductor crystal;
    A second main electrode region formed on one side of the substrate;
    A high resistance layer formed between the first and second main electrode regions;
    A control electrode region formed around the second main electrode region;
    An intermediate layer formed in the high resistance layer and in contact with the control electrode region;
    A recombination suppression region formed so as to cover a portion in contact with the control electrode region in the intermediate layer;
    A junction type semiconductor device.
  2. 　炭化珪素の半導体結晶で作られた基板である第１の主電極用領域と、
    　前記基板の１つの面の側に形成された第２の主電極用領域と、
    　前記の第１および第２の主電極用領域の間に形成された高抵抗層と、
    　前記第２の主電極用領域の周囲に形成された制御電極用領域と、
    　前記高抵抗層内に形成され、前記制御電極用領域に接触し、かつ低抵抗である第１中間層と、
    　前記高抵抗層内に形成され、前記第１中間層に連接し、かつ前記の第１および第２の主電極用領域の間に配置される第２中間層と、
    　を有する接合型半導体装置。     A first main electrode region which is a substrate made of a silicon carbide semiconductor crystal;
    A second main electrode region formed on one side of the substrate;
    A high resistance layer formed between the first and second main electrode regions;
    A control electrode region formed around the second main electrode region;
    A first intermediate layer formed in the high resistance layer, in contact with the control electrode region, and having a low resistance;
    A second intermediate layer formed in the high resistance layer, connected to the first intermediate layer, and disposed between the first and second main electrode regions;
    A junction type semiconductor device.
  3. 　炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、
    　前記高抵抗層の中に中間層を形成する第２の工程と、
    　前記高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第３の工程と、
    　前記高抵抗層の表面側における制御電極用領域の形成を予定する所定領域の近傍で、前記中間層の上下の面に接するようにイオン注入により再結合抑制領域を形成する第４の工程と、
    　前記高抵抗層の表面側における前記所定領域にイオン注入により前記制御電極用領域を前記中間層に接触するように形成する第５の工程と、
    　を含む接合型半導体装置の製造方法。     A first step of forming a high resistance layer on a substrate made of a semiconductor crystal of silicon carbide and serving as a first main electrode region;
    A second step of forming an intermediate layer in the high resistance layer;
    A third step of forming a low resistance layer to be a second main electrode region on the high resistance layer;
    A fourth step of forming a recombination suppression region by ion implantation so as to be in contact with the upper and lower surfaces of the intermediate layer in the vicinity of a predetermined region scheduled to form a control electrode region on the surface side of the high resistance layer;
    A fifth step of forming the control electrode region in contact with the intermediate layer by ion implantation in the predetermined region on the surface side of the high resistance layer;
    A method for manufacturing a junction type semiconductor device including:
  4. 　炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、
    　前記高抵抗層の中に中間層を形成する第２の工程と、
    　前記高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第３の工程と、
    　前記高抵抗層の表面側における制御電極用領域の形成を予定する所定領域の近傍で、前記中間層の一部をイオン注入により低抵抗とする第４の工程と、
    　前記高抵抗層の表面側における前記所定領域にイオン注入により前記制御電極用領域を前記中間層の前記低抵抗部分に接触するように形成する第５の工程と、
    　を含む接合型半導体装置の製造方法。     A first step of forming a high resistance layer on a substrate made of a semiconductor crystal of silicon carbide and serving as a first main electrode region;
    A second step of forming an intermediate layer in the high resistance layer;
    A third step of forming a low resistance layer to be a second main electrode region on the high resistance layer;
    A fourth step in which a part of the intermediate layer is made to have a low resistance by ion implantation in the vicinity of a predetermined region where the formation of the control electrode region on the surface side of the high resistance layer is scheduled;
    A fifth step of forming the control electrode region in contact with the low resistance portion of the intermediate layer by ion implantation in the predetermined region on the surface side of the high resistance layer;
    A method for manufacturing a junction type semiconductor device including:
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