JP5469068B2 - Bipolar silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a bipolar silicon carbide semiconductor device and a method for manufacturing the same, and in particular, is a bipolar silicon carbide semiconductor device having a normal four-layer structure, in which a main current flowing between main electrodes and a control current flowing through a control electrode are The present invention relates to a bipolar silicon carbide semiconductor device suitable for suppressing recombination between the two and increasing the current amplification factor, and a method for manufacturing the same.

  Silicon carbide (Silicon Carbide, hereinafter simply referred to as “SiC”) has a characteristic that it has a larger band gap energy than silicon that is widely applied to semiconductor devices. Therefore, a semiconductor device using SiC is suitable for high voltage, high power, and high temperature operation conditions, and is expected to be applied to power devices and the like. The structures of SiC power devices currently being researched and developed are mainly classified into two types, “MOS type” and “junction type”.

  Here, it demonstrates from a viewpoint of the performance improvement of a junction type SiC power device. Junction SiC power devices include Static Induction Transistor (“SIT”), Junction Field Effect Transistor (“JFET”), or Bipolar Junction Transistor (“BJT”). and so on.

An example of a conventional BJT is one having a structure described in Non-Patent Document 1, for example. The BJT is laminated on the low resistance n ⁺ type 4H-SiC (0001) plane 8 degree off substrate in the order of the n ⁻ type high resistance region, the p type base region, and the n ⁺ type emitter region from below. It is formed. The emitter region is composed of a number of elongated regions. Electrodes for establishing electrical connection to the outside are formed in the emitter region, base region, and collector region.

  FIG. 13 shows a cross section of the BJT disclosed in Non-Patent Document 1. As shown in FIG. 13, the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region. The base contact region 505 of the p-type low resistance region is formed. A collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503 (base contact region 505), and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.

Further, as an example of a conventional BJT with improved device characteristics (current amplification factor), there is one having a structure described in Patent Document 1. The BJT disclosed in Patent Document 1 has a first n-type high resistance layer, a p-type base region, and a second n-type layer on the n ⁺ -type 4H—SiC (0001) surface substrate serving as a collector region from below. A type high resistance layer and an n ⁺ type emitter region are stacked in this order. In the BJT, the emitter region is separated and formed by etching in a predetermined planar pattern shape from the upper surface to the middle of the n ⁺ -type emitter region and the second n-type high resistance layer in the stacked structure. . The BJT has a plurality of emitter regions separated on the upper surface based on a predetermined pattern shape. In the region between the separated emitter regions, an Al ion implantation process is subsequently performed to form a p-type base contact region in contact with the base region. Each of the plurality of separated emitter regions is surrounded by a base contact region when viewed in a BJT planar shape.

  The BJT disclosed in Patent Document 1 has a structure in which the SiC surface of the BJT is covered with a surface recombination suppressing semiconductor layer between the emitter region and the base contact region. The surface recombination suppressing semiconductor layer has a function of suppressing recombination between electrons flowing out from the emitter region and holes flowing out from the base contact region. This suppresses recombination of electrons from the emitter region and holes from the base contact region, and achieves an improvement in the current amplification factor of the junction type semiconductor layer device.

JP 2006-351621 A

J. Zhang et al., “High Power (500V-70A) and High Gain (44-47) 4H-SiC Bipolar Junction Transistors” Materials Science Forum Vols. 457-460 (2004) pp. 1149-1152.

  In a junction type transistor such as BJT, a control electrode portion called a base is formed with a pn junction. In order to pass a current between the main electrode between the emitter and the collector, it is necessary to pass a current through the control electrode. When the current flowing between the main electrodes is “main current Ic” and the current flowing through the control electrode is “control current Ib”, the ratio of both currents (Ic / Ib) is called “current amplification factor”. In the development of BJT, increasing the value of the current gain is an important issue.

  As a factor for reducing the current amplification factor, recombination of holes flowing from the control electrode (carrier of the control current Ib) and electrons flowing between the main electrodes (carrier of the main current Ic) can be mentioned. The value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.

  The SiC surface is known as a site where recombination is likely to occur. In order to reduce the density of recombination levels on the SiC surface, various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1. Further, in BJT of Patent Document 1, in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface. When such a surface recombination-inhibiting semiconductor layer is formed, a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered. Furthermore, the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration. By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.

  As described above, in BJT, many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface.

  On the other hand, in the conventional general BJT having a four-layer structure composed of an emitter region, a base region, a high-resistance layer, and a substrate (collector region) in this order from the upper surface side, recombination as described above has been performed so far. There has not been a sufficient attempt to realize a high current amplification factor by suppressing the above. Even in such a general BJT, the recombination of holes flowing from the control electrode and electrons flowing between the main electrodes via recombination centers existing on the SiC surface causes a reduction in current amplification factor. Another problem is that recombination occurs frequently because both the electron and hole concentrations are high at the interface between the base region and the collector region. In the BJT manufacturing method, the emitter region is etched until the surface of the base region is exposed. At this time, the base region layer needs to be slightly shaved. For this reason, since the base region becomes thin, the resistance increases, and the base resistance varies due to variations in the etching substrate surface. In order to improve the current amplification factor of the BJT, it is desirable to reduce the thickness of the base region. However, if the thickness of the base region is reduced, the increase or variation in base resistance due to the above-described etching process of the emitter region becomes remarkable. Become. For a conventional BJT having a four-layer structure, a device that achieves both a high current gain and a small and stable base resistance has not been realized.

  In view of the above problems, an object of the present invention is a conventional BJT having a four-layer structure, which reduces the recombination probability of electrons and holes, and controls the main current flowing between the main electrodes and the control electrode. An object of the present invention is to provide a bipolar silicon carbide semiconductor device capable of suppressing recombination between currents, improving a current amplification factor, and realizing a small and stable base resistance, and a method for manufacturing the same.

  A first bipolar silicon carbide semiconductor device (corresponding to claim 1) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer. A base region formed thereon, an emitter region formed of a low-resistance layer and bonded to the base region; a low-resistance base contact region formed around the emitter region and bonded to the base region; and a base contact region Near the surface between the emitter region, a recombination suppression region having the same conductivity type as the base region and higher than its resistivity, or a recombination suppression region having the same conductivity type as the emitter region and higher than its resistivity It is characterized by having.

  A second bipolar silicon carbide semiconductor device (corresponding to claim 2) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer. The base region formed above, an emitter region composed of a low resistance layer, joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and the base region, It is characterized by having a buried region that is in contact with the base contact region and has the same conductivity type as the base region and has a resistivity equal to or lower than the resistivity.

  A third bipolar silicon carbide semiconductor device (corresponding to claim 3) includes a collector region which is a substrate made of a silicon carbide semiconductor crystal, a high resistance layer formed on the collector region, and a high resistance layer. A base region formed on the base region, an emitter region joined to the base region, a low resistance base contact region formed around the emitter region and joined to the base region, and a high resistance layer A buried region that is in contact with the base region and has the same conductivity type as the base region and has a higher resistivity than the buried region, or a recombination suppression region that has the same conductivity type as the high resistance region and has a higher resistivity than It is characterized by having.

  In the fourth bipolar silicon carbide semiconductor device (corresponding to claim 4), the collector region is a low-resistance layer of the first conductivity type and the emitter region is a low-resistance layer of the first conductivity type in the above configuration. The high resistance layer is of the first conductivity type, and the base region is of the second conductivity type.

  A first bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 5) includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer In the fourth step, a recombination suppression region having the same conductivity type as the base region and higher in resistivity than the base region exposed by etching, or having the same conductivity type as the emitter region and its resistance A fifth step of forming a recombination suppression region higher than the rate, and a sixth step of forming a base contact region bonded to the base region.

  A second bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 6) includes a first step of forming a high resistance layer on a substrate made of silicon carbide semiconductor crystals and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fifth step of forming a buried region in the base region in contact with the base contact region and having the same conductivity type as the base region and having a resistivity equal to or lower than the resistivity. And a sixth step of forming a base contact region bonded to the base region.

  A third bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 7) includes a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a collector region; A second step of forming a base region on the high resistance layer; a third step of forming a low resistance layer on the base region; and forming an emitter region by partially etching the low resistance layer And a fourth step of contacting the base region with the high-resistance layer and having the same conductivity type as that of the base region and higher than its resistivity, or having the same conductivity type as that of the emitter region and its resistivity. A fifth step of forming a higher buried region, and a sixth step of forming a base contact region bonded to the base region.

  According to a fourth bipolar silicon carbide semiconductor device manufacturing method (corresponding to claim 8), in the above method, a collector electrode, an emitter electrode, and a base electrode are formed in each of the collector region, the emitter region, and the base contact region. And a step of forming an upper layer electrode above the emitter electrode and the base electrode.

The bipolar silicon carbide semiconductor device according to the present invention has the following effects.
First, since the recombination suppression region is formed on the base surface from the base region to the emitter region, it prevents the electron or hole from approaching the recombination level formed on the surface of the silicon carbide semiconductor, thereby increasing the current amplification factor. Can be increased.

  Second, since a buried region having a lower resistance than that of the base region is formed in the base region, holes from the base contact region flow into the buried region to prevent recombination on the surface of the silicon carbide semiconductor, The current amplification factor can be increased.

  Third, since the base region or the buried region having a higher resistance than the high resistance layer is formed in the high resistance layer, electrons from the high resistance layer can be prevented from approaching the base region, and the current amplification factor can be increased. .

  Fourth, by providing a recombination suppression region or a low-resistance or high-resistance buried region at a required location as described above, the base resistance value can be reduced and variations can be suppressed, and the device characteristics of BJT can be made uniform. can do.

  According to the method for manufacturing a bipolar silicon carbide semiconductor device according to the present invention, the bipolar silicon carbide semiconductor device is provided with the layered recombination suppressing semiconductor region at a required location as described above. Recombination of holes flowing from the base can be suppressed, and a bipolar silicon carbide semiconductor device having a high current gain can be easily and reliably manufactured.

FIG. 3 is a partial longitudinal sectional view of a bipolar semiconductor device (BJT) according to a first embodiment of the present invention, and is an enlarged sectional view taken along line AA in FIG. 2. 1 is a plan view of a part of a bipolar semiconductor device according to a first embodiment. It is a fragmentary longitudinal cross-section explaining the problem of operation | movement of the conventional bipolar type semiconductor device. It is a fragmentary longitudinal cross-sectional view explaining the operation | movement of the bipolar type semiconductor device by 1st Example. 3 is a flowchart illustrating a method for manufacturing a bipolar semiconductor device according to the first embodiment. It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the bipolar type semiconductor device by 1st Example. It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the bipolar type semiconductor device by 1st Example. FIG. 5 is a partial longitudinal sectional view of a bipolar semiconductor device according to a second embodiment of the present invention. It is a fragmentary longitudinal cross-sectional view explaining operation | movement of the bipolar type semiconductor device of 2nd Example. It is a longitudinal cross-sectional view of the bipolar type semiconductor device by 3rd Example of this invention. It is a longitudinal cross-sectional view explaining the operation | movement of the bipolar type semiconductor device of 3rd Example. FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fourth embodiment of the present invention. FIG. 6 is a longitudinal sectional view of a bipolar semiconductor device according to a fifth embodiment of the present invention. It is the longitudinal cross-sectional view which showed the structure of the conventional bipolar type semiconductor device.

  Several preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<First embodiment>
A first embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. This bipolar semiconductor device shows an example of a conventional BJT having a general four-layer structure.

  As shown in FIG. 2, the BJT 10 includes, for example, five emitter electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device. These emitter electrodes 19 are surrounded by a base electrode 20.

In the longitudinal cross-sectional structure shown in FIG. 1, the BJT 10 has a collector region 11 formed of an n-type low-resistance layer (n ⁺ layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal. An emitter region 12 made of an n-type low resistance layer (n ⁺ layer) formed on the upper side surface portion is provided. A layer forming the collector region 11 is a substrate.

In the positional relationship of the plan view of FIG. 2, a base electrode 20 is formed around each of the plurality of emitter electrodes 19 so as to surround the emitter electrode 19. This means that the periphery of the emitter region 12 located below the emitter electrode 19 is surrounded by the p-type base contact region 13 located below the base electrode 20. The base contact region 13 is formed up to a predetermined depth position. Further, in the BJT 10, an n-type high resistance layer (n ⁻ layer) 14 and a p-type base region 15 are stacked from the lower side between the upper emitter region 12 and the lower collector region 11. Yes. The base region 15 is formed so as to be in contact with and electrically connected to the base contact region 13. In other words, the base contact region 13 is formed so as to be embedded at a predetermined position on the base region 15.

  In this embodiment, the “n-type” is a “first conductivity type”, and the “p-type” is a “second conductivity type”.

In the BJT 10 of this embodiment, the p ⁺ type base region 15 is further interposed between the p ⁺ type base contact region 13 formed on a part of the surface of the layered p type base region 15 and the emitter region 12. A layered recombination suppression region 16 is provided on the exposed surface portion so as to cover the surface portion. The depth of the recombination suppression region 16 is substantially equal to the depth of the base contact region 13. The recombination suppression region 16 is a high-resistance semiconductor and is “p ⁻ ” or “n ⁻ ”. The base contact region 13 is formed so as to come into contact with the surface of the base region 15 and further enter the inside of the base region 15 from the surface.

  In the structure of the BJT 10 described above, as shown in FIG. 1, the collector electrode 18 is bonded to the lower surface of the collector region 11, the emitter electrode 19 is bonded to the upper surface of the emitter region 12, and the base contact region 13 A base electrode 20 is joined to the upper surface. On the upper surface of the BJT 10, the exposed surface between the emitter electrode 19 and the base electrode 20 is covered with a surface protective film 17 and is protected thereby.

  As shown in FIG. 2, an upper layer electrode 21 is provided above each of the emitter electrode 19 and the base electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.

  In the BJT 10, the main current is an electron flow that flows from the emitter region 12 (or the emitter electrode 19) to the collector region 11 (or the collector electrode 18). The emitter region 12 and the collector region 11 are main electrode regions for flowing a main current. Energization (ON) and non-energization (OFF) of the main current are based on a base voltage applied to the base electrode 20, that is, a control signal applied between the base contact region 13 and the base region 15 and the emitter region 12. Be controlled. When the applied voltage between the base and the emitter is 0 V or less, the BJT 10 does not flow main current and is turned off. When a voltage of a certain level or higher is applied between the base and the emitter, the BJT 10 is turned on due to the main current flowing. In the ON state, the pn junction formed between the base region 15 and the emitter region 12 is forward-biased, and a hole current that is a control current flows from the base region 15 to the emitter region 12.

  The characteristic structure of the BJT 10 will be described with reference to FIGS. 3 and 4 while comparing the conventional BJT structure with the BJT structure of the present embodiment.

  FIG. 3 shows a BJT 10A having a conventional structure. In FIG. 3, the same elements as those described in FIG. In the structure of the BJT 10A, in the base region 15, a large number of recombination levels 22 are formed in the vicinity of the SiC surface between the base contact region 13 and the emitter region 12. Therefore, some of the electrons 23 of the main current I1 flowing from the emitter region 12 toward the collector region 11 and the holes 24 flowing from the base contact region 13 are recombined at the recombination level 22. Such recombination of electrons 23 and holes 24 occurs frequently at the interface between the base region 15 and the high resistance layer 14. As a result, an invalid base current that does not contribute to the operation of the BJT 10A flows, and the current amplification factor of the BJT 10A is reduced.

In contrast to the BJT 10A having the conventional structure, in the BJT 10 of the present embodiment, as shown in FIG. 4, a layer-like layer is formed on the surface of the base region 15 exposed between the base contact region 13 and the emitter region 12 and its vicinity. A coupling suppression region 16 is formed. The recombination suppression region 16 is formed of a “p ⁻ ” or “n ⁻ ” semiconductor region, and forms a high potential barrier with respect to the electrons 23 or the holes 24 and has a high resistance layer with a low hole or electron concentration. It has become. Due to the existence of the recombination suppression region 16, the holes 24 flowing from the base contact region 13 to the base region 15 do not easily flow into the recombination suppression region 16 in FIG. Electrons flowing from the region 12 are also difficult to flow near the SiC surface. As a result, as shown in FIG. 4, the electrons 23 flowing out from the emitter region 12 flow toward the collector region 11 as the main current I2 without recombining with the holes, thereby improving the current amplification factor of the BJT 10. Can do.

  When the recombination suppression region 16 is formed, an ion implantation method is used as in the case where the base contact region 13 is formed. In this case, the implantation concentration is extremely low and the energy required for ion implantation is low compared to the ion implantation for forming the base contact region 13. Therefore, in the ion implantation for forming the recombination suppression region 16, the density of recombination levels can be suppressed low.

  Here, a specific example of the impurity concentration and dimensions of each high resistance layer of the BJT 10 of the first embodiment will be described.

The BJT 10 is designed with a target of a blocking voltage of 600V, for example. As the substrate portion, a low resistance n-type 4H—SiC substrate which is turned off by 8 degrees from the (0001) plane is used. In the BJT 10, the substrate portion becomes the collector region 11. The n-type high resistance layer 14 on the substrate is a layer for blocking a high voltage applied between the emitter and the collector. In the present embodiment, the high resistance layer 14 is set to have a thickness of 10 μm and an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ , for example, so as to block a voltage of 600 V or higher. The p-type base region 15 on the high resistance layer 14 has a thickness and an impurity concentration so as not to be depleted when a high voltage is applied between the emitter and the collector. In the present embodiment, the p-type base region 15 has a thickness of 0.2 to 0.5 μm and an impurity concentration of about 4 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ . On the base region 15, a low-resistance n-type emitter region 12 having a thickness of 0.5 to 2.0 μm and an impurity concentration of 1 to 5 × 10 ¹⁹ cm ⁻³ is provided. A low-resistance base contact region 13 is formed around the emitter region 12. As shown in FIG. 2, the planar shape of the emitter region 12 is an elongated island shape. One BJT 10 includes a plurality of emitter regions 12. The dimensions of one emitter region 12 are about 3 to 10 μm in width and about 100 to 1000 μm in length. The period of the unit structure including the base contact region 13 and the emitter region 12 is about 10 to 30 μm.

  Next, the manufacturing method of BJT10 is demonstrated with reference to FIG. FIG. 5 is a flowchart showing each process of the manufacturing method. 6A and 6B are longitudinal sectional views showing structures manufactured by each process.

  The manufacturing method of the BJT 10 includes the following processes (1) to (10) (steps S11 to S20). As shown in FIG. 5, each process is executed in the order from step S11 to step S20.

(1) High resistance layer forming process (step S11)
(2) Base region formation process (step S12)
(3) Low resistance layer formation process (step S13)
(4) Emitter etching process (step S14)
(5) Recombination suppression region formation process (step S15)
(6) Base contact region formation process (step 16)
(7) Ion implantation layer activation process (step S17)
(8) Surface protective film formation process (step S18)
(9) Electrode formation process (step S19)
(10) Upper layer electrode formation process (step S20)

  By performing the above steps S11 to S13, the structure shown in FIG. 6A is formed.

In the n-type high resistance layer forming process (step S11), nitrogen having a thickness of 10 μm and a concentration of 1 × 10 ¹⁶ cm ⁻³ is doped as an impurity on the n-type substrate 40 made of SiC by an epitaxial growth method. A high resistance layer 41 is grown. As the substrate 40, “4H—SiC (0001) 8 ° off” is used. The substrate 40 becomes the collector region 11 of the n-type low resistance layer described above.

In the base region formation process (step S12), aluminum (Al) is used as an impurity on the n-type high resistance layer 41 by an epitaxial growth method at a concentration of 4 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ^−3. A 0.5 μm p-type base region 42 is grown.

In the low resistance layer formation process (step S13), nitrogen having a thickness of 0.5 to 2.0 μm and a concentration of 1 to 5 × 10 ¹⁹ cm ⁻³ is formed on the n-type base region 42 by an epitaxial growth method as an impurity. A doped n-type low resistance layer 43 is grown. The low resistance layer 43 is a portion for forming the emitter region 12 described above.

In the next emitter etching process (step S14), in the structure shown in FIG. 6A (a), a silicon oxide film 51 is deposited on the upper surface by CVD, photolithography is performed, and then silicon oxide is formed by RIE. The film 51 is etched. Thus, a mask is formed. Then, using this silicon oxide film 51, SiC etching is performed on the low resistance layer 43 by RIE, and the emitter region 12 is formed using the low resistance layer 43. SF ₆ gas or the like is used for RIE of SiC etching. The resulting structure is shown in FIG. 6A (b).

In the process of forming the recombination suppression region (step S15), as shown in FIG. 6A (c), the recombination suppression region 16 is formed using the mask 51 shown in FIG. 6A (b) as it is. . The recombination suppression region 16 is formed by performing ion implantation of nitrogen as an impurity (ion species). Ions are implanted into all regions etched by the emitter etching process (step S15). In order to set the characteristics of the recombination suppression region to “p ⁻ ” or [n ⁻ ] having a high resistivity, the ion implantation amount is set to a value approximately equal to or before and after the impurity concentration of the base region 42. For example, if the impurity concentration of the base region 42 is 4 × 10 ¹⁷ cm ⁻³ , the ion implantation amount is desirably about ^{3 to} 5 × 10 ¹⁷ cm ⁻³ . Further, since the recombination suppression region 16 only needs to include a recombination level in the vicinity of the surface, its depth may be about 0.1 to 0.2 μm. Therefore, the implantation energy can be suppressed to as low as about 100 keV, and the generation of crystal defects in the ion implantation process can be suppressed.

In the base contact region forming process (step S16), first, as shown in FIG. 6A (d), a mask 52 is formed so that the surface portion for forming the base contact region 13 is exposed. The mask 52 is formed by depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, ion implantation is performed to form the base contact region 13. The implanted ions are aluminum (Al), and the depth of implantation is, for example, 0.2 μm. The ion implantation amount is 1 × 10 ¹⁸ to 10 ²⁰ cm ⁻³ , and the energy required for ion implantation is approximately 200 KeV.

  By the above steps S15 and S16, the recombination suppression region 16 is formed on the surface of the base region 15 between the base contact region 13 and the emitter region 12. The purpose of providing the recombination suppression region 16 is to keep electrons coming from the emitter region 12 away from the SiC surface of the recombination suppression region 16.

  Next, in the process of activating the ion implantation layer (step S17), after the ion implantation, the implanted ions are electrically activated in the semiconductor, and a heat treatment is performed to eliminate crystal defects generated by the ion implantation ( FIG. 6B (e)). In this activation heat treatment, both the implanted ions in the base contact region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time. Heat treatment is performed for about 10 minutes at a high temperature of about 1700 to 1800 ° C. using a high-frequency heat treatment furnace or the like. For example, argon gas (Ar) is used as the atmospheric gas.

In the process of forming the surface protective film (step S18), as shown in FIG. 6B (f), first, in order to remove the surface layer generated in the ion implantation process and the activation process, the oxide film is removed after the thermal oxidation. Perform sacrificial oxidation. The oxidation condition is, for example, 1100 ° C. for 20 hours in dry oxygen. Hydrofluoric acid is used to remove the oxide film. After the sacrificial oxidation, thermal oxidation is performed again to form an oxide film 53. In the formation of the thermal oxide film, for example, the temperature is 1100 ° C., the time is 5 hours, and the atmosphere is wet. Thereafter, heat treatment (POA: Post Oxidation Anneal) is performed to reduce the impurity level at the interface of the SiC oxide film. POA is performed in a hydrogen, nitric oxide (NO, N ₂ O) or argon atmosphere at a high temperature of about 800 to 1300 ° C. for about 10 to 30 minutes. After POA, a CVD oxide film or a CVD nitride film is formed.

  In the process of forming electrodes (step S19), the emitter electrode 19, the base electrode 20, and the collector electrode 18 are formed on the surfaces of the emitter region 12 (low resistance layer 43), the base contact region 13, and the collector region 11 (substrate 40), respectively. It forms (FIG. 6B (g)). The remaining oxide film 53 becomes the surface protective film 17 described above. The emitter electrode 19 and the collector electrode 18 are made of nickel or titanium, and the base electrode 20 is made of titanium or aluminum. Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used.

  After the electrodes 18 to 20 are formed, heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion. The heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.

  Finally, an upper layer electrode formation process (step S20) is performed. In this upper layer electrode formation step (step S20), an upper layer electrode 54 for taking out a plurality of separated emitter electrodes 19 as one electrode is formed (FIG. 6B (h)). After the silicon oxide film or the like is formed as the interlayer film 55 by the CVD method, the silicon oxide film or the like in the emitter electrode 19 is removed by photolithography and etching. After exposing the emitter electrode 19 in this way, the upper layer electrode 54 is deposited. For example, aluminum (Al) is used as the material of the upper electrode 54.

  In this way, the BJT 10 shown in FIGS. 1 and 2 is manufactured. The BJT 10 is a high-performance semiconductor device having normally-off characteristics.

  In the first embodiment, the combinations of the first and second conductivity types such as the collector region, the emitter region, the high resistance layer, the base region, the base contact region, and the recombination suppression region can be reversed. . This also applies to the other embodiments described below.

<Second embodiment>
A second embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. The bipolar semiconductor device of the second embodiment is also BJT. In FIG. 7, elements that are substantially the same as those described in FIG. 1 are given the same reference numerals.

  As shown in FIG. 3, in the conventional structure BJT 10A, the emitter region 12 is etched until the surface of the base region 15 is exposed. Thus, since a part of the base region 15 must be etched due to the limit of the accuracy of the etching process, the thickness of the base layer is reduced, and as a result, the resistance value of the base is increased. In addition, the base resistance value varies between wafers or between wafers due to variations in etching depth within a wafer or between wafers. Further, in order to improve the current amplification factor of the BJT, it is desirable to make the base layer thinner. However, if the base layer is made thinner, the increase in base resistance and the variation in value due to the etching process become more remarkable.

Therefore, in the BJT 100 according to the second embodiment, a p-type semiconductor having a resistivity equal to or lower than that of the base region in a region corresponding to the region of the base surface exposed by etching in the base region 15 formed in a layer shape ( A low-resistance buried region 61 made of p ⁺ or p ⁻ ) is provided. In this embodiment, the surface recombination suppression region 16 is not formed as in the first embodiment. Other structures are the same as those of the first embodiment.

  According to the above structure, the hole current flowing from the base contact region 13 to the base region 15 flows near the surface in the conventional example shown in FIG. 3, whereas the resistance value as shown in FIG. It flows to the lower low resistance buried region 61. Therefore, recombination near the surface of base region 15 is reduced, and the current amplification factor is improved.

  Since the low resistance buried region 61 has a lower resistance value than the base region 15, the resistance of the base region 15 is determined by the resistance value of the low resistance buried region 61. As a result, it is possible to increase the resistance and variation of the base region 15 caused by the etching.

The impurity concentration of the p-type base region 15 is 4 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ^{−3 as} described above, whereas the impurity concentration of the low-resistance buried region 61 is about the same or higher than that of the base region 15. And For example, when the impurity concentration of the p-type base region 15 is, for example, 4 × 10 ¹⁷ cm ⁻³ , the impurity concentration of the low-resistance buried region 61 is 2 × 10 ¹⁸ cm ⁻³ and the thickness is based on If the thickness of the region 61 is the same, the resistivity of the low-resistance buried region 61 can be reduced to 1/3 of the resistivity of the base region 15.

  Regarding the method for manufacturing the BJT 100 according to the second embodiment, the low-resistance buried region 61 can be formed by applying a multi-stage ion implantation method in the method for manufacturing the BJT 10 according to the first embodiment described above.

<Third embodiment>
A third embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIGS. The bipolar semiconductor device of the third embodiment is also a BJT. 9, elements that are substantially the same as the elements described in FIG.

  As described with reference to FIG. 3, the BJT 10A having the conventional structure has a characteristic that the holes flowing through the base region 15 and the electrons flowing through the collector region 11 recombine near the base-collector interface.

Therefore, in the BJT 200 of the third embodiment, the base region 15 is a region corresponding to the region of the base surface exposed by the etching described above on the lower side (on the high resistance layer 14 side) of the base region 15 formed in layers. A high resistance buried region made of a p-type semiconductor (p ⁻ ) having a higher resistance than that of the base region 15 or a high resistance buried region 63 made of an n-type semiconductor (n ⁻ ) having a higher resistance than that of the high resistance layer 14. Is provided. In this embodiment, the recombination suppression region 16 on the base surface is not formed as in the first embodiment. Other structures are the same as those of the first embodiment.

In the structure of the BJT 200 of the third embodiment, by providing the high-resistance buried region 63, in the case of the p ⁻ layer, a potential (partially between the high-resistance buried region 63 and the high-resistance layer 14 exists in the presence thereof. Potential difference) is formed, and the electrons of the high resistance layer 14 are moved away from the base region 15. The hole concentration in the high resistance buried region 63 is lower than the hole concentration in the base region 15. For this reason, the electron / hole concentration in the high resistance buried region / high resistance layer in the third embodiment is lower than that in the base region / high resistance layer vicinity in the BJT 10A having the conventional structure. Therefore, recombination can be reduced, thereby improving the current amplification factor. Even in the case of the n ⁻ layer, recombination can be suppressed by substantially the same principle, and the current amplification factor can be improved.

The impurity concentration of the p-type base region 15 is 4 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ^{−3 as} described above, whereas the impurity concentration of the high-resistance buried region 63 is the same as or less than that of the base region 15. And For example, when the impurity concentration of the p-type base region 15 is, for example, 4 × 10 ¹⁷ cm ⁻³ , the impurity concentration of the high-resistance buried region 63 is set to 1 × 10 ¹⁷ cm ⁻³ or less.

<Fourth embodiment>
A bipolar semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. 11, elements that are substantially the same as those described in FIGS. 7 and 9 are denoted by the same reference numerals.

  The BJT 300 of the fourth embodiment is configured by combining the characteristic structures of the second and third embodiments. In the fourth embodiment, the high resistance buried region 63 is formed so as to be in contact with the lower surface of the low resistance buried region 61. Other configurations are the same as those of the second or third embodiment. The same effect as described above is also exhibited by the BJT 300 of the present embodiment.

<Fifth embodiment>
A fifth embodiment of a bipolar semiconductor device according to the present invention will be described with reference to FIG. 12, elements that are substantially the same as those described in FIGS. 1, 7, and 9 are denoted by the same reference numerals.

  The BJT 400 of the fifth embodiment is configured by combining the characteristic structures of the first, second, and third embodiments. In the fifth embodiment, a recombination suppression region 16, a low-resistance buried region 61, and a high-resistance buried region 63 formed so as to be in contact with the lower surface of the low-resistance buried region 61 are provided. Other configurations are the same as those of the first, second, or third embodiment. The same effect as described above is also exhibited by the BJT 400 of the present embodiment.

  In this embodiment, a reverse polarity type in which the polarities of p and n in the description of the steps of the manufacturing method are reversed may be used. Furthermore, in this embodiment, an example of SiC has been described, but the present invention can also be applied to other semiconductors in which surface recombination is a problem.

  The configurations, shapes, sizes, and arrangement relationships described in each of the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented, and numerical values and compositions (materials) of the respective components. Is merely an example. Therefore, the present invention is not limited to the described embodiments, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.

  The present invention relates to a conventional general bipolar silicon carbide semiconductor device having a four-layer structure, which suppresses recombination of electrons of a main current with holes of a control current and improves a current amplification factor, and Even if the base layer is thinned, it is used for improving an increase or variation in the base resistance value, and further used for a method of manufacturing a bipolar silicon carbide semiconductor device having such characteristics.

10 Bipolar semiconductor devices (BJT)
DESCRIPTION OF SYMBOLS 11 Collector area | region 12 Emitter area | region 13 Base contact area | region 14 High resistance layer 15 Base area | region 16 Recombination suppression area | region 17 Surface protective film 18 Collector electrode 19 Emitter electrode 20 Base electrode 21 Upper layer electrode 40 Substrate 41 High resistance layer 42 Base area 43 Low resistance Layer 61 Low resistance buried region 63 High resistance buried region 100 BJT
200 BJT
300 BJT
400 BJT

Claims (12)

A collector region of one conductivity type of the first conductivity type or the second conductivity type, which is a substrate made of a silicon carbide semiconductor crystal;
A high resistance layer of the one conductivity type higher than the resistivity of the collector region formed on the collector region ;
A base region of the other conductivity type of the first conductivity type or the second conductivity type formed on the high resistance layer;
An emitter region of the one conductivity type , which comprises a low resistance layer lower than the resistivity of the high resistance layer, is joined to the base region, and is formed on the base region ;
A base contact region of the other conductivity type formed around the emitter region in a plan view and formed on the base region so as to be joined to the base region in a cross-sectional view, the resistance of the base region said base contact region of the lower resistance lower than the rate,
Formed on the side of the base region so as to include a surface which is a boundary between the base region and the surface protection film positioned between the base contact region and the emitter region, and the first conductivity type or the second type high recombination-inhibiting region than the resistivity of it and the base region a conductivity type,
Equipped with a,
In cross section, the depth of the recombination-inhibiting region, the base contact same der Ru bipolar and depth of the region silicon carbide semiconductor device. By performing ion implantation on a part of the provisional recombination suppression region formed in advance, the base contact region and the final recombination are respectively applied to the part and the rest of the provisional recombination suppression region. bipolar silicon carbide semiconductor device according to claim 1, debonding region Ru is formed. A collector region of one conductivity type of the first conductivity type or the second conductivity type, which is a substrate made of a silicon carbide semiconductor crystal;
A high resistance layer of the one conductivity type higher than the resistivity of the collector region formed on the collector region ;
A base region of the other conductivity type of the first conductivity type or the second conductivity type formed on the high resistance layer;
An emitter region of the one conductivity type , which comprises a low resistance layer lower than the resistivity of the high resistance layer, is joined to the base region, and is formed on the base region ;
A base contact region of the other conductivity type formed around the emitter region in a plan view and formed on the base region so as to be joined to the base region in a cross-sectional view, the resistance of the base region said base contact region of the lower resistance lower than the rate,
Said base region and is formed on the high resistance layer, the contact with the upper surface in cross section to the base contact region, said a first conductivity type or the second conductivity type electrically and by the resistivity of the base region remote A low buried region , the buried region having the top surface ;
Equipped with a,
In cross section, the thickness of the buried region, said base region to be the same as the thickness of the bipolar type silicon carbide semiconductor device. The bipolar silicon carbide semiconductor device according to claim 3 , wherein a resistivity of the buried region is 1/3 of the resistivity of the base region . A collector region of one conductivity type of the first conductivity type or the second conductivity type, which is a substrate made of a silicon carbide semiconductor crystal;
A high resistance layer of the one conductivity type higher than the resistivity of the collector region formed on the collector region ;
A base region of the other conductivity type of the first conductivity type or the second conductivity type formed on the high resistance layer;
An emitter region of the one conductivity type , which comprises a low resistance layer lower than the resistivity of the high resistance layer, is joined to the base region, and is formed on the base region ;
A base contact region of the other conductivity type formed around the emitter region in a plan view and formed on the base region so as to be joined to the base region in a cross-sectional view, the resistance of the base region said base contact region of the lower resistance lower than the rate,
Formed only in the high-resistance layer, is in contact with the base region at a first upper surface in a sectional view , and is embedded in the first conductivity type or the second conductivity type and higher in resistivity than the base region A region of the high buried region having the first top surface ;
A bipolar silicon carbide semiconductor device comprising: Formed only in the base region, and is in contact with the base contact region and the high buried region at the second upper surface and the lower surface in a sectional view, respectively, and is of the first conductivity type or the second conductivity type; wherein a lower embedding region than the resistivity of the base region, the bipolar-type silicon carbide semiconductor device according to claim 5 that further having a said buried region having said bottom surface and said first top surface. A high conductivity of the one conductivity type higher than the resistivity of the collector region on a substrate made of a semiconductor crystal of silicon carbide and serving as a collector region of one conductivity type of the first conductivity type or the second conductivity type A first step of forming a resistive layer;
A second step of forming a base region of the other conductivity type of the first conductivity type or the second conductivity type on the high resistance layer;
A third step for forming a low-resistance layer of the one conductivity type lower than the resistivity of the high-resistance layer on the base region;
A fourth step of partially etching the low resistance layer to form an emitter region of the one conductivity type ;
A fifth step of forming, in the vicinity of the surface of the base region exposed by etching, a recombination suppression region of the first conductivity type or the second conductivity type and higher in resistivity than the base region ;
A base contact region of the other conductivity type formed on the base region so as to be joined to the base region in a cross-sectional view, wherein a base contact region having a lower resistivity than the base region is formed. And the process of
Only including,
The method of manufacturing a bipolar silicon carbide semiconductor device , wherein the depth of the recombination suppression region is the same as the depth of the base contact region in a cross-sectional view . Forming a collector electrode, an emitter electrode, and a base electrode in each of the collector region, the emitter region, and the base contact region;
Forming an upper layer electrode above the emitter electrode and the base electrode;
The method for manufacturing a bipolar silicon carbide semiconductor device according to claim 7, further comprising: A high conductivity of the one conductivity type higher than the resistivity of the collector region on a substrate made of a semiconductor crystal of silicon carbide and serving as a collector region of one conductivity type of the first conductivity type or the second conductivity type A first step of forming a resistive layer;
A second step of forming a base region of the other conductivity type of the first conductivity type or the second conductivity type on the high resistance layer;
A third step for forming a low-resistance layer of the one conductivity type lower than the resistivity of the high-resistance layer on the base region;
A fourth step of partially etching the low resistance layer to form an emitter region of the one conductivity type ;
Wherein in contact with the base contact region of the other conductivity type formed thereafter, the base region and the high resistance layer, wherein a first conductivity type or the second conductivity type conductive and the resistance of the base region a fifth step of forming the rate by remote low buried region,
A sixth step of forming a base contact region joined to the base region;
Only including,
A method of manufacturing a bipolar silicon carbide semiconductor device , wherein the thickness of the buried region is the same as the thickness of the base region in a cross-sectional view . Forming a collector electrode, an emitter electrode, and a base electrode in each of the collector region, the emitter region, and the base contact region;
Forming an upper layer electrode above the emitter electrode and the base electrode;
The method for manufacturing a bipolar silicon carbide semiconductor device according to claim 9, further comprising: A high conductivity of the one conductivity type higher than the resistivity of the collector region on a substrate made of a semiconductor crystal of silicon carbide and serving as a collector region of one conductivity type of the first conductivity type or the second conductivity type A first step of forming a resistive layer;
A second step of forming a base region of the other conductivity type of the first conductivity type or the second conductivity type on the high resistance layer;
A third step for forming a low-resistance layer of the one conductivity type lower than the resistivity of the high-resistance layer on the base region;
A fourth step of partially etching the low resistance layer to form an emitter region of the one conductivity type ;
In contact with the upper surface before Symbol base region, only the high-resistance layer, the first conductive type or said a second conductivity type and a higher embedding area than the resistivity of said base layer, said A fifth step of forming the high buried region having an upper surface ;
A sixth step of forming the base contact region of the other conductivity type joined to the base region;
A method for manufacturing a bipolar silicon carbide semiconductor device, comprising: Forming a collector electrode, an emitter electrode, and a base electrode in each of the collector region, the emitter region, and the base contact region;
Forming an upper layer electrode above the emitter electrode and the base electrode;
The method for manufacturing a bipolar silicon carbide semiconductor device according to claim 11, further comprising:

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