JP2002359378A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a deep expansion type diffusion area at low cost without increasing the number of processes as much as possible. SOLUTION: On the surface of an n-type epitaxial growth layer 12, a mask 13M for ion implantation is formed. The mask 13M for ion implantation is sued to perform the selective ion implantation of boron (<11> B<+> ) deep into the n-type epitaxial growth layer 12. Further, the mask 13M for ion implantation is used to carry out the selective ion implantation of aluminum (<27> Al<+> ) from the surface of the n-type epitaxial growth layer 12 shallower than the boron. Then p-type deep expansion diffusion areas 15a and 15b are formed by activating heat-treatment. The diffusion areas 15a and 15b increase in lateral diffusion width perpendicular to the depth toward an ohmic contact area 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a wide band gap semiconductor (wide gap semiconductor) material having a high breakdown voltage and low current loss.

[0002]

BACKGROUND OF THE INVENTION Researched early in the semiconductor industry,
Silicon for practical use (forbidden band width Eg = about 1.1 eV)
As compared with a semiconductor material having a normal forbidden bandwidth Eg such as GaAs or gallium arsenide (forbidden bandwidth Eg = about 1.4 eV), a semiconductor material having a wide forbidden bandwidth Eg is referred to as a wide forbidden bandwidth semiconductor (wide gap semiconductor). Call. For example, the forbidden band width Eg = about 2.2
eV zinc telluride (ZnTe), bandgap Eg = about 2.4 eV cadmium sulfide (CdS), bandgap Eg
= About 2.7 eV zinc selenide (ZnSe), band gap Eg = gallium nitride (GaN) with about 3.4 eV, band gap Eg = zinc sulfide (ZnS) with about 3.7 eV, and band gap Eg = About 5.5 eV diamond can be cited as a wide gap semiconductor. Also, silicon carbide (SiC)
Is also an example of a wide gap semiconductor. The forbidden band width Eg of SiC is 2.23 eV in 3C-SiC, 6H-Si
A value of about 2.93 eV for C and about 3.26 eV for 4H-SiC has been reported.

[0003] Wide gap semiconductors are generally thermally, chemically and mechanically stable and have excellent radiation resistance. In particular, SiC is excellent in these characteristics, and is a power semiconductor device (power device) that exhibits high reliability and stability under severe conditions such as high temperature, high power, and radiation irradiation as well as light emitting elements and high frequency devices. It is expected to be applied in various industrial fields.

In such a wide-gap semiconductor, as the forbidden band width Eg becomes wider, the property as an insulator becomes closer, so that it becomes difficult to obtain a low resistivity by doping impurities. In general, it is currently difficult to obtain a “good conductive” material with high reproducibility and reliability in a wide gap semiconductor. For example, as a material for a blue light emitting diode, GaN which is a III-V group semiconductor having a wurtzite structure, ZnSe of a II-VI group and the like have been vigorously studied as promising materials from an early stage.
The research task was to achieve control of p-type conductivity. The difficulty in controlling p-type valence electrons in wide-gap semiconductors has been attributed to the self-compensation effect. In the case of introducing a donor impurity into ZnSe, for example, when a donor impurity is introduced, Zn vacancies acting as double acceptors are naturally formed, and electrons in a conduction band formed by the introduction of the donor impurity are spontaneously compensated. It is a phenomenon of doing. For this to happen,
It is sufficient that the enthalpy of formation of Zn vacancies ΔHv (Zn) is smaller than the total energy ΔE released when two electrons fall into the acceptor, ΔEv. Now, ignoring the binding energy of carriers to donors and Zn vacancies,
ΔE is approximately twice the forbidden band width Eg. For this reason,
It is considered that the self-compensation effect occurs more remarkably in a semiconductor having a wider gap (forbidden band width Eg). Because of this,
Achieving p-type conduction in wide gap semiconductor materials has been considered to be inherently difficult. On the other hand, such a problem is not a problem at all in a semiconductor material such as Si having a forbidden band width of about 1.1 eV or GaAs having a forbidden band width of about 1.4 eV. Therefore, Si,
Semiconductor materials such as GaAs have been put to practical use as materials for various semiconductor devices.

In particular, it has been reported that a power semiconductor device (power device) having a high withstand voltage using SiC has a lower on-resistance than a power device using Si. or,
It has been reported that the forward drop voltage of a Schottky diode using SiC is reduced. As is well known, there is a trade-off between the on-resistance and the switching speed of a power device. However, according to a power device using SiC, there is a possibility that low on-resistance and high switching speed can be simultaneously achieved.

[0006]

However, the diffusion coefficient of impurities into SiC is very small, about one thousandth of that of impurities in Si. For this reason, it is difficult to simply design the p ⁺ region to have a desired impurity concentration and a desired geometric shape by using the ion implantation technique as well as the predeposition (gas phase diffusion) technique.

One of the semiconductor power devices is a junction barrier Schottky diode (hereinafter referred to as “J”).
BS diode ". ). This JBS diode has a structure in which a plurality of p ⁺ regions are buried under a Schottky electrode in a normal n-type Schottky diode. The feature of the JBS diode is that the depletion layer extends from each p ⁺ region in the reverse characteristics and pinches off, thereby alleviating the electric field applied to the Schottky interface and suppressing the reverse leakage current. On the other hand, in the forward characteristics, a plurality of p ⁺ regions are buried under the Schottky electrode, so that the region through which carriers pass is effectively reduced, resulting in an increase in forward resistance. There is.

Therefore, there is a need for a new structure that does not impair reverse characteristics such as withstand voltage and leakage current and that sufficiently reduces forward resistance. However, in SiC, as described above, since a process technology, particularly a diffusion technology has not been developed, it is not easy to realize a desired structure of the JBS diode. Therefore, SiC
At present, there is a strong demand for a JBS diode using the above-mentioned structure that satisfies the above-mentioned requirements without increasing the number of steps if possible and at a low manufacturing cost.

The problem of the JBS diode using SiC described above is common to the problem relating to the shape of the gate region of an electrostatic induction transistor (SIT) which is another semiconductor power device. SIT has embedded gate type,
Various structures such as a surface gate type and a cut gate type are known. Among them, in the surface gate type SIT, a pair of gate regions are formed so as to face each other with the source region interposed therebetween on the substrate surface. A region sandwiched between the pair of gate regions is a channel region. The main current flowing between the source region and the drain region is electrostatically controlled by the voltage applied to the gate region to the height of the potential barrier formed in the channel region in front of the source region. In this surface gate type SIT, as in the case of the JBS diode described above, a structure for improving characteristics is being studied. By adopting a new structure, the depletion layer can be effectively extended in the drift region with a smaller gate voltage to make it easier to obtain normally-off characteristics, and the forward resistance between the source and drain is sufficiently reduced. The structure which can do is expected. However, even in a surface gate type SIT using SiC, the number of steps is not increased and the manufacturing cost is low.
At present, a technique for realizing a desired device structure has not been found sufficiently.

[0010] In view of the above problems, the present invention provides a high withstand voltage,
An object of the present invention is to provide a semiconductor device having a small reverse leakage current and a small forward voltage drop, and a method for manufacturing the same.

[0011]

SUMMARY OF THE INVENTION In view of the above-mentioned object, a first feature of the present invention is that an ohmic contact region of the first conductivity type and a wide band gap material provided on the ohmic contact region are provided. A drift region of one conductivity type, a plurality of deep-expansion diffusion regions of a second conductivity type provided inside the drift region, and a Schottky junction with a drift region provided in contact with the surface of the drift region. The gist is that the semiconductor device includes electrodes. The plurality of deep-diffusion regions of the second conductivity type are JB
It constitutes the structure of the S diode. That is, by providing a plurality of the second-conductivity-type deep-expansion diffusion regions, a depletion layer is formed from each of the deep-expansion diffusion regions in reverse characteristics.
The electric field applied to the Schottky interface is reduced by extending into the drift region and pinching off each other. For this reason, the leakage current in the reverse direction can be suppressed. still,
The same applies to the following second to fifth features, but in the present invention, the “wide bandgap material” means a semiconductor material having a wider bandgap than 2.2 eV. The drift region has a lower impurity concentration than the ohmic contact region. Each of the deep-expansion diffusion regions has a horizontal sectional area gradually increasing from the surface of the drift region toward the ohmic contact region. For example, it has a trapezoidal cone shape or a mirror cake shape. The deep expansion diffusion region has a top exposed at the surface of the drift region. The first conductivity type and the second conductivity type are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type.

According to the first feature of the present invention, the horizontal cross-sectional area of the deep expansion type diffusion region is increased as the depth increases in the drift region. The forward resistance can be sufficiently reduced without impairing the reverse characteristics.

[0013] In the first aspect of the present invention, each of the plurality of deeply inflatable diffusion regions preferably includes an upper region and a lower region located below the upper region. The upper region contains a first impurity element. On the other hand, the lower area
A second impurity element having a larger diffusion coefficient in the wide bandgap material than the first impurity element is included.

A second feature of the present invention is that a first main electrode region,
A first conductivity type drift region made of a wide bandgap material provided above the first main electrode region, a plurality of second conductivity type deep expansion diffusion regions provided inside the drift region; The gist of the present invention is a semiconductor device including a first conductivity type second main electrode region provided inside a drift region sandwiched between a plurality of deep expansion diffusion regions.
As in the first aspect of the present invention, each of the deep expansion diffusion regions has a horizontal cross-sectional area gradually increasing from the surface of the drift region toward the first main electrode region.
It has a dimensional shape. Each of the deep expansion diffusion regions functions as a control electrode region for controlling a current flowing between the first and second main electrode regions. The “first main electrode region” means a semiconductor region that becomes either the emitter region or the collector region in a bipolar transistor (BJT) or an insulated gate bipolar transistor (IGBT). In a field-effect transistor (FET) or a static induction transistor (SIT), it means a semiconductor region that becomes one of a source region and a drain region. In the case of an electrostatic induction thyristor (SI thyristor) or a gate turn-off thyristor (GTO thyristor), it means a semiconductor region which is one of an anode region and a cathode region. The “second main electrode region” refers to BJT, IG
In a BT or the like, a semiconductor region that becomes either the emitter region or the collector region that does not become the first main electrode region, and in a FET or SIT, one of a source region and a drain region that does not become the first main electrode region Means a semiconductor region to be formed. SI thyristor, G
In the TO thyristor, the “second main electrode region” is the first main electrode region.
It means a semiconductor region that becomes either an anode region or a cathode region that is not a main electrode region. That is, if the first main electrode region is an emitter region, the second main electrode region is a collector region. If the first main electrode region is a source region, the second main electrode region is a drain region. 1
If the main electrode region is a cathode region, the second main electrode region means an anode region. The “control electrode region” means a semiconductor region, a Schottky junction region, an insulated gate structure region or a structure for controlling a current flowing between the first main electrode region and the second main electrode region. For example, IGBT, F
In ET, SIT, SI thyristor and GTO thyristor, it means a gate region or a gate structure, and BJT
Means a base region including an external base region (base electrode extraction region).

The first conductivity type and the second conductivity type are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. The first main electrode region may be of the first conductivity type or the second conductivity type. The drift region has a lower impurity concentration than the first main electrode region. The deep expansion type diffusion region and the second main electrode region are arranged such that the top is exposed on the surface of the drift region.

According to a second feature of the present invention, the width of the deep-expansion diffusion region, that is, the cross-sectional area in the horizontal direction in three dimensions, is
In the drift region, the resistance gradually increases as the depth increases, so that the forward resistance can be sufficiently reduced without impairing the breakdown voltage characteristics of the control electrode region of the semiconductor device.

In the second aspect of the present invention, a base region of the second conductivity type may be further provided between the plurality of deeply inflated diffusion regions. If the impurity concentration of the base region of the second conductivity type is reduced, the punch-through between the first and second main electrode regions is almost complete. It functions as a bipolar mode SIT (BSIT) or a normally-off SI thyristor. On the other hand, if the impurity concentration of the second conductivity type base region is set high so that a neutral region remains between the first and second main electrode regions, it functions as a BJT or GTO thyristor.

According to a second feature of the present invention, each of the plurality of deep expansion diffusion regions is located at an upper region containing a first impurity element and at a lower portion of the upper region.
And a lower region containing a second impurity element having a larger diffusion coefficient in the wide bandgap material than the impurity element.

A third feature of the present invention is that a first main electrode region of the first conductivity type or the second conductivity type is provided above the first main electrode region and lower than the first main electrode region. A first conductivity type drift region made of a wide bandgap material with an impurity concentration, a plurality of second conductivity type body regions disposed on the surface of the drift region, and a second conduction type body region disposed on the surface of the body region; A second main electrode region of one conductivity type; a plurality of trenches dug from the surface of the second main electrode region toward the first main electrode region; and a gate insulating layer formed on inner walls of the plurality of trenches A film, inside the plurality of trenches, a gate electrode disposed on the surface of the gate insulating film, and provided inside the drift region below the plurality of trenches,
A semiconductor including a plurality of second-conductivity-type deep-expansion diffusion regions each having a horizontal cross-sectional area gradually increasing from a bottom of the trench toward the first main electrode region region and functioning as an electric field relaxation region; It is assumed that the device is a gist. Here, the “first main electrode region” means a semiconductor region that becomes either the emitter region or the collector region in an insulated gate bipolar transistor (IGBT). Insulated gate type FET and insulated gate type SI
T means a semiconductor region to be either a source region or a drain region. The “second main electrode region” is a semiconductor region that becomes either the emitter region or the collector region that does not become the first main electrode region in an IGBT or the like, an insulated gate FET, an insulated gate SI.
T means a semiconductor region that becomes either the source region or the drain region that is not the first main electrode region.

According to the third feature of the present invention, the deep expansion type diffusion region greatly reduces the electric field intensity of the gate insulating film near the bottom of the trench, thereby realizing an insulated gate semiconductor device having a higher breakdown voltage. I can do it. This is because the deep expansion diffusion region equally shares the voltage applied to the gate insulating film. As a result, the reliability of the insulated gate semiconductor device is also improved.

According to a third feature of the present invention, each of the plurality of deep-expansion diffusion regions is located at an upper region containing a first impurity element and at a lower portion of the upper region.
It is the same as the first and second features that the lower region including the second impurity element having a larger diffusion coefficient in the wide bandgap material than the impurity element described above may be included.

A fourth feature of the present invention is that a drift region of a first conductivity type made of a wide bandgap material, a plurality of body regions of a second conductivity type disposed on the surface of the drift region,
A first main electrode region of a first conductivity type or a second conductivity type disposed on the surface of the drift region at a higher impurity concentration than the drift region and separated from the body region; and disposed on the surface of the body region. A second main electrode region of a first conductivity type;
A plurality of trenches penetrating from the surface of the second main electrode region to the drift region through the body region, a gate insulating film formed on inner walls of the plurality of trenches, and a surface of the gate insulating film inside the plurality of trenches And a horizontal cross-sectional area is gradually increased from the bottom of the trench toward the direction away from the body region. The gist of the present invention is to provide a semiconductor device including a plurality of second conductivity type deep expansion diffusion regions functioning as a relaxation region. Here, the “first main electrode region”
Is an insulated gate bipolar transistor (IGB
T) means a semiconductor region that becomes either the emitter region or the collector region, and is an insulated gate FE.
In the case of T or an insulated gate SIT, the meaning of a semiconductor region which is either a source region or a drain region is the same as the third feature. Therefore, the “second main electrode region” is a semiconductor region that becomes either the emitter region or the collector region that is not the first main electrode region in an IGBT or the like, an insulated gate FET, or an insulated gate SIT. It means a semiconductor region that becomes either the source region or the drain region that is not the first main electrode region.

According to the fourth aspect of the present invention, similarly to the third aspect, the deep expansion diffusion region greatly reduces the electric field intensity of the gate insulating film near the bottom of the trench, and provides a higher breakdown voltage. A horizontal insulated gate semiconductor device can be realized. This is because the deep expansion diffusion region equally shares the voltage applied to the gate insulating film. As a result, the reliability of the lateral insulated gate semiconductor device is also improved. Further, in the lateral insulated gate semiconductor device according to the fourth aspect of the present invention, the first and second main electrode regions are provided on the same side surface, so that they can be easily integrated as a monolithic IC. It is. In addition, the wiring work is simplified even when used in a hybrid IC or the like. In addition, the degree of freedom of surface wiring and connection is increased, and the design becomes easy.

According to a fourth feature of the present invention, each of the plurality of deep expansion diffusion regions is located at an upper region containing a first impurity element and at a lower portion of the upper region.
This is the same as the first to third features in that the lower region including the second impurity element having a larger diffusion coefficient in the wide bandgap material than the impurity element described above may be included.

A fifth feature of the present invention is that (a) a step of forming an ion implantation mask on the surface of a semiconductor region of the first conductivity type made of a wide band gap material; Using the first conductive type in the semiconductor region.
A deep ion implantation step of implanting impurity ions a plurality of times while changing the acceleration energy; (c) using a mask for ion implantation, forming second impurity ions having a smaller diffusion coefficient in the semiconductor region than the first impurity ions into the first impurity ions; A shallow ion implantation step of implanting a plurality of times at a position shallower than the projection range of the impurity ions while changing the acceleration energy, and (d) a heat treatment step, thereby electrically activating the first and second impurity ions, and Forming a deep-expansion diffusion region inside the semiconductor device.

According to the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, the semiconductor device according to the first to fourth aspects can be easily manufactured.

For example, if the wide bandgap material is silicon carbide (Si)
C), boron (B) as the first impurity ion, and aluminum (A) as the second impurity ion.
l) may be selected.

[0028]

Next, first to eighth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Further, it is needless to say that dimensional relationships and ratios are different between the drawings.

(First Embodiment) As shown in FIG. 2F, a JBS diode according to a first embodiment of the present invention has a first conductivity type ohmic contact region (n-type low resistance SiC). Substrate) 11, the ohmic contact region 1
A first conductivity type drift region (n-type epitaxial growth layer) 12 made of a wide bandgap material provided on
The plurality of second electrodes provided inside the drift region 12
It is composed of conductive deep-expansion diffusion regions 15a and 15b, a drift region 12 provided in contact with the surface of drift region 12, and a Schottky electrode 17 forming a Schottky junction. An ohmic electrode 16 is formed on the entire surface of the ohmic contact region (n-type low-resistance SiC substrate) 11. A plurality of second-conductivity-type deep-expansion diffusion regions 15a and 15b shown in FIG. 2F constitute the structure of the JBS diode.

Drift region 12 has a lower impurity concentration than ohmic contact region 11. Each of the deep expansion diffusion regions 15a and 15b is configured such that the horizontal cross-sectional area gradually increases as approaching the ohmic contact region 11 from the surface of the drift region 12. According to the structure shown in FIG. 2 (f), the horizontal cross-sectional area of the deep-expansion diffusion regions 15a and 15b is increased in the drift region 12 as it becomes deeper.
In a BS diode, the forward resistance can be sufficiently reduced without impairing reverse characteristics such as withstand voltage and leakage current. That is, the area of the Schottky junction is made sufficiently large, and at the same time, a good pinch-off characteristic between the deep expansion type diffusion regions 15a and 15b is realized.

A method for manufacturing a JBS diode according to the first embodiment of the present invention shown in FIG. 2F will be described with reference to FIGS. 1 and 2. (A) First, FIG. As shown, the impurity concentration 1
× 10 ¹⁹ cm ^-3 , 300 μm thick n-type low-resistance SiC
An n-type epitaxial growth layer 12 having an impurity concentration of 3 × 10 ¹⁵ cm ⁻³ and a thickness of 10 μm is formed on a substrate 11 by an epitaxial growth method. Here, nitrogen (N) is used as the n-type impurity, but another impurity, for example, phosphorus (P) may be used.

(B) Next, the n-type epitaxial growth
A metal film 13 is formed on the surface of the layer 12 by vacuum evaporation or sputtering.
Deposits. As the metal film 13, for example, molybdenum
(Mo) can be used. And on the metal film 13
A photoresist film (hereinafter simply referred to as “resist”)
Abbreviated. ) 14 is spin-coated. And the photo
By lithography technology, as shown in FIG.
The dist is patterned. And, in FIG.
Etch the patterned resist 14 as shown.
The metal film 13 is patterned by using
Forming an ion implantation mask 13M as shown in FIG.
I do. Patterning of the metal film 13 is performed by reactive ion etching.
RIE may be used. And this ion
Using the implantation mask 13M, as shown in FIG.
At a position deep from the surface of the n-type epitaxial growth layer 12.
And the substrate temperature T_SUB= Boron at around 700 ° C¹¹B⁺)of
Perform selective ion implantation (deep ion implantation step). here
And boron has the acceleration energy E _ACC= 100-200k
eV, total dose Φ = 3 × 10¹⁵cm^-2For multi-stage injection
From the surface at a depth of 0.25 to 0.5 μm.
Pure substance concentration 1 × 10²⁰cm^{- Three}To form a boron-implanted layer
You. For example: First ion implantation: Φ = 6 × 10¹⁴cm^-2/ E_ACC= 10
0 keV; second ion implantation: Φ = 6 × 10¹⁴cm^-2/ E_ACC= 13
0 keV; third ion implantation: Φ = 6 × 10¹⁴cm^-2/ E_ACC= 15
0 keV; fourth ion implantation: Φ = 1.2 × 10^Fifteencm^-2/ E_ACC
= 200 keV;

[0033] (c) Further, by using the ion implantation mask 13M, as shown in FIG. 2 (d), the n-type epitaxial layer 12 the surface of aluminum at a position shallower than the projected projected range of the boron ⁽²⁷ Al ⁺ ) Selective ion implantation (shallow ion implantation step). Aluminum has a substrate temperature T
_SUB = about 700 ° C, acceleration energy E _ACC = 10-1
Multi-stage implantation is performed at 80 keV and a total dose Φ = 2 × 10 ¹⁵ cm ⁻² . Thereby, an aluminum injection layer having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ is formed in a region having a depth of 0.25 μm from the surface.

(D) Thereafter, the substrate temperature T _SUB = 1600
As shown in FIG. 2 (e), the p-type deep expansion diffusion regions 15a and 15b
To form At this time, the deep expansion diffusion regions 15a, 15
b is about 2 μm wide at each surface, and
The width of the Schottky junction near the surface sandwiched between the opposed deep expansion diffusion regions 15a and 15b was set to about 2 μm.

(E) Then, the n-type low-resistance SiC substrate 11
(Ni) is vapor-deposited to a thickness of about 1 μm on the back surface of the substrate. Further, an ohmic electrode (cathode electrode) 16 is formed as shown in FIG. 2E by sintering at a substrate temperature T _{SUB of} about 1000 ° C.

(F) Next, as shown in FIG.
-Type epitaxial growth layer 12 and deep-expansion diffusion region 15
a, 15b is coated with titanium (Ti) by about 200 n.
m and Al are sequentially deposited to a thickness of about 1 μm to form a Schottky electrode (anode electrode) 17 to complete a JBS diode.

The results of evaluating the electrical characteristics of the JBS diode manufactured as described above are as follows. JBS diode withstand voltage 1000V, reverse voltage 700V
The reverse current at the time of application is 1 × 10 ⁻⁶ A / cm ² , and when the forward current density is 100 A / cm ² , the forward voltage is 1.
It became 7V. On the other hand, when the conventional JBS diode is compared at the same withstand voltage of 1000 V, the forward voltage is 2.
It will be around 5V. Therefore, in the JBS diode of the present invention, a forward voltage reduction of about 0.8 V can be obtained. Here, the reason why the forward voltage can be reduced by about 0.8 V according to the present invention is that the depletion layer extending from the pn junction between the deep expansion diffusion regions 15a and 15b and the n-type epitaxial growth layer 12 to the n-type epitaxial growth layer 12 is reduced. This is because the area of the effective Schottky junction was able to be enlarged while realizing the pinch-off characteristic. It can be seen that the forward voltage drop of the diode having the same chip area can be reduced by about 0.8 V by increasing the area of the effective Schottky junction.

As shown in FIG. 2 (f), when realizing a structure in which the horizontal cross-sectional area of the deep expansion type diffusion regions 15a and 15b becomes deeper toward the inside of the substrate, the lighter boron is deeper. Since injection is performed in the projection range, damage during injection can be greatly reduced. As a result, the forward resistance can be sufficiently reduced without impairing the reverse characteristics such as the breakdown voltage and the leakage current in the JBS diode of the present invention.

(Second Embodiment) A semiconductor device according to a second embodiment of the present invention is a surface gate type SIT as shown in FIG. That is, the surface gate type SIT according to the second embodiment of the present invention includes the first main electrode region (n
Type low-resistance SiC substrate) 11, a first conductivity type drift region (n-type epitaxial growth layer) 21 made of a wide bandgap material provided above the first main electrode region 11, and inside the drift region 21. A plurality of second conductive type deep-expansion diffusion regions 25a, 25b, and a first conductivity-type second deep-diffusion diffusion region 25a, 25b. 2 main electrode area 3
And 5. As in the first embodiment of the present invention, each of the deep-expansion diffusion regions 25a and 25b has a horizontal cross-sectional area gradually increasing as approaching the first main electrode region 11 from the surface of the drift region 21. Three-dimensional shape.

More preferably, the curvature of the outer peripheral surface of the second main electrode region 35 and the curvature of the outer peripheral surfaces of the deep expansion type diffusion regions 25a and 25b opposed to the second main electrode region 35 are equal to each other.
You can make them equal in the female relationship. More preferably, the deep expansion diffusion is performed so that the potential profile of the second main electrode region 35 and the potential profiles of the deep expansion diffusion regions 25a and 25b opposed to the second main electrode region 35 are evenly continuous. Region 25a,
What is necessary is just to select the curvature of 25b.

Each of the deep expansion diffusion regions 25a and 25b functions as a control electrode region (gate region) for controlling a current flowing between the first and second main electrode regions 35.
The first main electrode region 11 functions as a drain region of the surface gate type SIT. The second main electrode region 35 functions as a source region of the surface gate type SIT. Each of the plurality of deep-expansion diffusion regions 25a and 25b is located at an upper region made of the first impurity element and at a lower portion of the upper region, and has a diffusion coefficient in the material with a wider bandgap than the first impurity element. And a lower region made of a second impurity element having a large value.

The drain electrode 43 is in ohmic contact with the first main electrode region (drain region) 11, and the source electrode 41 is in ohmic contact with the second main electrode region (source region) 35. Furthermore, a deep expansion type diffusion region (gate region) 25
a and 25b are respectively provided with gate electrodes 45a and 45b.
Are in ohmic contact.

The SIT can be understood as an extreme transistor in which the FET has a short channel. That is, FE
It can be defined as a device in which the channel is made short enough to cause punching-through between the source region and the drain region of T, and in which a potential barrier which can be controlled by the drain voltage and the gate voltage exists in the channel. Specifically, this device is a device in which the height of a potential barrier (potential), which is a saddle point in a two-dimensional space between a source-drain potential and a potential in a channel due to a gate voltage, is controlled by the drain voltage and the gate voltage. The potential barrier (potential) is a deep expansion type diffusion region (gate region) 25.
Under the influence of the potentials a and 25b, a second main electrode region (source region) 35 is formed on the front surface. Since the drain current flows depending on the height of the potential barrier (potential), the drain current / drain voltage characteristics of the SIT exhibit characteristics in accordance with the same exponential function law as the triode characteristics of a vacuum tube.

As will be described later, the deep expansion type diffusion region 25
If each of a and 25b has a three-dimensional shape such that the horizontal cross-sectional area gradually increases as approaching the first main electrode region 11 from the surface of the drift region 21,
The forward voltage drop can be reduced while the reverse breakdown voltage of the surface gate type SIT is kept high.

The surface gate type SIT shown in FIG.
It can be manufactured by the following procedure: (a) First, an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 3
An impurity concentration of 3 × 10 ¹⁵ cm ^-3 and a thickness of 10 μm are formed on a n-type low-resistance SiC substrate 11 of 00 μm by epitaxial growth.
A μm n-type epitaxial growth layer 21 is formed. Here, nitrogen is used as the n-type impurity, but another impurity such as phosphorus may be used.

(B) Next, a metal film 24 is deposited on the surface of the n-type epitaxial growth layer 21 by vacuum evaporation or sputtering. For example, Mo can be used as the metal film 24. Then, a resist is spin-coated on the metal film 24. Then, the resist is patterned by a photolithography technique. Then, by using the patterned resist as an etching mask, the metal film 24 is patterned to form an ion implantation mask 24 as shown in FIG. RIE may be used for patterning the metal film 24. Then, as shown in FIG. 3A, selective ion implantation of ¹¹ B ⁺ is performed at a deep position from the surface of the n-type epitaxial growth layer 21 via the ion implantation mask 24 (deep ion implantation step). Here, ¹¹ B ⁺ indicates that the substrate temperature T _SUB = about 700 ° C., the acceleration energy E _ACC = 100 to 400 keV, and the total dose Φ =
Multistage injection of 6 × 10 ¹⁵ cm ⁻² is performed. As a result, an impurity concentration of 1.times.
An injection layer of 10 ²⁰ cm ^-3 is formed.

(C) Next, as shown in FIG.
Using the ion implantation mask 24 as a mask, ²⁷ Al ⁺ selective ion implantation is performed from the surface of the type epitaxial growth layer 21 at a position shallower than the projected range of ¹¹ B ⁺ (shallow ion implantation step). ²⁷ Al ⁺ is implanted in multiple stages at a substrate temperature T _{SUB of} about 700 ° C., an acceleration energy E _{ACC of} 10 to 180 keV, and a total dose of Φ = 2 × 10 ¹⁵ cm ⁻² . As a result, an impurity concentration of 1
× 10 ²⁰ A cm ^{-3 27} Al ⁺ implanted layer is formed.

(D) Thereafter, the ion implantation mask 24 is removed, and an activation heat treatment at a substrate temperature T _{SUB of} about 1600 ° C. is performed, as shown in FIG. 25a and 25b are formed. The p-type deep expansion diffusion regions 25a and 25b are the gate regions of the surface gate type SIT. At this time, the deep expansion type diffusion region 25a,
Each width of 25b is about 2 μm near the surface.
Further, the width of the channel sandwiched between the pair of mold deep-expansion diffusion regions 25a and 25b is approximately 1 near the surface.
μm.

(E) Next, the n-type epitaxial growth layer 21
Is deposited on the surface of the substrate by a CVD method. Then, by thermally oxidizing this polycrystalline silicon, the polycrystalline silicon shown in FIG.
As shown in (d), an oxide film 91 is formed on the surface of the n-type epitaxial growth layer 21. When this polycrystalline silicon is thermally oxidized, a thin oxide film 30 is also formed on the back surface of the low-resistance SiC substrate 11. Further, a second metal film 32 is deposited on the surface of the oxide film 91 by a vacuum evaporation method or sputtering. For example, Mo can be used as the second metal film 32. Then, a resist 33 is spin-coated on the second metal film 32. Then, the resist 33 is patterned by photolithography as shown in FIG. Then, using the patterned resist 33 as an etching mask, the second metal film 32 is patterned to form a second ion implantation mask 32M as shown in FIG. RIE may be used for patterning the second metal film 32. Following the RIE of the second metal film 32, the underlying oxide film 91 is also selectively removed by RIE to expose a part of the surface of the n-type epitaxial growth layer 21. Then, as shown in FIG. 4F, the substrate temperature T _SUB = 700 through the second ion implantation mask 32M.
At about ℃, ³¹ P ⁺ is accelerated energy E _ACC = 10 to 200
Multistage ion implantation is selectively performed under the conditions of keV and a total dose Φ = 5 × 10 ¹⁵ cm ⁻² . Then, the second for ion implantation
After removing the mask 32M and the oxide film 91, the substrate temperature T _SUB
As shown in FIG. 5 (g), an n-type source region 35 having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ is formed at a depth of about 0.3 μm from the surface by an activation heat treatment at about 1600 ° C.

(F) Next, an oxide film 31 is formed on the substrate surface by CV.
After the formation by the method D or the like, the oxide film 31 is patterned by RIE or the like using the patterned resist as an etching mask in the same manner as described above. Thereafter, the resist is removed, and the opening of the patterned oxide film 31 is used as a source contact hole. Thereafter, the surface of the oxide film 31 in which the source contact hole is opened is covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is diluted with hydrofluoric acid (HF) or buffer H.
Etch with F or the like. On the back surface of the n-type low-resistance SiC substrate 11, a Ni film is deposited as a third metal film 43 with a thickness of about 1 μm, and a drain electrode 43 is formed by sintering at a substrate temperature T _{SUB of} about 1000 ° C. to 1200 ° C. I do.

(G) Next, as shown in FIG.
A fourth metal film 36 is formed on the surface of the
The film is deposited to a thickness of about 1 μm. Then, the fourth metal film 3
6 is spin-coated with a resist. And the photo library
A resist is formed on the source region 35 by lithography technology.
The resist is patterned so that the resist remains. Soshi
The patterned resist as an etching mask
And etching the fourth metal film, as shown in FIG.
Such a fourth metal film is selectively formed on the source region 35.
leave. And the substrate temperature T _SUB = 1000 ° C. to 1100
The source electrode 41 is formed by sintering at about
You.

(H) Next, a resist is spin-coated on the source electrode 41 and the oxide film 31 exposed from the source electrode 41. Then, by photolithography, the resist is patterned so as to have an opening above each of the deep expansion type diffusion regions (gate regions) 25a and 25b. Then, using the patterned resist as an etching mask, the oxide film 31 is selectively etched to expose the surfaces of the gate regions 25a and 25b,
A gate contact hole as shown in FIG. Thereafter, a Ti film is formed on the entire surface of the
1 films are sequentially deposited to a thickness of about 1 μm. A resist is spin-coated on this Al film, and deep-expansion diffusion regions (gate regions) 25a and 25 are formed by photolithography.
Patterning is performed so as to leave the resist on the upper part of each of b. Then, using the patterned resist as an etching mask, as shown in FIG.
The film and the Ti film are selectively etched by RIE sequentially to form patterns of the gate electrodes 45a and 45b. afterwards,
Substrate temperature T _SUB = 800 to 1000 ° C., for example, 950 ° C.
And sintering for about 5 minutes to form gate electrodes 45a and 45b.
Good ohmic contact. In order to perform the heat treatment for a short time of about 5 minutes, infrared (IR) lamp heating may be used. Thus, the schematic process of the surface gate type SIT is completed.

In this case, the above ion implantation conditions are used for ¹¹ B ⁺ and ²⁷ Al ^+. However, in order to further effectively perform pinch-off by the gate, the acceleration energy E is increased.
By appropriately adjusting the _ACC and the dose Φ, the p-type deep expansion type diffusion regions 26a and 26b can be formed in a substantially trapezoidal shape as shown in FIG. Because in comparison with the deep position of deep expansion-type diffused region and ²⁷ Al ⁺ has intentionally injected several times large diffusion coefficient ¹¹ B ⁺ as described above, after the thermal activation, as shown in FIG. 2 Can effectively widen the width of the deep-expansion diffusion region toward the inside of the substrate. Another advantage of implanting ¹¹ B ⁺ deeper is that ²⁷ A
Since the mass is lighter than l ⁺ , damage at the time of injection can be further reduced, and as a result, a leak current at the time of pinch-off can be greatly suppressed.

The surface gate type SIT manufactured as described above
The results of evaluating the electrical characteristics of are as follows. With a surface-gate type SIT with a withstand voltage of 1000 V, a gate voltage of -3
The leakage current when applying 0 V and drain voltage 600 V is 1
× 10 ⁻⁶ A / cm ² , and ON resistance was 16 mΩcm ² . On the other hand, the on-resistance of the conventional surface gate type SIT is 26 mΩcm when compared at the same withstand voltage of 1000 V.
It will be around ² . Therefore, in the surface gate type SIT according to the second embodiment of the present invention, a reduction in on-resistance of about 10 mΩcm ² can be obtained. Here, the reason that the on-resistance was reduced by about 10 mΩcm ² by the surface gate type SIT according to the second embodiment of the present invention is that the source area could be relatively increased as compared with the same pinch-off characteristic. is there. As a result, the deep expansion diffusion regions 15a, 15
The parasitic resistance caused by the depletion layer extending from the pn junction between b and the n-type epitaxial growth layer 12 to the n-type epitaxial growth layer 12 is reduced by about 10 mΩcm ² . Therefore, by adopting a configuration like the surface gate type SIT according to the second embodiment, the width of the deep expansion type diffusion region can be effectively increased toward the inside of the substrate as described above, and light mass ¹¹ B ⁺ can greatly reduce the damage during implantation because they injected into deeper towards the, without compromising the breakdown voltage, the gate withstand voltage characteristics such as leakage current at its result surface gate type SIT, forward Can be reduced sufficiently. Also, surface gate type SI
Since the voltage amplification factor μ of T depends on the distance between the adjacent gate regions, the voltage amplification factor μ can be increased and the on-resistance can be reduced by using the deep expansion diffusion regions 25a and 25b.

(Third Embodiment) As shown in FIG. 8 (i), a notched-gate SIT according to a third embodiment of the present invention comprises a first conductive type first main electrode region (drain). Region) 11, a first conductivity type drift region 2 made of a wide bandgap material provided on the first main electrode region 11
1, from the surface of the drift region 21 to the first main electrode region 1
A plurality of trenches 48a, 4 dug toward one direction
, A plurality of second-conductivity-type deep-expansion diffusion regions (gate regions) 2 provided inside the drift region 21 at the bottoms of the trenches 48a, 48b,.
5a, 25b,..., A plurality of deep expansion type diffusion regions 2
, The first main electrode regions (source regions) 35a, 35b, 35c,... Of the first conductivity type provided inside the drift region 21 sandwiched between 5a, 25b,. Have been. As in the second embodiment of the present invention, each of the deep-expansion diffusion regions 25a, 25b,... Is formed in a depth direction from the surface of the drift region 21 toward the first main electrode region 11. It has a shape such that the diffusion width in the horizontal direction in the direction perpendicular to the depth direction increases as approaching the first main electrode region 11. A plurality of deep expansion diffusion regions 25a, 25
Each of b,... is located in an upper region made of the first impurity element and in a lower region of the upper region, and has a larger diffusion coefficient in the wide bandgap material than the first impurity element. And a lower region made of two impurity elements. Third
In the embodiment, the case where n-type is used as the first conductivity type and p-type is used as the second conductivity type will be described.

The first main electrode region (drain region) 11 has a drain electrode 43, and the second main electrode regions (source regions) 35a, 35b, 35c,..., Have source electrodes 41a, 41b,. , 41c,... Are in ohmic contact.

The notched gate type SIT shown in FIG.
Can be manufactured by the following procedure: (a) First, an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 3
As shown in FIG. 6 (a), an n-type low-resistance SiC substrate 11
As shown in FIG. 5, an n-type epitaxial growth layer (first epitaxial growth layer) 21 having an impurity concentration of 3 × 10 ¹⁵ cm ⁻³ and a thickness of 10 μm and an impurity concentration of 6 × 10 ¹⁸ cm above the first epitaxial growth layer 21 are obtained by an epitaxial growth method.
^A second epitaxial growth layer 19 having a thickness of about ⁻³ to 1 × 10 ²⁰ cm ⁻³ and a thickness of about 0.3 μm to 1 μm is formed. Here, nitrogen is used as the n-type impurity, but another impurity,
For example, phosphorus may be used. A plurality of impurities such as nitrogen and phosphorus may be used at the same time. Second epitaxial growth layer 19
Instead of forming n-type first epitaxial growth layer 2
Phosphorus on the surface of No. 1 at a substrate temperature T _SUB = about 700 ° C., acceleration energy E _ACC = 10-200 keV, and total dose Φ =
Selective multi-stage ion implantation under the condition of 5 × 10 ¹⁵ cm ^-2 ,
Thereafter, an n-type low resistance region 19 having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ may be formed in a region having a depth of about 0.3 μm from the surface by an activation heat treatment at about 1600 ° C.

(B) Next, an oxide film 34 is formed on the surface of the second epitaxial growth layer 19. Then oxide film 3
A resist 14 is spin-coated on the surface of No. 4 and patterned by photolithography as shown in FIG. 6B. Then, using the patterned resist as an etching mask, as shown in FIG. 6C, an oxide film 34 and an n-type low resistance region (second epitaxial growth layer) are formed by anisotropic etching such as RIE.
19, and the bottom is the n-type first epitaxial growth layer 2
The trenches 48a, 48b,... By forming the trenches 48a, 48b,.
The low-resistance type region (second epitaxial growth layer) 19 is divided into source regions 35a, 35b, 35c,...

(C) After removing the resist 14, as shown in FIG. 7D, the trenches 48a, 48b,.
An oxide film 37 is formed inside. Then, the trenches 48a, 48b,.
.. Are removed. Further, the oxide film 34
A first metal film is deposited on the surface by vacuum evaporation or sputtering. For example, Mo can be used as the first metal film. Then, a resist is spin-coated on the first metal film, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the first metal film is patterned to form an ion implantation mask 13 as shown in FIG.
M may be formed. The patterning of the first metal film is performed by R
IE may be used.

(D) Then, the ion implantation mask 13M
7E, the exposed n at the bottom as shown in FIG.
Selective ion implantation of ¹¹ B ⁺ is performed at a deep position of the first type epitaxial growth layer 21 (deep ion implantation step). Here, ¹¹ B ⁺ is the substrate temperature T _SUB = room temperature to 700 ° C., and here, about 500 ° C., and the acceleration energy E _ACC = 100 to 40 ° C.
Multi-stage implantation is performed at 0 keV and a total dose Φ = 1.8 × 10 ¹³ cm ⁻² . As a result, the depth from the surface is 0.25 to 0.8.
An injection layer having an impurity concentration of 3 × 10 ¹⁷ cm ⁻³ is formed in a region of μm.

(E) Further, as shown in FIG. 7 (f), the n-type first epitaxial growth layer 21 exposed at the bottom is removed from the projected range of ¹¹ B ⁺ using the ion implantation mask 13M as a mask. At a shallow position, ²⁷ Al ⁺ selective ion implantation is performed (shallow ion implantation step). ²⁷ Al ⁺ is implanted in multiple stages with a substrate temperature T _SUB = room temperature to 700 ° C., here about 500 ° C., an acceleration energy E _ACC = 10 to 150 keV, and a total dose Φ = 2 × 10 ¹³ cm ⁻² . As a result, the impurity concentration of 1 × 10 ¹⁸ was obtained in a region 0.25 μm deep from the surface.
A cm ^{-3 27} Al ⁺ implanted layer is formed.

(F) Thereafter, the oxide films 34 and 37 and the ion implantation mask 13M are removed, and the substrate temperature T _SUB = 160
By the activation heat treatment at about 0 ° C., as shown in FIG.
... are formed. p-type deep expansion type diffusion region 25a, 2
Reference numerals 5b,... Indicate gate regions of the cut-gate type SIT. Here, the ion implantation conditions described above were used for boron and aluminum. However, in order to further effectively perform pinch-off by the gate, the acceleration energy E
It is also possible to form the p-type deep-expansion diffusion regions 25a, 25b,... In a substantially trapezoidal shape by appropriately adjusting the _ACC and the dose Φ. As described above, the p-type deep expansion type diffusion region 2
Since boron having a diffusion coefficient approximately several times larger than that of aluminum is intentionally implanted into deep portions of 5a, 25b,..., After the activation heat treatment as in the second embodiment, The widths of the p-type deep-expansion diffusion regions 25a, 25b,... can be effectively increased toward the inside of the substrate.
Another advantage of implanting boron at a deep position is that since the mass is lighter than aluminum, damage at the time of implantation can be further reduced, and as a result, a leak current at the time of pinch-off can be largely suppressed.

(G) Next, the substrate surface and the trenches 48a,
The oxide films 74, 77 are formed inside 48b,.
Then, as shown in FIG. 8G, the oxide film 77 at the bottom of the trenches 48a, 48b,... Is removed by directional etching such as RIE. Then, trenches 48a, 48
, about 200 n of an Al film (second metal film) inside
m, and polycrystalline silicon is deposited on the Al film by a CVD method. Then, the surface is planarized by CMP until the oxide film 74 is exposed, and the Al film / polycrystalline silicon is buried in the trenches 48a, 48b,... As shown in FIG. 45a, 45b,... Are formed.

(H) Then, a resist is spin-coated on the oxide film 74, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the oxide film 74 is selectively etched, a source contact hole is opened, and a part of the source regions 35a, 35b, 35c,... Is exposed. RIE may be used for patterning the oxide film 74. Thereafter, the surface of the oxide film 74 where the source contact hole is opened is covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is etched with diluted hydrofluoric acid (HF) or buffered HF. On the back surface of the n-type low resistance SiC substrate 11, N
An i film is deposited to a thickness of about 1 μm to form a drain electrode 43.

(I) Next, the n-type source regions 35a, 35
An Al film is deposited on the surfaces of b, 35c,... as a fourth metal film with a thickness of about 1 μm. As the fourth metal film, T
Metal such as i or Mo, or various metal silicides may be used. Then, a resist is spin-coated on the fourth metal film. Then, the resist is patterned by photolithography so that the resist remains on the source regions 35a, 35b, 35c,.... Then, using the patterned resist as an etching mask, the fourth metal film is etched.
The fourth metal film as shown in FIG.
The source electrodes 41a, 41b, 41c,... Are selectively left on the upper portions of 5b, 35c,.
Then, sintering is performed for 5 minutes at a substrate temperature T _SUB = 800 to 1100 ° C., for example, 950 ° C.
a, 41b, 41c,..., and the ohmic contact between the drain electrode 43 and the gate electrodes 45a, 45b is improved. This completes the schematic process of the cut-gate SIT.

The notched gate type S manufactured as described above
The results of evaluating the electrical characteristics of IT are as follows. A cut-gate SIT with a withstand voltage of 800 V, a leak current of 1 × 10 ⁻⁶ A / cm ² when a gate voltage of −20 V and a drain voltage of 500 V are applied, and an on-resistance of 13 mΩc
It became m ^2. On the other hand, the on-resistance of the conventional SiC cut-gate SIT is about 26 mΩcm ² when compared at the same withstand voltage of 800 V. Therefore, the cut-gate SIT according to the third embodiment is about 13 mΩcm.
^Thus, a reduction in the on-resistance of ² can be obtained. Here, the reason why the on-resistance can be reduced by about 13 mΩcm ² by the third embodiment is that the p-type deep expansion type diffusion regions 25 a and 25
.. and the pn between the first epitaxial growth layer 21
This is because the parasitic resistance caused by the depletion layer extending from the junction to the first epitaxial growth layer 21 is reduced by about 13 mΩcm ² . Further, in the notched gate type SIT, the capacitance of the gate regions 25a, 25b,... Is greatly reduced, so that the p-type deep expansion diffusion regions 25a, 25b,.・ High speed operation is greatly improved by combining

Therefore, by adopting the structure as in the third embodiment, the gate regions 25a, 25a,
It is possible to effectively increase the width of 25b,... Toward the inside of the substrate, and to reduce the damage at the time of implantation by implanting lighter boron at a deeper position. As a result, the forward resistance can be sufficiently reduced without impairing the gate breakdown voltage characteristics such as the breakdown voltage and the leakage current in the cut-gate SIT.

<Modification of Third Embodiment> FIG.
(F) is a sectional view of a trench sidewall gate type SIT according to a modification of the third embodiment of the present invention. The present invention and the third
Of the present embodiment is that one-sided p-type deep-expansion diffusion regions 39a, 39b, 39c, 39d,... Exist between the top and bottom of the trench. The method for manufacturing the trench side wall gate type SIT shown in FIG.
The p-type deep expansion type diffusion region 2 is formed at the bottom of the trench shown in FIG.
Since the steps up to the point where 5a, 25b,... Are formed are the same as those of the cut-gate type SIT of the third embodiment, description thereof is omitted.

(A) Thereafter, as shown in FIG. 9 (a), the bottom portion of the p-type deep expansion type diffusion regions 25a, 25b,. A second trench reaching the epitaxial growth layer 21 is formed. Due to the formation of the second trench, one-sided p-type deep-expansion diffusion regions 39a, 39b, 39c, 39d,... Are formed on the sidewall between the trench upper portion (first trench) and the bottom portion (second trench). Is done.

(B) Thereafter, as shown in FIG. 10C, an insulating film 46 is deposited by a CVD method inside the extension trench including the first trench and the second trench. Insulating film 4
6 is an oxide film formed by low-temperature CVD or vacuum deposition, or PS
A material having a film quality such as a G film having a higher etching rate of the oxide film than the oxide film 74 is selected. Alternatively, part or all of the surface of the oxide film 74 may be formed of a silicon nitride film (Si ₃ N ₄ film). Further, the surface is planarized by CMP until the oxide film 74 is exposed, and the insulating film 46 is buried inside the extension trench. Further, a back etch is performed by using the film quality of the oxide film having a higher etching rate than the oxide film 74, and FIG.
As shown in (d), buried insulating films 47a, 47b,... Are formed in the bottom (second trench).

(C) Next, an Al film (second metal film) of about 200 nm is deposited inside the extension trench, and polycrystalline silicon is further deposited on the Al film by the CVD method. Then, the surface is planarized by CMP until the oxide film 74 is exposed, and the Al film / polycrystalline silicon is buried in the extension trench as shown in FIG.
.. are formed.

(D) A resist is spin-coated on the oxide film 74, and the resist is patterned by photolithography. Then, using the patterned resist as an etching mask, the oxide film 74 is patterned, a source contact hole is opened, and a part of the source regions 35a, 35b, 35c,... Is exposed. RIE may be used for patterning the oxide film 74. After that, the surface of the oxide film 74 where the source contact hole is opened is covered with a resist,
Hydrofluoric acid (H) diluted the thin oxide film 30 on the back surface of the substrate 11
F) or etching with buffer HF or the like. On the back surface of the n-type low-resistance SiC substrate 11, Ni is used as the third metal film 43.
A film is deposited with a thickness of about 1 μm to form a drain electrode 43.

(E) Next, the n-type source regions 35a, 35
An Al film is deposited on the surfaces of b, 35c,... as a fourth metal film with a thickness of about 1 μm. As the fourth metal film, T
Metal such as i or Mo, or various metal silicides may be used. Then, a resist is spin-coated on the fourth metal film, and the resist is patterned by photolithography so that the resist remains on the source regions 35a, 35b, 35c,.... Then, using the patterned resist as an etching mask, the fourth metal film is etched, and the fourth metal film as shown in FIG. 11F is applied to the source regions 35a, 35b, 35c,
······················································································ Then, the substrate temperature T _SUB =
The ohmic contact between the source electrodes 41a, 41b, 41c,..., The drain electrode 43, and the gate electrodes 45a, 45b is improved by sintering at about 1000 ° C. to 1100 ° C. With this, the trench sidewall gate type SIT
Is completed.

The electrical characteristics of the trench sidewall gate type SIT according to the modification of the third embodiment are greatly improved as in the case of the cut-gate type SIT shown in FIG. Trench sidewall gate type S according to a modification of the third embodiment
In IT, one-sided p-type deep expansion diffusion regions 39a, 39b,
Since the capacities of 39c, 39d,... Are reduced, high-speed operation is greatly improved. That is, by adopting the configuration as shown in FIG. 11F, the width of the one-sided p-type deep-expansion diffusion regions 39a, 39b, 39c, 39d,. Can be done. In addition, since boron having a lighter mass is implanted deeper, damage at the time of implantation can be greatly reduced, and as a result, the trench sidewall gate type S
In the IT, the forward resistance can be sufficiently reduced without impairing the gate breakdown voltage characteristics such as the breakdown voltage and the leakage current.

(Fourth Embodiment) As shown in FIG. 15 (l), a vertical UMOS according to a fourth embodiment of the present invention
The FET has a first conductive type first main electrode region (drain region) 11 and a first conductive type drift region 2 made of a wide bandgap material provided on the first main electrode region 11.
1. a plurality of body regions 64a, 64b, 64c of the second conductivity type disposed on the surface of the drift region 21;
.. a plurality of second main electrode regions (source regions) 63a, 63b, 63c, 63d of the first conductivity type selectively disposed on the surfaces of the body regions 64a, 64b, 64c,.
..., Source regions 63a, 63b, 63c, 63d,.
A plurality of trenches dug from the surface of... In the direction of the drain region 11, a gate oxide film 65 formed on inner walls of the plurality of trenches, and buried in the plurality of trenches and disposed on the surface of the gate oxide film 65 Gate electrodes 45a, 4
5b,..., A plurality of second conductivity type deep expansion diffusion regions (electric field relaxation regions) 66a, 66b,... Provided inside the drift region 21 at the bottoms of the plurality of trenches.
・ It is composed of Similarly to the second and third embodiments of the present invention, the deep expansion diffusion regions 66a, 66b,
Each of the shapes in the depth direction from the surface of the drift region 21 to the drain region 11 has such a shape that the lateral diffusion width in the vertical direction in the depth direction becomes wider as approaching the drain region 11. Having. Each of the plurality of deep-expansion diffusion regions 66a, 66b,... Is located in an upper region made of the first impurity element and is located below the upper region, and has a wider bandgap than the first impurity element. And a lower region made of a second impurity element having a large diffusion coefficient in the width material. In the fourth embodiment, a case in which the first conductivity type is n-type and the second conductivity type is p-type will be described.

The first main electrode region (drain region) 11 has a drain electrode 43, and the second main electrode regions (source regions) 63a, 63b, 63c, 63d,. Ohmic contact. The source electrode 41 includes source regions 63a, 63b, 63c, 63
.. and body regions 64a, 64b, 64c,.
And are short-circuited.

The vertical UMOSFET shown in FIG.
(A) First, as shown in FIG. 12A, an n-type low-resistance Si having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 300 μm.
An n-type epitaxial growth layer (first epitaxial growth layer) 21 having an impurity concentration of 3 × 10 ¹⁵ cm ⁻³ and a thickness of 10 μm and an impurity concentration of 1 × 10 ¹⁶ cm above the first epitaxial growth layer 21 are formed on the C substrate 11 by an epitaxial growth method.
^-3 , a p-type second epitaxial growth layer 55 having a thickness of 3 μm is formed. Here, nitrogen is used as the n-type impurity, but another impurity such as phosphorus may be used. A plurality of impurities such as nitrogen and phosphorus may be used at the same time. Although boron is used as the p-type impurity, another impurity, for example, aluminum may be used.

(B) Next, an oxide film 76 is deposited on the surface of the second epitaxial growth layer 55. Next, the oxide film 76
(Not shown) is spin-coated on the substrate, and the resist is patterned by a photolithography technique. Next, the oxide film 76 is patterned using the patterned resist as an etching mask. After that, the resist is removed. Then, using the patterned oxide film 76 as an ion implantation mask, phosphorus is applied at a substrate temperature T _SUB = 70.
Acceleration energy E _ACC = 10 to 200 ke at about 0 ° C
V, a multi-stage ion implantation is selectively performed under the condition of a total dose Φ = 5 × 10 ¹⁵ cm ⁻² .

(C) Thereafter, the oxide film 76 is removed, and
Activated heat treatment at about 00 ° C to a depth of about 0.3 from the surface
In the region of μm, n-type low resistance regions 57a, 57b,... having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ are formed. Then, FIG.
As shown in FIG. 2C, the n-type low resistance regions 57a and 57
.., an oxide film 58 is deposited.

(D) Next, a resist 59 is spin-coated on the surface of the oxide film 58, and is subjected to a photolithography technique.
As shown in FIG. 13D, the resist 59 is patterned. Then, using the patterned resist 59 as an etching mask, the oxide film 58 is patterned. Then, using the patterned oxide film 58 as an etching mask, as shown in FIG.
The trenches 48a, 48b,... Which penetrate the p-type second epitaxial growth layer 55 and reach the n-type first epitaxial growth layer 21 by IE or the like are formed.

By forming the trenches 48a, 48b,..., The n-type low resistance regions 57a, 57b,... Are divided into source regions 63a, 63b, 63c, 63d,. Is done. Further, the p-type second epitaxial growth layer 55
Are divided into mold body regions 64a, 64b, 64c,...

(E) Then, as shown in FIG. 13 (f), the thickness of the trenches 48a, 48b,.
An oxide film 65 of about nm is formed.

(F) Using the oxide film 58 as a mask for ion implantation, as shown in FIG.
8a, 48b,..., Selective ion implantation of ¹¹ B ⁺ is performed at a deep position of the n-type first epitaxial growth layer 21 located at the bottom (deep ion implantation step). The selective ion implantation of ¹¹ B ⁺ is performed through the oxide film 65. At this time, the oxide film 5
A metal film may be deposited on the surface of 8 by vacuum evaporation or sputtering, and the metal film may be patterned to serve as an ion implantation mask. Here, ¹¹ B ⁺ is the substrate temperature T _SUB
= Room temperature to 700 ° C, here about 500 ° C, acceleration energy E _ACC = 100 to 400 keV, total dose Φ =
Multistage injection of 1.8 × 10 ¹³ cm ⁻² is performed. As a result, the impurity concentration of 3 to 0.25 to 0.8 μm deep from the surface was obtained.
An injection layer of × 10 ¹⁷ cm ^-3 is formed.

(G) Further, as shown in FIG.
Using the oxide film 58 as an ion implantation mask, selective ion implantation of ²⁷ Al ⁺ is performed on the n-type first epitaxial growth layer 21 located at the bottom of the trench at a position shallower than the projected range of ¹¹ B ⁺ (shallow). Part ion implantation step). The selective ion implantation of ²⁷ Al ⁺ is performed through the oxide film 65. ²⁷ A
l ⁺ is the substrate temperature T _SUB = room temperature to 700 ° C., here 50
At about 0 ° C., acceleration energy E _ACC = 10 to 150 ke
V, multi-stage implantation with a total dose Φ = 2 × 10 ¹³ cm ⁻² .
As a result, a ²⁷ Al ⁺ implantation layer having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ is formed in a region having a depth of 0.25 μm from the surface.

(H) Next, after the oxide films 58 and 65 are removed, an activation heat treatment at a substrate temperature T _{SUB of} about 1600 ° C. is performed, as shown in FIG. Form diffusion regions 66a, 66b,.... The p-type deep-expansion diffusion regions 66a, 66b,.
This is a p-type electric field relaxation region of the MOSFET. Since boron having a diffusion coefficient approximately several times larger than that of aluminum is intentionally implanted into deep portions of the p-type electric field relaxation regions 66a, 66b,..., as in the third embodiment. After the activation heat treatment, the width of the p-type electric field relaxation regions 66a, 66b,... Can be effectively increased toward the inside of the substrate.
Another advantage of implanting boron at a deeper position is that the mass is lighter than aluminum, so damage during implantation can be further reduced, and as a result, the electric field concentration when a reverse voltage is applied can be greatly suppressed. can give.

(I) Next, the substrate surface and the trenches 48a,
The oxide films 58 and 65 are formed again inside 48b,. Thereafter, polysilicon doped with a high concentration of phosphorus is deposited inside the trenches 48a, 48b,... By a CVD method. By using dry etching such as RIE or CDE, the polysilicon to which phosphorus is added at a high concentration is left only in the trenches 48a, 48b,... As a result, buried gate electrodes 45a, 45b,... Are formed. Then, an interlayer insulating film 67 is deposited on the oxide film 58 by a CVD method as shown in FIG.

(G) A resist is spin-coated on the interlayer insulating film 67, and the resist is patterned by photolithography. Then, using the patterned resist as an etching mask, the interlayer insulating film 67 and the oxide film 58 are selectively etched, a source contact hole is opened, and the source regions 63a and 63 are formed.
3b, 63c, 63d,... And p-type body region 64
a, 64b, 64c,... are partially exposed. The source contact hole is opened so as to expose both the source regions 63a, 63b, 63c, 63d,... And the p-type body regions 64a, 64b, 64c,. Is done. Interlayer insulating film 67 and oxide film 58
May be continuously performed using RIE.
Thereafter, the surfaces of the interlayer insulating film 67 and the oxide film 58 where the source contact holes are opened are covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is diluted with hydrofluoric acid (HF) or buffered HF. Etch with etc. On the back surface of the n-type low-resistance SiC substrate 11, a metal film 4
As No. 3, a Ni film is deposited with a thickness of about 1 μm to form a drain electrode 43.

(L) Next, as shown in FIG.
n-type source regions 63a, 63b, 63c, 63d,...
An Al film is deposited in a thickness of about 1 μm as a metal film on the surface of. As the metal film, a metal such as Ti, Mo, or various metal silicides may be used. Then, a resist is spin-coated on the metal film, and the source regions 63a, 63b, 63c, and 6 are formed by photolithography.
The resist is patterned so that the resist remains on 3d,.... Then, using the patterned resist as an etching mask, the metal film is etched, and the metal film as shown in FIG.
The source electrode 41 is patterned while being selectively left above the portions 3a, 63b, 63c, 63d,.... In the case of a power device, the source electrode 41 is formed on the entire surface,
In some cases, patterning is not necessary. Then, at a substrate temperature T _SUB = 800 to 1100 ° C., for example,
Sintering is performed for a minute to improve the ohmic contact between the source electrode 41, the drain electrode 43, and the gate electrodes 45a and 45b. This completes the schematic process of the vertical UMOSFET.

The vertical UMOSFE manufactured as described above
In T, the electric field strength of the insulating film at the bottom end of the p-type electric field relaxation regions 66a, 66b,.
Higher withstand voltage can be realized. It is the p-type electric field relaxation regions 66a and 66 according to the fourth embodiment of the present invention.
This is because the voltages are equally shared by b,. When the p-type electric field relaxation regions 66a, 66b,... are not provided, the breakdown voltage is about 700 to 900 V, whereas when the p-type electric field relaxation regions 66a, 66b,.
.., To about 1200 V, and the electric field concentration in the p-type electric field relaxation regions 66a, 66b,...

<Modification of Fourth Embodiment> FIG.
(L) is a sectional view of a vertical UMOSFET according to a modification of the fourth embodiment of the present invention. FIG. 18 (l) and FIG.
The structure shown in FIG. 18 (l) is different from the structure shown in FIG. 18 (l) in that the structure shown in FIG. 15 (l) is different from the structure shown in FIG. .. Are provided. Electric field relaxation regions 69a, 69b, 69c,...
^Represents a p-type region having a thickness of about 0.5 μm and a surface impurity concentration of about 10 ¹⁷ to 10 ¹⁸ cm ⁻³ (second conductivity type)
It is.

The vertical UMOSFET shown in FIG.
Can be manufactured by the following procedure: (a) First, an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 3
An impurity concentration of 3 × 10 ¹⁵ cm ^-3 and a thickness of 10 μm are formed on a n-type low-resistance SiC substrate 11 of 00 μm by epitaxial growth.
A μm n-type epitaxial growth layer (first epitaxial growth layer) 21 is grown. Thereafter, the SiC substrate 11 is taken out from the epitaxial growth furnace, and an oxide film (not shown) is formed on the first epitaxial growth layer 21. Next, a resist (not shown) is spin-coated on the oxide film, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the oxide film 68 is patterned by RIE or the like. Next, after removing the resist, FIG.
As shown in (a), selective ion implantation of ¹¹ B ⁺ is performed (deep ion implantation step). Here, ¹¹ B ⁺ is the substrate temperature T _SUB = room temperature to 700 ° C., and here, about 500 ° C., the acceleration energy E _ACC = 50 to 200 keV, and the total dose Φ
= 1.8 × 10 ¹³ cm ⁻² multi-stage implantation. Further, FIG.
As shown in (b), the n-type first epitaxial growth layer 2
On the other hand, the oxide film 68 is used as a mask for ion implantation.
^{At a} position shallower than the projected range of ¹¹ B ⁺ , ²⁷ Al ⁺ selective ion implantation is performed (shallow ion implantation step). ²⁷ Al ⁺ is implanted in multiple stages with a substrate temperature T _SUB = room temperature to 700 ° C., here about 500 ° C., an acceleration energy E _ACC = 5 to 70 keV, and a total dose Φ = 2 × 10 ¹³ cm ⁻² .

(B) Thereafter, the oxide film 68 on the surface is removed, and an activation heat treatment at a substrate temperature T _{SUB of} about 1600 ° C. is performed, as shown in FIG. The regions 69a, 69b, 69c,... Are formed. Thereafter, an impurity concentration of 1 × 10 ¹⁶ c is formed on the first epitaxial growth layer 21 as shown in FIG.
m ⁻³ , 3 μm thick p-type second epitaxial growth layer 55
To form

(C) Subsequent manufacturing steps are basically the same as the steps shown in FIGS. 12 (b) to 15 (l) described above. For example, FIGS. 17 (g), (h), and (i) correspond to FIGS. 14 (g), (h), and (i), respectively. Also, FIG.
8 (j), (k), and (l) correspond to FIGS.
(K) and (l). Therefore, duplicate description is omitted here.

As described above, in the vertical UMOSFET according to the modification of the fourth embodiment, the voltage is equally shared by the deep expansion p-type electric field relaxation regions 66a, 66b,. In addition, since the voltage is equally distributed also by the deep expansion type electric field relaxation regions 69a, 69b, 69c,... The electric field concentration on the substrate is further remarkably reduced. It is a deep expansion type electric field relaxation region 6.
, And a depletion layer extending from the junction between the first epitaxial growth layer 21 and the deep expansion type p-type electric field relaxation regions 66a, 66b,.
This is because the depletion layer extending from the junction with the epitaxial growth layer 21 is coupled, and as a result, the voltage applied between the drain and source electrodes is equally shared by the coupled depletion layer.

More specifically, the p-type electric field relaxation regions 69a, 69b, and 69 have the above-described configuration according to the modification of the fourth embodiment.
.., the breakdown voltage is about 1000 to 1200 V, whereas the deep expansion type p-type
a, 66b,.
The voltage greatly increased to about 50 V, and the electric field concentration on the gate oxide film 65 was further improved, so that the reliability of the device was significantly improved.

(Fifth Embodiment) As shown in FIG. 20 (f), a surface gate type bipolar mode SIT (BSIT) according to a fifth embodiment of the present invention has a first conductivity type first mode. A main electrode region (drain region) 11; a first region made of a wide band gap material provided on the drain region 11;
Drift region of conductivity type (n-type epitaxial growth layer) 2
1. A plurality of second conductivity type deep expansion diffusion regions (gate regions) 25 provided inside the drift region 21
a, 25b,..., a plurality of deep expansion type diffusion regions 25
a base region 72 of the second conductivity type sandwiched between a, 25b,..., a second main electrode region (source region) 35 of the first conductivity type provided near the inner surface of the base region 72, It is composed of The impurity concentration of the base region 72 is set sufficiently lower than that of the deep-expansion type diffusion regions 25a, 25b,..., And the drain region 11 and the source region 35 are almost punched through. I have. However, when no voltage is applied to the gate regions 25a, 25b,..., The height of the potential barrier for electrons is sufficiently high, so that no drain current flows and the surface gate type BSIT
Indicates normally-off characteristics. Gate regions 25a, 25
When a voltage equal to or less than the built-in voltage is applied to b,.

Surface Gate Type SI According to Second Embodiment
As in the case of T, each of the surface-gate-type BSIT deep-expansion diffusion regions 25a, 25b,... Three-dimensional shape. In the fifth embodiment, the first conductivity type is n
The case where the mold is used and the p-type is used as the second conductivity type will be described. In the first main electrode region (drain region) 11, the drain electrode 43 is provided with a second main electrode region (source region) 35.
Is in ohmic contact with the source electrode 41.
Further, deep expansion type diffusion regions (gate regions) 25a, 25
Each of the gate electrodes 45a, 45b
Are in ohmic contact.

The surface gate type BSIT shown in FIG.
Can be manufactured by the following procedure: (a) First, an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 3
An impurity concentration of 3 × 10 ¹⁵ cm ^-3 and a thickness of 10 μm are formed on a n-type low-resistance SiC substrate 11 of 00 μm by epitaxial growth.
A μm n-type epitaxial growth layer 21 is formed. Here, nitrogen is used as the n-type impurity, but another impurity such as phosphorus may be used. Next, a metal film is deposited on the surface of the n-type epitaxial growth layer 21 by vacuum evaporation or sputtering. As a metal film, for example, M
o is available. Then, a resist is spin-coated on the metal film, and the resist is patterned by a photolithography technique. Then, using the patterned resist as an etching mask, the metal film is patterned to form an ion implantation mask. Then, similarly to the second embodiment, the n-type epitaxial growth layer 2
Deep from the surface of 1 through an ion implantation mask
¹¹ B ⁺ selective ion implantation is performed (deep ion implantation step). Here, ¹¹ B ⁺ is the substrate temperature T _SUB = room temperature to 700
° C, here about 500 ° C, acceleration energy E _ACC = 1
00 to 400 keV, total dose Φ = 6 × 10 ¹⁴ cm ⁻²
Multi-stage injection. As a result, the depth from the surface is 0.25 to
An injection layer having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ is formed in a 0.8 μm region. Further, the n-type epitaxial growth layer 21
Then, using a mask for ion implantation as a mask, selective ion implantation of ²⁷ Al ⁺ is performed at a position shallower than the projected range of ¹¹ B ⁺ (shallow ion implantation step). ²⁷ Al ⁺ is implanted in multiple stages with a substrate temperature T _SUB = room temperature to 700 ° C., here about 500 ° C., an acceleration energy E _ACC = 10 to 150 keV, and a total dose Φ = 2 × 10 ¹⁶ cm ⁻² . As a result, an impurity concentration of 1 × 10 ²⁰ was obtained in a region having a depth of 0.25 μm from the surface.
A cm ^{-3 27} Al ⁺ implanted layer is formed. Then, the metal film of the mask for ion implantation is removed, and the substrate temperature T _SUB = 16
By the activation heat treatment at about 00 ° C., as shown in FIG.
.. are formed. p-type deep expansion type diffusion region 25
a, 25b,... are gate regions of the surface gate type BSIT. At this time, the deep expansion diffusion regions 25a, 25
Each width of b,... is about 2 μm. Further, a pair of mold deep-expansion diffusion regions 25a and deep-expansion diffusion regions 2
The width of the channel sandwiched between 5b is set to about 1 μm near the surface. Here, the above-described ion implantation conditions were used for boron and aluminum. However, in order to further effectively perform pinch-off by the gate, the acceleration energy E _ACC and the dose Φ were appropriately adjusted to obtain a p-type deep expansion type. The diffusion regions 25a, 25b,... Can be formed in a substantially trapezoidal shape as shown in FIG. As mentioned above, p
Boron, whose diffusion coefficient is several times larger than that of aluminum, is intentionally implanted into the deep portion of the mold low-resistance region, so that the gate regions 25a, 25b ,... Can be effectively expanded toward the inside of the substrate. Another advantage of implanting boron at a deep position is that since the mass is lighter than aluminum, damage at the time of implantation can be further reduced, and as a result, a leak current at the time of pinch-off can be largely suppressed.

(B) Next, the n-type epitaxial growth layer 21
As shown in FIG. 19A, boron is ion-implanted in a multi-stage manner under the conditions of an acceleration energy E _ACC = 10 to 200 keV and a total dose Φ = 5 × 10 ¹² cm ⁻² , as shown in FIG.
A mask for ion implantation is formed, and the gate regions 25a, 25
For b,..., selective ion implantation may be performed so that ion implantation is not performed.

(C) 1600 ° C. after boron ion implantation
As shown in FIG. 19B, an activation heat treatment is performed to a depth of about 0.5 μm from the surface of the n-type epitaxial growth layer 21 to an impurity concentration of 1 × 10 ¹⁷ cm ^−3.
Is formed. Next, polycrystalline silicon is deposited on the surface of the n-type epitaxial growth layer 21 by a CVD method. Then, by thermally oxidizing the polycrystalline silicon, an oxide film 91 is formed on the surface of the n-type epitaxial growth layer 21 as shown in FIG. When the polycrystalline silicon is thermally oxidized, the low-resistance SiC substrate 11
A thin oxide film 30 is also formed on the back surface of the substrate. As the method of forming the oxide film, other than the above method, the oxide film may be deposited by a CVD method using SiH4, N2O, or the like.

(D) Further, the second metal is formed on the surface of the oxide film 91.
The film 32 is deposited by a vacuum evaporation method or sputtering.
For example, Mo can be used as the second metal film 32.
Then, a resist 33 is spin-coated on the second metal film 32.
Cloth. Then, by photolithography technology,
The strike 33 is patterned as shown in FIG.
You. Then, the patterned resist 33 is etched.
The second metal film 32 is etched by RIE using the mask as an etching mask.
20D for ion implantation as shown in FIG.
A mask 32M is formed. Following the RIE of the second metal film 32
And the underlying oxide film 91 is also selectively removed by RIE,
Exposing a part of the surface of the n-type epitaxial growth layer 21
You. Then, via the second mask 32M for ion implantation,
As shown in FIG. 20D, the substrate temperature T_SUB= 700 ° C
About³¹P⁺The acceleration energy E _ACC= 10-200k
eV, total dose Φ = 5 × 10¹⁵cm^-2Select by condition
Multi-stage ion implantation. Then, a second mask for ion implantation is used.
After removing the mask 32M and the oxide film 91, the substrate temperature T_SUB=
By the activation heat treatment at about 1600 ° C., as shown in FIG.
As shown in FIG.
Concentration 1 × 10²⁰cm^{- Three}Of n-type source region 35
You.

(E) Next, an oxide film 31 is formed again on the substrate surface by the CVD method or the like, and then the resist is patterned using the resist patterned as described above as an etching mask.
The oxide film 31 is patterned using E or the like. Thereafter, the resist is removed, and the opening of the patterned oxide film 31 is used as a source contact hole. afterwards,
The surface of the oxide film 31 with the source contact hole opened is covered with a resist, and the thin oxide film 30 on the back surface of the low-resistance SiC substrate 11 is etched with diluted hydrofluoric acid (HF) or buffered HF. n-type low resistance SiC substrate 11
On the back surface, a Ni film is deposited as a third metal film 43 to a thickness of about 1 μm to form a drain electrode 43. Then, n
On the surface of the mold source region 35, an Al film is deposited as a fourth metal film to a thickness of about 1 μm. Then, a resist is spin-coated on the fourth metal film. Then, the resist is patterned by photolithography so that the resist remains above the source region 35. Then, using the patterned resist as an etching mask,
The fourth metal film is etched to selectively leave the fourth metal film as shown in FIG. 20F above the source region 35, thereby forming the source electrode 41. Next, a resist is spin-coated on the source electrode 41 and the oxide film 31 exposed from the source electrode 41. Then, the deep expansion type diffusion regions (gate regions) 25a, 25a are formed by photolithography technology.
The resist is patterned so as to have an opening above each of b,. Then, using the patterned resist as an etching mask, the oxide film 31 is formed.
Are selectively etched to form gate regions 25a, 25b,
The surface of... Is exposed, and a gate contact hole as shown in FIG. Thereafter, a Ti film is deposited in a thickness of about 200 nm and an Al film is deposited in a thickness of about 1 μm sequentially on the entire surface. A resist is spin-coated on the Al film and patterned by photolithography so as to leave the resist on each of the deep-expansion diffusion regions (gate regions) 25a, 25b,.... Then, using the patterned resist as an etching mask, the Al film and the Ti film are selectively etched by RIE sequentially as shown in FIG.
The patterns a and 45b are formed. Then, the substrate temperature T
Sintering is performed at _SUB = 800 to 1150 ° C., for example, 950 ° C. for about 5 minutes to improve the ohmic contact between the source electrode 41, the drain electrode 43, and the gate electrodes 45a and 45b. Thus, the schematic process of the surface gate type BSIT is as follows.
finish.

The surface gate type BSI manufactured as described above
The results of evaluating the electrical characteristics of T are as follows.
Surface voltage type BSIT withstand voltage 1000V, gate voltage
Leakage current when -10V and drain voltage 600V are applied
Is 1 × 10^-6A / cm^Two And the on-resistance is 18mΩcm^Two 
It became. On the other hand, a conventional SiC surface gate type BS
Compared with the same withstand voltage of 1000 V in IT, the ON resistance is
26mΩcm^Two Before and after. Therefore, the fifth embodiment
About 8 mΩcm in the surface gate type BSIT according to ^Two On
A reduction in resistance will be obtained.

Here, the reason why the on-resistance can be reduced by about 8 mΩcm ² by the fifth embodiment is that the p-type deep expansion diffusion regions 25 a, 25 b,... The parasitic resistance caused by the depletion layer extending from the pn junction to the n-type epitaxial growth layer 21 is reduced to about 8 mΩ.
This is due to the reduction in cm ² . Therefore, FIG.
By adopting the configuration shown in FIG.
The widths of a, 25b,... can be effectively increased toward the inside of the substrate. In addition, since the lighter boron is injected deeper, damage during injection can be greatly reduced,
As a result, the forward resistance can be sufficiently reduced without impairing the gate breakdown voltage characteristics such as the breakdown voltage and the leakage current in the surface gate type BSIT. In the fifth embodiment, a normally-off type surface-gate type BSIT is realized by providing the p-type base region 72.

As shown in FIG. 21, an n-type region 73 having a low impurity concentration may be provided between n-type source region 35 and p-type base region 72.

Further, the invention according to the fifth embodiment can also be applied to the bipolar transistor (BJT) shown in FIG. A BJT according to a modification (second modification) of the fifth embodiment of the present invention is provided on a first main electrode region (collector region) 81 made of a SiC substrate, and provided above the first main electrode region 81. Drift region (n-type epitaxial growth layer) 21 made of a wide bandgap material and a plurality of deeply-expanded diffusion regions 82 a and 82 b of the second conductivity type provided inside drift region 21. ,..., A p-type base region 83 sandwiched between a plurality of deep-expansion diffusion regions 82a, 82b,. And a second main electrode region (emitter region) 84.

In the BSIT shown in FIG.
The impurity concentration of the base region 72 is
Are set sufficiently lower than 5a, 25b,..., And almost punching-through occurs between the drain region 11 and the source region 35. However, FIG.
In the BJT shown in FIG. 2, the impurity concentration of the p-type base region 83 is set higher than that of the base region 72. For example, the impurity concentration of the p-type base region 83 is 1 × 10 ¹⁸
It is set to about cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . Therefore, a neutral p-type base region 83 remains between the collector region 81 and the emitter region 84, and the collector region 8
1 is less likely to affect the emitter region 84 side.

The deep expansion diffusion regions 82a, 82b,...
Each has a three-dimensional shape such that the horizontal cross-sectional area gradually increases as approaching the first main electrode region 81 from the surface of the drift region 21. In this case, the p-type deep expansion diffusion regions 82a, 82b,... Function as an external base region (base electrode extraction region) of the BJT. A collector electrode 87 is in ohmic contact with the collector region 81, and an emitter electrode 86 is in ohmic contact with the emitter region 84. Also, the base electrode extraction region 82a,
A base electrode 85 made of an Al / Ti composite film is in ohmic contact with 82b,. BJT shown in FIG.
Are effectively expanded toward the inside of the substrate, the p-type deep expansion diffusion regions 82a, 82b,... Are connected to the p-type base region 72 of the internal base with low resistance. Can be greatly reduced. That is, BJ
It is possible to increase the frequency of T. Further, since the device is a bipolar device, conductivity modulation can be used, and the on-resistance can be further reduced.

(Sixth Embodiment) The second to fifth embodiments of the present invention
The method for manufacturing a semiconductor device described in the above embodiments can also be applied to an electrostatic induction thyristor (SI thyristor). SI
In the case of a thyristor, the surface gate type SI shown in FIG.
In the structure of T, the conductivity type of the n-type low-resistance SiC substrate 11 may be a p-type low-resistance SiC substrate 51 as shown in FIG.

That is, S according to the sixth embodiment of the present invention.
As shown in FIG. 23, the I-thyristor includes a first main electrode region 51, a first conductivity type drift region 21 provided on the first main electrode region 51 and made of a wide bandgap material, Are provided between the plurality of deeply-diffused diffusion regions 25a, 25b,... Of the second conductivity type provided in the inside of the. And the second main electrode region 53 of the first conductivity type provided inside the drift region 21. As in the first embodiment of the present invention, the deep expansion diffusion region 25 is used.
Each of a, 25b,... has a three-dimensional shape in which the horizontal cross-sectional area gradually increases as approaching the first main electrode region 51 from the surface of the drift region 21. Each of the deep expansion diffusion regions 25a, 25b,... Is a control electrode region (gate region 25a, 25b,...) For controlling a current flowing between the first and second main electrode regions 53.
・) The first main electrode region 51 functions as an anode region of the SI thyristor. The second main electrode region 53 functions as a cathode region of the SI thyristor. A plurality of deep expansion type diffusion regions 25a, 25b,...
Are an upper region made of a first impurity element and a lower region made of a second impurity element located below the upper region and having a larger diffusion coefficient in the wide bandgap material than the first impurity element. Area.

An anode electrode 52 is in ohmic contact with the first main electrode region (anode region) 51, and a cathode electrode 54 is in ohmic contact with the second main electrode region (cathode region) 53. Further, a deep expansion type diffusion region (gate region) 2
Each of the gate electrodes 45a, 25b,.
a and 45b are in ohmic contact.

In the SI thyristor, the height of a potential barrier (potential) which is a saddle point in a two-dimensional space of a potential between a cathode and an anode and a potential in a channel by a gate voltage is controlled by an anode voltage and a gate voltage. The potential barriers (potentials) are deep expansion type diffusion regions (gate regions) 25a, 25b,.
Is formed on the front surface of the second main electrode region (cathode region) 35 under the influence of the potential of the second main electrode region. An anode current flows depending on the height of the potential barrier (potential). When the SI thyristor is turned on, the height of the potential barrier formed in the drift region 21 by applying a positive potential to the deep expansion type diffusion regions (gate regions) 25a, 25b,. (Electric induction effect). That is, as the height of the potential barrier decreases, the second
From the main electrode region (cathode region) 35 to the drift region 2
Electrons are injected into 1. The injected electrons are accumulated on the front surface of the first main electrode region (anode region) 51,
Hole from main electrode region (anode region) 51
Promotes the injection of That is, a large amount of electrons and holes start flowing instantaneously. The turn-off is performed by applying a negative potential or a zero potential to the deep expansion type diffusion regions (gate regions) 25a, 25b,. Start by blocking the electrons that are made.

In the case of a normally-off type SI thyristor, a deep expansion type diffusion region (gate region) 25a, 25
b,... Applying a zero potential prevents electrons injected from the second main electrode region (cathode region) 35 into the drift region 21. In the case of a normally-on type SI thyristor, a deep expansion type diffusion region (gate region) 25a, 2
... 5b,..., Applying a negative potential to increase the height of the potential barrier (potential), and block electrons injected from the second main electrode region (cathode region) 35 into the drift region 21. . However, as long as the electrons accumulated on the front surface of the first main electrode region (anode region) 51 do not disappear by recombination or the like,
Since there is injection of holes from the first main electrode region (anode region) 51, a tail current exists.

Also in the case of the SI thyristor, the area of the cathode can be relatively increased by comparison with a fixed pinch-off characteristic. Therefore, a lower on-resistance can be obtained with the same breakdown voltage.

That is, similarly to the SIT, also in the case of the SI thyristor, the forward loss can be sufficiently reduced without impairing the gate breakdown voltage characteristics such as the breakdown voltage and the leakage current.
High-efficiency switching becomes possible.

The method of manufacturing the SI thyristor according to the sixth embodiment of the present invention is the same as the method of manufacturing the surface gate type SIT described with reference to FIGS.
23, as shown in FIG. 23, the p-type low-resistance SiC
If the substrate is changed to the substrate 51, the others are basically the same. Therefore, duplicate description will be omitted.

FIG. 24 is a sectional view of a semiconductor device according to a modification (first modification) of the sixth embodiment of the present invention. In the anode short type SI thyristor shown in FIG. 24, the anode region is divided into a plurality of divided anode regions 62a, 62b, 62c,... S formed with
It has an I anode short structure. Each of the divided anode regions 62a, 62b, 62c,... Forms a deep-expansion type diffusion region similar to the gate regions 25a, 25b,. In this case, the divided anode region 6
2a, 62b, 62c,... And the short area 61a,
The electron is shorted to the short region 61 by the potential with 61b
a, 61b. Therefore, the tail current at the time of turn-off is small, and high-speed switching is possible. Note that the divided anode regions 62a, 62b,
The pitch of 62c,... May be selected to be not more than twice the electron diffusion length. A plurality of divided anode regions 62a, 62b, 62c,... Forming the structure of the deep expansion type diffusion region shown in FIG.
Are used to effectively extract electrons accumulated on the entire surface of the anode region using the short regions 61a, 61b,... While increasing the effective area of the anode region. Becomes possible. Therefore, the tail current can be suppressed without increasing the on-resistance. Therefore, an anode short-type SI thyristor having a low on-voltage and a high-speed turn-off characteristic at the same time is obtained.

FIG. 25 is a sectional view of a semiconductor device according to a modified example (second modified example) of the sixth embodiment of the present invention. The notched gate SI thyristor shown in FIG.
This corresponds to a structure in which the conductivity type of the resistance SiC substrate 11 of the cut-gate SIT according to the third embodiment shown in FIG.

FIG. 26 is a sectional view of a semiconductor device according to a modification (third modification) of the sixth embodiment of the present invention. In the normally-off SI thyristor shown in FIG.
BSI according to the fifth embodiment shown in FIG.
This corresponds to a structure in which the conductivity type of the T resistance SiC substrate 11 is p-type. (Seventh Embodiment) FIG. 27 shows a lateral UMOSFET (lateral UMOSFE) according to a seventh embodiment of the present invention.
It is sectional drawing of T). Horizontal UM according to a seventh embodiment
OSFET and vertical UMOSFE according to fourth embodiment
The difference from T is that the drain electrode 90 is formed not on the back surface of the substrate but on the surface of the first epitaxial growth layer 21.

In the seventh embodiment, instead of the p-type second epitaxial growth layer 55 formed on the first epitaxial growth layer 21 by the epitaxial method in the fourth embodiment, a certain amount is provided on the first epitaxial growth layer 21. , For example, a p-type body region 64a having a stripe shape,
Are formed by selective ion implantation using boron or aluminum or both. Next, the p-type body region 6 is formed on the first epitaxial growth layer 21.
An n-type drain region 89 is formed at a position at a certain distance from 4a, 64b, 64c,.... Next, one or more p-type electric field relaxation regions 6 are provided between the p-type body regions 64a, 64b, 64c,.
4d, 64e,... To p-type body regions 64a, 64
, 64c,... are provided in parallel. The p-type electric field relaxation regions 64d, 64e, ... alleviate the electric field concentration at the ends of the p-type body regions 64a, 64b, 64c, .... Next, a drain electrode 90 is formed on the n-type drain region 89. Here, the drain electrode 90 is desirably formed at a predetermined distance from the gate electrodes 45a, 45b,... And in parallel with the gate electrodes 45a, 45b,. The structure other than the above steps is shown in FIG.
Vertical UMOSF according to the fourth embodiment shown in FIG.
Basically the same as ET. The horizontal UMOSFET
To complete.

In the lateral UMOSFET, the source electrode 41
Since a, 41b, 41c,... and the drain electrode 90 are provided on the same surface, it is easy to integrate them as a monolithic IC on the same semiconductor chip. In addition, the wiring work is simplified even when used in a hybrid IC or the like. Further, since the drain electrode 90 is provided in each semiconductor device, the degree of freedom in surface wiring and connection is increased, and the design is facilitated.

The structure of the n-type drain region 8 and the drain electrode 90 shown in the seventh embodiment can be similarly applied to the structure of the modification of the fourth embodiment shown in FIG. It is.

(Eighth Embodiment) FIG. 28 shows a JBS diode according to the first embodiment as the auxiliary element 2 and an anode short type SI thyristor according to the sixth embodiment as the main element 1. Are arranged on the same semiconductor chip. The manufacturing steps of the semiconductor integrated circuit according to the eighth embodiment are the same as those described in detail in the first and sixth embodiments, and a description thereof will be omitted.

In the semiconductor integrated circuit according to the eighth embodiment, a JBS diode as the auxiliary element 2 and an anode short type SI thyristor as the main element 1
A unit cell is configured. The anode short type SI thyristor is a reverse conducting SI thyristor, and the JBS diode functions as a freewheel diode connected in parallel to the reverse conducting SI thyristor. That is, the parallel connection structure of the reverse conducting SI thyristor and the freewheel diode is used as a unit cell, and these unit cells are formed in a stripe shape in the n-type drift region 21 periodically in a multi-channel structure.

Here, the p-type gate region 25 of each unit cell
a, 25b,... are p-type gate regions 25a, 25b,.
, And also functions as a guard ring for the JBS diode. Therefore, as compared with the case where the anode short type SI thyristor and the JBS diode are independently formed, the area of the entire device can be reduced, and the device current density can be improved.

(Other Embodiments) As described above, the present invention has been described with reference to the first to eighth embodiments. However, the description and drawings constituting a part of this disclosure limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

In the first embodiment, if the deep expansion diffusion regions 18a and 18b are formed in a substantially trapezoidal shape as shown in FIG. 29, the leakage current in the reverse direction can be further reduced. To form a trapezoid, the acceleration energy E _ACC
And the dose Φ may be adjusted. In any case, since the deep expansion type diffusion regions 18a and 18b are intentionally implanted with boron having a diffusion coefficient about several times larger than that of aluminum, the activation heat treatment after the ion implantation is performed. The width of the deep expansion type diffusion regions 18a and 18b can be effectively increased toward the inside of the substrate. Another advantage of implanting boron deeper is that the mass is lighter than aluminum, which can reduce damage during implantation.
As a result, the leakage current at the time of pinch-off can be greatly suppressed.

In the above description of the first to eighth embodiments, the case where the n-type is used as the first conductivity type and the p-type is used as the second conductivity type has been described. Of course, the opposite is also possible.

In the first to eighth embodiments, Si
C has been described by way of example, but the forbidden band width Eg = about 2.C.
2 eV ZnTe, forbidden band width Eg = about 2.4 eV Cd
S, forbidden band width Eg = ZnSe of about 2.7 eV, forbidden band width Eg = GaN of about 3.4 eV, forbidden band width Eg = about 3.7
The present invention can be similarly applied to a wide band gap semiconductor such as eV ZnS and diamond having a forbidden band width Eg = about 5.5 eV.

Further, the present invention provides a JBS diode, a surface gate type SIT, a notched gate type SIT, and a vertical UMOSFE described in the first to eighth embodiments, respectively.
T, BSIT, SI thyristor, horizontal UMOSFET,
The present invention is not limited to an integrated circuit, but can be applied to various other semiconductor devices including a MOS composite device such as an emitter switched thyristor (EST). or,
15 (l) and 18 described in the fourth embodiment.
(1) In the structure of the vertical UMOS of FIG.
If the C substrate 11 is replaced with a p-type low resistance SiC substrate, it functions as a trench IGBT. Further, in the structure of the horizontal UMOS of FIG. 27 described in the seventh embodiment,
If the n-type drain region 89 is replaced with a p-type collector region, it functions as a lateral IGBT. Further, in the BSIT or BJT structure shown in FIGS. 20F and 22 described in the fifth embodiment, the n-type low-resistance SiC substrate 11 is
Normally-off type S
It functions as an I thyristor or a GTO thyristor. In addition, various modifications may be made without departing from the spirit of the present invention.
It can be applied to various other semiconductor devices.

In the above description of the first to eighth embodiments, an oxide film is used as an insulating film formed on a trench or a surface. However, in addition to this, a tantalum oxide (Ta ₂
0 ₅ ), silicon nitride (Si ₃ N ₄ ) and aluminum nitride (A
1N) may be used.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0133]

According to the first feature of the present invention, the forward resistance can be sufficiently reduced without impairing the reverse characteristics such as the withstand voltage and the leakage current.

According to the second feature of the present invention, the forward resistance can be sufficiently reduced without impairing the breakdown voltage characteristics of the control electrode region of the semiconductor device.

According to the third feature of the present invention, the deep expansion diffusion region greatly reduces the electric field strength of the gate insulating film near the bottom of the trench, and realizes an insulated gate semiconductor device with a higher breakdown voltage. I can do it.

According to the fourth feature of the present invention, a horizontal insulated gate semiconductor device having a higher withstand voltage can be realized as in the third feature. In addition, since the first and second main electrode regions are provided on the same surface, integration is easy.

According to the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, the semiconductor device according to the first to fourth aspects can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view for explaining a manufacturing process of a JBS diode according to a first embodiment of the present invention (part 1).

FIG. 2 is a process cross-sectional view for explaining a manufacturing process of the JBS diode according to the first embodiment of the present invention (part 2).

FIG. 3 is a process cross-sectional view for explaining a manufacturing process of a surface-gate type SIT according to a second embodiment of the present invention (part 1).

FIG. 4 is a process cross-sectional view for explaining a manufacturing process of the surface-gate type SIT according to the second embodiment of the present invention (part 2).

FIG. 5 is a process cross-sectional view for explaining the manufacturing process of the surface-gate type SIT according to the second embodiment of the present invention (part 3).

FIG. 6 is a process cross-sectional view for explaining the manufacturing process of the notched-gate SIT according to the third embodiment of the present invention (part 1).

FIG. 7 is a process cross-sectional view for explaining the manufacturing process of the notched-gate SIT according to the third embodiment of the present invention (part 2).

FIG. 8 is a process sectional view for explaining the manufacturing process of the notched-gate SIT according to the third embodiment of the present invention (part 3).

FIG. 9 is a process cross-sectional view for explaining a manufacturing process of a trench sidewall gate type SIT according to a modification of the third embodiment of the present invention (part 1).

FIG. 10 is a process cross-sectional view for explaining a manufacturing process of the trench sidewall gate type SIT according to the modification of the third embodiment of the present invention (part 2).

FIG. 11 is a process sectional view for describing the manufacturing process of the trench side wall gate type SIT according to the modification of the third embodiment of the present invention (part 3).

FIG. 12 is a vertical UM according to a fourth embodiment of the present invention.
FIG. 11 is a process sectional view for describing the manufacturing process of the OSFET (Part 1).

FIG. 13 is a vertical UM according to a fourth embodiment of the present invention.
FIG. 10 is a process sectional view for describing the manufacturing process of the OSFET (part 2).

FIG. 14 is a vertical UM according to a fourth embodiment of the present invention.
FIG. 10 is a process sectional view for describing the manufacturing process of the OSFET (part 3).

FIG. 15 is a vertical UM according to a fourth embodiment of the present invention.
FIG. 14 is a process sectional view for describing the manufacturing process of the OSFET (part 4).

FIG. 16 is a process sectional view for describing the manufacturing process of the vertical UMOSFET according to the modification of the fourth embodiment of the present invention (part 1).

FIG. 17 is a process cross-sectional view for explaining a manufacturing process of the vertical UMOSFET according to the modification of the fourth embodiment of the present invention (part 2).

FIG. 18 is a process sectional view for describing the manufacturing process of the vertical UMOSFET according to the modification of the fourth embodiment of the present invention (part 3).

FIG. 19 shows a BSIT according to a fourth embodiment of the present invention.
It is a process sectional view for explaining the manufacturing process (No. 1).

FIG. 20 is a diagram illustrating a BSIT according to a fourth embodiment of the present invention.
It is a process sectional view for explaining the manufacturing process of (2).

FIG. 21 is a cross-sectional view for describing a BSIT structure according to a modification (first modification) of the fourth embodiment of the present invention.

FIG. 22 is a cross-sectional view illustrating a structure of a BSIT according to another modification (second modification) of the fourth embodiment of the present invention.

FIG. 23 is a schematic sectional view for explaining a structure of an SI thyristor according to a sixth embodiment of the present invention.

FIG. 24 is a schematic cross-sectional view illustrating a structure of an SI thyristor according to a modification (first modification) of the sixth embodiment of the present invention.

FIG. 25 is a schematic cross-sectional view illustrating a structure of an SI thyristor according to another modification (second modification) of the sixth embodiment of the present invention.

FIG. 26 is a schematic cross-sectional view of an SI thyristor according to still another modification (third modification) of the sixth embodiment of the present invention.

FIG. 27 is a lateral UM according to a seventh embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view illustrating a structure of an OS.

FIG. 28 is a schematic sectional view illustrating the structure of a semiconductor integrated circuit according to an eighth embodiment of the present invention.

FIG. 29 is a schematic sectional view of a JBS diode according to another embodiment of the present invention.

FIG. 30 is a schematic sectional view of a surface gate type SIT according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 main element 2 auxiliary element 11 n-type low-resistance SiC substrate (first main electrode region) 12, 21 n-type epitaxial growth layer (first epitaxial growth layer) 13 metal film 13M ion implantation mask 14, 33, 56 resist 15a, 15b , 18a, 18b, 25a, 25b, 2
6a, 26b Deep expansion type diffusion region 16 Ohmic electrode (cathode electrode) 17 Schottky electrode (anode electrode) 19 n-type epitaxial growth layer (second epitaxial growth layer) 24 Ion implantation mask (metal film) 30, 31, 34, 37 , 58, 74, 76, 77, 9
Reference Signs List 1 oxide film 32 second metal film 32M second mask for ion implantation 35, 35a, 35b, 35c, 63a, 63b, 63
c, 63d Second main electrode region (source region) 36 Fourth metal film 39a, 39b, 39c, 39d One side p-type deep expansion diffusion region (gate region) 41, 41a, 41b, 41c Source electrode 43 Third metal film (Drain electrode) 45a, 45b, 45c Gate electrode 46, 71a, 71b Insulating film 47a, 47b Buried insulating film 48a, 48b Trench 51 First main electrode region (anode region) 52 Anode electrode 5 53 Second main electrode region (cathode) Region) 54 Cathode electrode 55 P-type epitaxial growth layer (second epitaxial growth layer) 57a, 57b N-type low resistance region 61a, 61b, 61c Short region 62a, 62b, 62c, 62d Split anode region 64a, 64b, 64c P-type body region 64d, 64ep p-type electric field relaxation region 65 gate Oxide film 67 interlayer insulating film 68 mask for ion implantation 69a, 69b, 69c electric field relaxation region (deep expansion type diffusion region) 72, 83 p-type base region 73 n-type region 81 first main electrode region (collector region) 82a, 82b Deep expansion type diffusion region (base electrode extraction region) 84 second main electrode region (emitter region) 85 base electrode 86 emitter electrode 87 collector electrode 89 drain region (first main electrode region) 90 drain electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/822 H01L 29/78 658E 29/161 21/265 Z 29/737 F 29/74 29/48 F 29/78 29/80 V 652 29/163 29/74 M 29/78 301 V 653 29/72 H 29/80 27/06 TF term (reference) 4M104 AA03 BB02 BB05 BB14 BB16 BB25 BB26 CC01 CC03 CC05 FF01 FF13 GG03 GG06 GG09 GG11 GG18 5F003 AP04 BE04 BF03 BF06 BG03 BH08 BJ12 BJ93 BM01 BM04 BP05 BZ01 BZ02 BZ03 5F005 AC01 AE02 AE07 AE09 AF02 AH02 GA01 5F102 FA01 FB01 GB04 GC07 GC02 AGC02A

Claims (8)

[Claims] An ohmic contact region of a first conductivity type; and 2.2 e having a lower impurity concentration than the ohmic contact region and being provided above the ohmic contact region.
A drift region of a first conductivity type made of a wide bandgap material having a wider forbidden band than V; and a top exposed on the surface of the drift region and provided inside the drift region. A plurality of second-conductivity-type deep-expansion diffusion regions having a horizontal cross-sectional area gradually increasing toward the ohmic contact region; and the drift region provided in contact with the surface of the drift region. A semiconductor device comprising: a Schottky electrode forming a Schottky junction. 2. A first main electrode region of a first conductivity type or a second conductivity type, provided above the first main electrode region and having a lower impurity concentration than the first main electrode region and 2.2 eV. A drift region of a first conductivity type made of a wide bandgap material having a wider forbidden band, and a top portion exposed on the surface of the drift region and provided inside the drift region; A plurality of second-conductivity-type deep-expansion diffusion regions each having a horizontal cross-sectional area gradually widening toward an ohmic contact region; and A second main electrode region of the first conductivity type provided inside the drift region between the deep expansion type diffusion regions;
The semiconductor device according to claim 1, wherein each of the deep-expansion diffusion regions functions as a control electrode region for controlling a current flowing between the first and second main electrode regions. 3. The method according to claim 2, wherein the plurality of deeply inflated diffusion regions include:
The semiconductor device according to claim 2, further comprising a second conductivity type base region. 4. A first main electrode region of a first conductivity type or a second conductivity type, and provided above the first main electrode region and having a lower impurity concentration than the first main electrode region and 2.2 eV. A first conductivity type drift region made of a wide bandgap material having a wider forbidden band, a plurality of second conductivity type body regions disposed on the surface of the drift region, and a plurality of body regions disposed on the surface of the body region. A second main electrode region of the first conductivity type, a plurality of trenches dug from the surface of the second main electrode region toward the first main electrode region, penetrate the body region and reach the drift region; A gate insulating film formed on inner walls of the plurality of trenches; a gate electrode disposed on a surface of the gate insulating film inside the plurality of trenches; and an inside of the drift region below the plurality of trenches Provided in the A plurality of second-conductivity-type deep-expansion diffusion regions each having a horizontal cross-sectional area gradually increasing from the bottom of the wrench toward the first main electrode region region and functioning as an electric field relaxation region. A semiconductor device characterized by the above-mentioned. 5. A drift region of a first conductivity type made of a wide bandgap material having a wider bandgap than 2.2 eV, a plurality of body regions of a second conductivity type disposed on a surface of the drift region, A first impurity layer having a higher impurity concentration than the drift region and arranged on the surface of the drift region;
A first main electrode region of a conductivity type or a second conductivity type; a second main electrode region of a first conductivity type disposed on a surface of the body region; and a penetrating through the body region from the surface of the second main electrode region. A plurality of trenches reaching the drift region; a gate insulating film formed on inner walls of the plurality of trenches; a gate electrode disposed on a surface of the gate insulating film inside the plurality of trenches; Are provided inside the drift region below the trench, and have a horizontal cross-sectional area that gradually increases from the bottom of the trench toward the direction away from the body region, and functions as an electric field relaxation region. And a deep expansion type diffusion region of the second conductivity type. 6. Each of the plurality of deep-expansion diffusion regions includes an upper region containing a first impurity element, and a lower bandgap band located below the upper region, the wider bandgap than the first impurity element. Second material with large diffusion coefficient in material
6. The semiconductor device according to claim 1, comprising a lower region containing the impurity element of (a). 7. A step of forming an ion implantation mask on the surface of a semiconductor region of the first conductivity type made of a wide bandgap material having a wider bandgap than 2.2 eV, and using the ion implantation mask A deep ion implantation step of implanting a first impurity ion exhibiting a second conductivity type into the semiconductor region a plurality of times while changing the acceleration energy; and using the ion implantation mask to make the semiconductor region more than the first impurity ion. A shallow ion implantation step of implanting a plurality of second impurity ions having a small diffusion coefficient therein at a position shallower than a projection range of the first impurity ions while changing acceleration energy, and a heat treatment step, And a step of electrically activating the second impurity ions to form a deep expansion diffusion region inside the semiconductor region. Law. 8. The wide bandgap material is made of silicon carbide (Si).
The method according to claim 7, wherein C), wherein the first impurity ions are boron (B), and the second impurity ions are aluminum (Al).