JP2686125B2 - Static induction type switching element and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electrostatic induction switching device having a gate region embedded in a semiconductor substrate and a method for manufacturing the same.

[Conventional technology]

Fig. 5 shows static induction type transistor (hereinafter referred to as "SI transistor"), static induction type thyristor (hereinafter referred to as "SI transistor").
It is called "SI thyristor". ) Etc., the conventional static induction switching device with a buried gate structure (hereinafter referred to as “SI device”).
That. 2] A sectional view showing the gate structure of FIG. As shown in the figure, by selective impurity diffusion in the upper layer part of the n ⁻ substrate 1,
The p ⁺ gate region 5 (5a, 5b) is formed. n ^- substrate 1
An n epitaxial layer 2 is formed on the region 1a, and the p ⁺ gate region 5a is buried therein. Therefore, the n ⁻ substrate 1 and the n epitaxial layer 2 between the p ⁺ gate regions 5 form the channel region 8.

Gate metal electrode 3 is formed on p ⁺ gate region 5b. An n ⁺ cathode region 4 is formed on the surface of the n epitaxial layer 2, and a cathode metal electrode 6 is formed on the n ⁺ cathode region 4. Each p ⁺ gate region 5
Are connected by an impurity diffusion layer having a cross section different from that shown in the figure.

FIG. 6 is a cross-sectional view showing the gate structure of the SI element having the surface gate structure. As shown in the figure, the p ⁺ gate region 5 is deeply formed in the upper layer portion of the n ⁻ substrate 1 by selective impurity diffusion. Further, n between p ⁺ gate region 5 ^- n ⁺ cathode region 4 is shallower than the p ⁺ gate region 5 by selective impurity diffusion in the upper layer portion of the substrate 1. Therefore, a deep portion between the p ⁺ gate regions 5 where the n ⁺ cathode region 4 is not formed becomes the channel region 8.

A gate metal electrode 3 is formed on the p ⁺ gate region 5 and a cathode metal electrode 6 is formed on the n ⁺ cathode region 4, and these electrodes 3 and 4 are insulated by an insulating film 7.

FIG. 7 is a cross-sectional view showing the gate structure of an SI device having a grooved gate structure. As shown in the figure, a large number of concave grooves are formed in the n ⁻ substrate 1. Below these grooves, ap ⁺ gate region 5 obtained by diffusing impurities from the groove bottom is formed. On the other hand, the n ⁺
A cathode region 4 is formed. Therefore, the region between the p ⁺ gate regions 5 becomes the channel region 8.

Further, the gate metal electrode 3 is formed on the p ⁺ gate region 5,
A cathode metal electrode 6 is formed on the n ⁺ cathode region 4, and the gate metal electrode 3 and the cathode metal electrode 6 are formed.
Are insulated by the insulating film 7 formed on the uneven step portion.

Although the gate metal electrode 3 in FIG. 7 functions as a wiring, the gate metal electrode 3 may not be formed and the gate impurity diffusion layer, that is, the p ⁺ gate region 5 itself may be used as a gate wiring. is there.

When the SI element having the configuration shown in FIGS. 5 to 7 is a normally-on type, a voltage is applied to each of the electrodes 3 and 6 so that a reverse bias is applied between the gate metal electrode 3 and the cathode metal electrode 6. When applied, the main current flowing in the channel region 8 is blocked by the pinch-off of the channel region 8,
At the same time, excess minority carriers are extracted from the gate metal electrode 3 and the SI element is turned off. On the other hand, when 0 or a positive bias is applied between the gate and the cathode, the pinch-off of the channel region 8 is released, the main current flows in the channel region 8, and the SI element is turned on.

The characteristics related to ON / OFF of the SI element that operates as described above depend largely on the gate structure. For example,
The resistance of the p ⁺ gate region 5 needs to be as low as possible in order to quickly extract the minority carriers and achieve a fast turn-off.

In addition, since the turn-off speed and the amount of current that can be blocked depend on the reverse breakdown voltage between the gate and cathode (how much reverse bias can be applied), high reverse breakdown voltage between the gate and cathode is also required. .

On the other hand, since the main current flows through the channel region 8, it is necessary to precisely control the channel width and the channel length determined when the p ⁺ gate region 5 is formed by impurity diffusion in order to improve the on / off characteristics.

In addition to the above-mentioned improvement in switching characteristics, in order to lower the on-voltage, it is desired to increase the number of channels and miniaturize the gate structure.

[Problems to be solved by the invention]

As described above, there are mainly three types of conventional SI devices: a buried gate structure, a surface gate structure, and a grooved gate structure.

The SI element of the buried gate structure shown in FIG. 5 has an advantage that the reverse breakdown voltage between the gate and the cathode can be made high because the p ⁺ gate region 5 is buried, and the structure is a pressure contact type packaging. Is advantageous to.

However, when the n epitaxial layer 2 is formed, it is necessary to suppress the occurrence of defects and the autodoping from the high-concentration p ⁺ gate region 5 in the underground, and therefore, n
It is difficult to form the epitaxial layer 2. Therefore, the sixth
There is a problem that the impurity concentration profile of the channel region 8 becomes worse as compared with the case where only the n ⁻ substrate 1 is used as in the surface gate structure and the uneven groove gate structure shown in FIGS. Further, there is a problem that it is difficult to accurately form the channel width and the channel length of the channel region 8 due to floating of impurities from the p ⁺ gate region 5 when forming the n epitaxial layer 2.

On the other hand, the SI element having the surface gate structure shown in FIG. 6 has an advantage that it is easy to manufacture. However, p ⁺ gate region 5 the n ^- are formed on the substrate 1 surface, n ^- easily occurs an electric field concentration in the pn junction surface of the substrate 1, it is difficult to set a high reverse breakdown voltage. Therefore, there is a problem that the amount of current that can be blocked at the time of turn-off cannot be large.

Further, since the SI element having the recessed groove gate structure shown in FIG. 7 forms the p ⁺ gate region 5 by the impurity diffusion from the bottom of the recessed groove, as in the SI element having the buried gate structure, the p ⁺
There is an advantage that the gate region 5 can be formed and a high reverse breakdown voltage can be obtained.

The formation of the p ⁺ gate region 5 of this SI element is performed after forming the concave groove.
It is performed by normal ion implantation or doping with a gas containing impurities at a high temperature. This p ⁺ gate region 5
In the step of forming, it is necessary to prevent p-type impurities from diffusing in the direction of the side surface of the groove in order to improve the reverse breakdown voltage between the gate and the cathode. For this reason, when high-concentration impurity diffusion is performed to form the p ⁺ gate region 5, it is necessary to prevent the diffusion of impurities to the side surface of the concave portion by enlarging the etching on the side surface in advance and increasing the width of the concave-convex groove. Therefore, it is not suitable for miniaturization. Conversely speaking, there is a problem that the impurity concentration of the p ⁺ gate region 5 cannot be increased when miniaturization is intended.

Also, for the purpose of preventing a short circuit between the gate metal electrode 3 and the cathode metal electrode 6, there is a problem that it is difficult to miniaturize the gate pattern and the cathode pattern because the groove width is sufficient. . Further, the SI element of the grooved gate structure is basically a surface wiring structure, and it is unsuitable to apply this SI element to a pressure contact type element because it may not be possible to maintain a sufficient insulation distance. . As described above, there is a structure in which wiring is not performed by the gate metal electrode 3, but in this case, another problem that the gate resistance cannot be made sufficiently small occurs.

The present invention has been made to solve the above-mentioned problems, and has excellent reverse breakdown voltage between the gate and the cathode, and the entire channel region can be formed using a semiconductor substrate. The width can be formed accurately,
It is an object to obtain an electrostatic induction switching device having a low gate resistance and suitable for miniaturization.

[Means for solving the problem]

An electrostatic induction switching element according to the present invention is a semiconductor substrate of a first conductivity type having first and second main surfaces, and a semiconductor substrate covered with an insulating material and embedded therein. And a gate region formed of a diffusion layer of a second conductivity type formed around the polysilicon and a polysilicon containing impurities of a second conductivity type, the gate region being insulated from the first main surface by the insulating layer. A portion of the semiconductor substrate between the gate regions is defined as a channel region by being embedded in the semiconductor substrate by the thickness of the material and is formed in the semiconductor substrate, and the first region above the channel region is defined. A first main electrode region of a first conductivity type formed on a main surface; a second main electrode region of a first or second conductivity type formed on the second main surface; The first main electrode is electrically connected to the main electrode region. A first metal electrode formed on the region and on the insulating material, and a second metal electrode formed on the second main electrode region by being electrically connected to the second main electrode region. I have it.

The method for manufacturing an electrostatic induction switching device according to the present invention comprises: (a) a step of preparing a first conductivity type semiconductor substrate having first and second main surfaces; and (b) a step of preparing the semiconductor substrate. Forming a first main electrode region of a first conductivity type on the first main surface; and (c) selectively removing the first main electrode region and the semiconductor substrate to form a trench. , (D) forming polysilicon containing a second conductivity type impurity at the bottom of the trench, and (e) diffusing the second conductivity type impurity using the polysilicon as a diffusion source, Forming a diffusion layer around the polysilicon, the diffusion layer forming a gate region together with the polysilicon, and (f) burying the polysilicon in a bottom portion of the trench with an insulating material. Further equipped with a lid The gate region is embedded in the semiconductor substrate by the thickness of the insulating material from the first main surface to the second main surface side, and (g) is formed on the second main surface of the semiconductor substrate. Forming a second main electrode region of the first or second conductivity type on the main surface, and (h) electrically connecting to the first main electrode region, Forming a first metal electrode on the insulating material; and (g) forming a second metal electrode on the second main electrode region by electrically connecting to the second main electrode region. And are further equipped.

[Action]

The gate region in the present invention is composed of polysilicon containing an impurity of the second conductivity type buried in the semiconductor substrate and a diffusion layer which can be formed by diffusion using this polysilicon as a diffusion source. The channel region formed in the portion of the semiconductor substrate between the regions can be formed with high precision.

〔Example〕

1 (a) to 1 (g) are cross-sectional views showing a method of manufacturing an SI element according to an embodiment of the present invention. Hereinafter, the manufacturing method will be described with reference to FIG.

First, an n ⁺ cathode region 12 is formed on the entire surface of an n ⁻ substrate 11 by impurity diffusion, and an oxide film 13 is further formed on the n ⁺ cathode region 12 by a thermal oxidation method. Then, a resist is applied on the oxide film 13, and then the resist is patterned. Then, the oxide film 13 is selectively etched using this resist as a mask. Further, as shown in FIG. 3A, the n ⁻ substrate 11 is formed using the patterned oxide film as a mask.
The trench 14 is formed by anisotropically etching.

Next, a so-called doped polysilicon 15 containing a high concentration of p-type impurities is buried in the trench 14 as shown in FIG. Further, after the surface is flattened, a thermal oxide film 16 is formed on the entire surface of the n ⁻ substrate 1 containing the doped polysilicon 15. At this time, at the same time, the p ⁺ diffusion layer 17 is formed on the outer periphery of the polysilicon 15 by thermal diffusion using the polysilicon 15 as a diffusion source.

Then, a resist 18 is applied on the oxide film 16, and the resist 18 is patterned in a region including the upper layer portion of the doped polysilicon 15 and wider by 2 to 3 μm. Then, the oxide film 16 is etched by using the resist 18 as a mask to form an opening 19 wider than the upper surface of the doped polysilicon 15 as shown in FIG.

Further, using the patterned oxide film 16 as a mask,
The doped polysilicon 15, n ⁺ cathode region 12 and the p ⁺ diffusion layer 17 are anisotropically etched to form a trench 20 having an opening wider than the upper surface of the doped polysilicon 15 and a depth shallower than the trench 14. As a result, the doped polysilicon 15 and the p ⁺ diffusion layer 17 up to the depth of the trench 20 are removed as shown in FIG.

Next, an oxide film 21 is formed on the entire surface of the n ⁻ substrate 11 including the trench 20 by a thermal oxidation method. Furthermore, due to impurity diffusion using the doped polysilicon 15 as a diffusion source by heat treatment,
As shown in FIG. 7E, the p ⁺ gate region 22 is formed.
At this time, at the same time, a channel region 23 having a desired channel width and channel length is formed.

Then, the insulator 24 is buried in the trench 20 by the CVD method or the like, and the surface is flattened as shown in FIG. Further, the oxide film 21 on the n ⁺ cathode region 12 is selectively etched to expose the surface of the n ⁺ cathode region 12 to form a cathode contact region 12a. Thereafter, as shown in FIG. 9G, a cathode metal electrode 25 electrically connected to the n ⁺ cathode region 12 via the cathode contact region 12a is formed. As a result, the gate and cathode regions of the SI element in this embodiment are completed. Then, the p ⁺ anode region 27 is formed on the back surface of the n ⁻ substrate 11 by impurity diffusion, and the anode metal electrode 28 is formed on the p ⁺ anode region 27.
The SI thyristor as shown in the figure is completed. Further, when the p ⁺ anode region 27 is replaced with the n ⁺ layer, it becomes an SI transistor.

FIG. 3 is a plan view of the SI element of this embodiment. In addition,
In the figure, 29 is a gate contact region electrically connected to the p ⁺ gate region 22 by a buried doped polysilicon or silicide layer, and a gate metal electrode 30 is formed on this gate contact region 29. . Further, 31 is an insulating film, which is formed below the cathode metal electrode 25. The II cross section of this plan view corresponds to the cross sectional view of FIG.

As described above, the p ⁺ gate region 22 of the SI element of the present embodiment is n ⁻
It is formed by thermal diffusion using the doped polysilicon 15 formed in the substrate 11 as a diffusion source. Therefore, the dimensional accuracy is improved as described below.

First, the thickness control of the p ⁺ gate region 22, p ⁺ gate region 22
Even in the case of increasing the impurity concentration of, it can be easily performed by increasing the impurity concentration of the doped polysilicon 15. Therefore, if the spacing between the trenches 14 is set to 10 to 20 μm, p ⁺ is obtained by thermal diffusion using the doped polysilicon 15 containing p-type impurities as the diffusion source.
The channel width d between the gate region 22-p ⁺ gate region 22 is 2 to
It can be accurately formed with a width of 5 μm (the optimum width for a normally-on SI element).

By the way, in a general SI element, the ratio (blocking gain) G of a constant voltage that can be blocked by the gate voltage to the gate voltage is determined by the following equation (1).

G ∝ L × W / d ² (1) where d is the channel width (see FIG. 1 (g)), L is the channel length (see FIG. 1 (g)), and W is in the off state from the gate to the anode. Is the thickness of the depletion layer that extends to. The higher the blocking gain G, the more suitable for high power applications.

The channel length L is the final remaining doped polysilicon.
Depends on the depth of 15. Therefore, the trench 14,20
A desired channel length L can be obtained by appropriately setting the depth. For example, the SI element for high power applications with a blocking voltage of 1000V and a blocking gain μ of 160-200 is 5μ.
A channel length L of about m is required.

In addition, the reverse breakdown voltage between the gate and cathode is the p ⁺ gate region
It also depends on the depth at which 22 is formed, that is, the depth of the trench 20. For example, if the impurity concentration of the n ⁻ substrate 11 is 1 × 10 ¹⁵ / cm ³ or less, a reverse breakdown voltage of about 100 V can be obtained when the depth of the trench 20 is 7 to 8 μm. That is, by setting the depth of the trench 20 appropriately, a sufficient reverse breakdown voltage can be obtained.

On the other hand, the width of the trench 14 is related to the resistance value of the p ⁺ gate region 22, and SI for high power with a large current drawn from the gate is used.
In the device, the impurity concentration of p ⁺ gate region 22 is 10 ¹⁹ to 10 ²⁰ / c.
When it is m ³ , 5 to 10 μm is required. Therefore, as described above, since the interval between the trenches 14 is about 10 to 15 μm, if one gate region and one cathode region are regarded as one unit, one unit can be formed with a width of 15 to 25 μm. 2 to 3 compared to the conventional SI element shown in Fig. 5
More than double the miniaturization is possible.

Next, improvement of electrical characteristics by forming the p ⁺ gate region 22 of the SI element by thermal diffusion using the doped polysilicon 15 formed in the n ⁻ substrate 11 as a diffusion source will be described.

First, since the entire channel region can be formed only by the n ⁻ substrate 11 without using the epitaxial layer, the impurity concentration profile of the channel region does not deteriorate unlike the conventional SI element shown in FIG. As a result, stable switching characteristics, sufficient gate and reverse breakdown voltage between cathodes, and improved blocking characteristics can be obtained with high accuracy.

Furthermore, since the doped polysilicon 15 itself contains a high concentration of impurities and the gate resistance value can be greatly reduced, high-speed switching characteristics can be obtained and excess minority carriers can be reliably extracted at turn-off.

Moreover, since the insulator 24 is embedded in the trench 20, the gate,
The junction capacitance due to the pn junction between the cathodes is reduced, which is also advantageous for faster turn-on and turn-off. The above is the improvement of electrical characteristics.

Further, since the completed SI element is flattened by the insulating layer 24, it has the same structure as the conventional buried gate structure shown in FIG.
Like the SI element, it can be used as a pressure contact type element.

4 (a) to 4 (h) are cross-sectional views showing a method of manufacturing an SI element which is another embodiment of the present invention. Hereinafter, the manufacturing method will be described with reference to FIG.

First, the n ⁺ cathode region 12 is formed on the entire surface of the n ⁻ substrate 11,
Further, an oxide film 13 is formed on the n ⁺ cathode region 12 by a thermal oxidation method. Then, a resist is applied on the oxide film 13, and then the resist is patterned. Then, the oxide film 13 is selectively etched using this resist as a mask, and as shown in FIG. 3A, the n ⁻ substrate 1 is anisotropically etched using the patterned oxide film as a mask to form trenches 14. To form.

Then, doped polysilicon 15 containing a high concentration of impurities is buried in the trench 14 as shown in FIG. Further, after the surface is flattened, a thermal oxide film 16 is formed on the entire surface of the n ⁻ substrate 11 containing the doped polysilicon 15. At this time,
At the same time, the p ⁺ diffusion layer 17 is formed on the outer periphery of the doped polysilicon 15 by thermal diffusion using the doped polysilicon 15 as a diffusion source.

Then, a resist 18 is applied on the oxide film 16, and the resist 18 in a wide area of 2 to 3 μm including the upper surface of the doped polysilicon 15 is patterned and removed.
The oxide film 16 is etched by using as a mask to form an opening 19 wider than the upper surface of the doped polysilicon 15, as shown in FIG.

Next, using the patterned oxide film 16 as a mask, the doped polysilicon 15, n ⁺ cathode region 12 and p ⁺ diffusion layer 1 are formed.
7 is taper-etched to have a larger opening than the top surface of the doped polysilicon 15 and a bottom that is about the top surface of the doped polysilicon 15 and is shallower than the trench 14.
Form 20. As a result, as shown in FIG. 3D, the polysilicon 15 and p ⁺ diffusion layer 17 up to the depth of the trench 20 are almost removed.

Next, the entire surface of the n ⁻ substrate 1 including the trench 20 is covered with an oxide film 21 by a thermal oxidation method. Further, by heat treatment, using the doped polysilicon 15 as a diffusion source, impurity diffusion is performed to form ap ⁺ gate region 22 as shown in FIG. At this time, a channel region 23 having a desired channel width and channel length is simultaneously formed.

After that, the surface of the polysilicon 15 is exposed by etching or the like, and a conductive layer 26 such as metal silicide is formed on the exposed portion of the polysilicon 15 as shown in FIG.
At this time, since the trench 20 is formed in a tapered shape, the conductive layer is easily formed on the exposed surface of the polysilicon 15, that is, the bottom of the trench 20 by etching after forming the conductive layer over the entire surface of the n ⁻ substrate 1 including the trench 20. A conductive layer 26 can be formed on the substrate.

Then, an insulator 24 is buried on the conductive layer 26 in the trench 20 by the CVD method or the like, and the surface is flattened as shown in FIG. Further, the oxide film 21 on the n ⁺ cathode region 12 is selectively etched to expose the surface of the cathode region 12,
A cathode contact region 12a is formed. Thereafter, as shown in FIG. 6H, a cathode metal electrode 25 electrically connected to the n ⁺ cathode region 12 via the cathode contact region 12a is formed, and the gate and cathode of the SI element in another embodiment are formed. The area is complete.

In addition to the effect of the SI element of the embodiment shown in FIGS. 1 to 3, this SI element has the effect of further reducing the gate resistance by forming the conductive layer 26 on the polysilicon 15. is there.

In these examples, the gate structures of SI thyristors and SI transistors have been described.
It can also be applied to the gate structure of FETs and permeable base transistors. That is, the electrostatic induction switching element in this specification includes all switching elements whose current control mechanism is performed by electrostatic induction.

Further, in these embodiments, the SI element for high power was mainly described, but it goes without saying that the invention can be applied to the IC of the SI element for weak power.

〔The invention's effect〕

As described above, according to the present invention, the gate region can be formed by the polysilicon containing the impurity of the second conductivity type buried in the semiconductor substrate and the diffusion using the polysilicon as the diffusion source. Since it is composed of a diffusion layer, it is excellent in reverse breakdown voltage, all the channel regions can be formed using a semiconductor substrate, and the channel length and channel width of the channel regions can be formed with high accuracy. Further, there is an effect that the gate resistance becomes low and it is suitable for miniaturization.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method for manufacturing an SI element according to an embodiment of the present invention, FIG. 2 is a sectional view of an SI thyristor, FIG. 3 is a plan view of the SI element of the embodiment shown in FIG. FIG. 4 is a sectional view showing a method of manufacturing an SI element which is another embodiment of the present invention.
FIG. 6 is a sectional view showing an SI element having a conventional buried gate structure, FIG. 6 is a sectional view showing an SI element having a conventional planar structure, and FIG. 7 is a sectional view showing an SI element having a conventional grooved gate structure. . In the figure, 12 is an n ⁺ cathode region, 15 is doped polysilicon, 22 is a p ⁺ gate region, and 23 is a channel region. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (10)

(57) [Claims] 1. A first-conductivity-type semiconductor substrate having first and second principal surfaces, and a second-conductivity-type impurity buried in the semiconductor substrate with an insulating material. And a gate region formed of a diffusion layer of a second conductivity type formed around the polysilicon including the polysilicon, the gate region including the first region.
A thickness of the insulating material from the main surface of the semiconductor substrate is embedded in the second main surface side to be formed in the semiconductor substrate, and a portion of the semiconductor substrate between the gate regions is defined as a channel region. A first conductive type first main electrode region formed on the first main surface above the region, and a first or second conductive type second main electrode formed on the second main surface An electrode region, a first metal electrode electrically connected to the first main electrode region, formed on the first main electrode region and the insulating material, and electrically connected to the second main electrode region. And a second metal electrode that is electrically connected to the second main electrode region and is formed on the second main electrode region. 2. The static induction switching device according to claim 1, wherein the diffusion layer is formed around a bottom surface and a side surface of the polysilicon. 3. A first-conductivity-type semiconductor substrate having first and second main surfaces, and a second-conductivity-type impurity buried in the semiconductor substrate with an insulating material. And a gate region formed of a diffusion layer of a second conductivity type formed around the polysilicon and a stacked body of polysilicon and silicide containing the polysilicon,
A portion of the semiconductor substrate between the gate regions is defined as a channel region, a first conductivity type first main electrode region formed on the first main surface above the channel region, and the second main electrode region. An electrostatic induction switching device comprising: a first main electrode region of a second conductivity type or a second main electrode region of a second conductivity type formed on a main surface. 4. The static induction switching device according to claim 3, wherein the silicide and the lid are formed in a taper shape that opens upward. 5. (a) A first having a first and a second main surface.
And (b) forming a first main electrode region of a first conductivity type on the first main surface of the semiconductor substrate, and (c) the first main electrode region of the first conductivity type. A step of selectively removing one main electrode region and the semiconductor substrate to form a trench; (d) a step of forming polysilicon containing an impurity of a second conductivity type at the bottom of the trench; (e) Diffusing the impurity of the second conductivity type using the polysilicon as a diffusion source to form a diffusion layer around the polysilicon, the diffusion layer forming a gate region together with the polysilicon. (F) further comprising the step of burying the polysilicon in a bottom portion of the trench and covering the trench with an insulating material, wherein the gate region is formed from the first main surface by a thickness of the insulating material, Embedded in the main surface side of (G) forming a second main electrode region of the first or second conductivity type on the second main surface of the semiconductor substrate; and (h) the first Electrically connecting to the main electrode region to form a first metal electrode on the first main electrode region and on the insulating material; and (g) electrically connecting to the second main electrode region. And then the second
And a step of forming a second metal electrode on the main electrode region. 6. In the step (e), the diffusion layer is formed around the bottom surface and the side surface of the polysilicon.
The method for manufacturing an electrostatic induction switching device according to claim 5. 7. The step (d) includes a step of filling the trench with the polysilicon, and a step of partially removing the filled polysilicon with another trench wider and shallower than the trench. The method of manufacturing an electrostatic induction switching device according to claim 5, wherein the step (f) includes a step of filling the another trench with the insulating material. 8. (a) A first having a first and a second main surface.
And (b) forming a first main electrode region of a first conductivity type on the first main surface of the semiconductor substrate, and (c) the first main electrode region of the first conductivity type. A step of selectively removing one main electrode region and the semiconductor substrate to form a trench; (d) a step of forming polysilicon containing an impurity of a second conductivity type at the bottom of the trench; (e) Diffusing the impurity of the second conductivity type using the polysilicon as a diffusion source to form a diffusion layer around the polysilicon, the diffusion layer forming a gate region together with the polysilicon. (F) forming a silicide on the polysilicon, (g) burying the polysilicon and the silicide in the bottom of the trench and covering with an insulating material, (h) the semiconductor substrate of And a step of forming a second main electrode region of the first or second conductivity type on the second main surface. 9. The step (d) comprises a step of filling the trench with the polysilicon, and another step of filling the filled polysilicon with a taper shape in which an upper opening is wider and shallower than the trench. 9. The method of manufacturing an electrostatic induction switching device according to claim 8, further comprising: a step of removing the trench halfway, wherein the step (g) includes a step of filling the another trench with the insulating material. 10. A polysilicon layer containing a second conductivity type impurity and buried in the bottom of a plurality of trenches formed in parallel with the first surface of a first conductivity type semiconductor substrate, and the polysilicon layer. A gate electrode electrically connected to a side surface of the polysilicon layer and a second conductive type diffusion layer formed on the semiconductor substrate on the side surface, the bottom surface being in contact with the upper surface of the trench and the upper surface of the polysilicon layer. And the gate electrode is buried in the semiconductor substrate by being buried in the second surface side facing the first surface by the thickness of the insulating layer from the first surface, A first main electrode region of the first conductivity type formed on the first surface of the semiconductor substrate between the gate electrodes; and a second main electrode of the second conductivity type formed on the second surface of the semiconductor substrate. An electrode region, electrically connected to the first main electrode region A first metal electrode formed on the first main electrode region and on the insulating layer, and a second metal electrode electrically connected to the second main electrode region and formed on the second main electrode region. An electrostatic induction type switching element, comprising: