JP2687489B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to the structure of a high breakdown voltage transistor.

[Conventional technology]

Conventionally, in this type of transistor, a relatively deep N well 2 is formed in a region for forming a high breakdown voltage transistor in a P type semiconductor substrate 1 as shown in FIG. 5, and a P type source is diffused in the N well 2. A layer 8 and a P well 3 are formed, and a P type drain diffusion layer 7 is formed in the P well 3.

A method of manufacturing such a conventional high breakdown voltage transistor will be described below. The N well 2 is shown by a hatched portion in FIG. 6 (the hatched portion in the drawing is for convenience sake to show a mask pattern,
(Not shown in cross section), N in a state of being covered with the mask 9 on the semiconductor substrate 1 other than the element formation planned region.
It is formed by implanting mold ions into the substrate and performing high-temperature heat treatment for indentation. A P well 3 is formed inside the N well 2 so as to be shallower than the N well. Similarly to the method of forming the N well 2, the P well 3 is also formed by covering the substrate other than the P well forming region with a mask material, implanting P-type ions into the substrate, and then performing heat treatment. The P well 3 is formed at a position including a region which will be the P type drain diffusion layer 7 in the future.

Next, a field oxide film 4 for element isolation is formed except for the regions to be the source, drain and channel.

Next, the gate electrode 6 is formed through the gate oxide film 5 from a part of the field oxide film 4 between the source and the drain, over the channel portion.

Next, by using the field oxide film 4 and the gate electrode 6 as a mask, P-type ions are implanted at a high concentration into the substrate to form a P-type drain diffusion layer 7 and a P-type source diffusion layer 8 to form a high breakdown voltage transistor. To be done.

Here, by covering the P-type drain diffusion layer 7 with the P-well 3 and placing one end of the gate electrode 6 on the drain side on the field oxide film 4, it is possible to operate at 30 V or higher.

As shown by the hatched portion in FIG. 6, in the conventional example, since the ion implantation for forming the N well is performed in the entire high breakdown voltage transistor formation region, the N well concentration distribution from the source to the drain of the high breakdown voltage transistor is It is constant. The well concentration distribution in the BB ′ cross section of FIG. 6 is shown in FIG. 7, but the concentration distribution obtained by combining the N well and P well has a relatively steep concentration gradient at the well boundary. ing.

[Problems to be solved by the invention]

The conventional high breakdown voltage transistor described above has the following drawbacks. The breakdown voltage of the high breakdown voltage transistor is determined by the N well concentration and the P well concentration, and the lower the concentration, the higher the breakdown voltage can be. However, if the N well concentration is lowered, the N well under the field oxide film is inverted by the high voltage applied to the wiring, and the parasitic transistor composed of P well-N well-P type substrate becomes conductive, which causes leakage. In terms of circuit layout, it is necessary to design the parasitic transistor so that it does not conduct, which leads to an increase in area. Further, when the ion implantation amount of the N well is reduced to lower the N well concentration, the N well becomes shallower, and punch-through between the P well and the P type substrate is likely to occur. Although it is possible to lengthen the N-well pushing time to deepen the N-well, there is a problem that productivity is poor because heat treatment at high temperature for a long time is required. On the other hand, when the P well concentration is lowered, there is a drawback that the resistance of the P well portion becomes high and the current driving capability becomes low.

Further, as described in the article, since the well concentration gradient at the P well-N well boundary is relatively steep, there is a drawback that the withstand voltage fluctuates greatly due to an alignment error when the P well and the field oxide film are formed. There is also.

As described above, in the conventional structure, the manufacturing and design margin of the high breakdown voltage transistor is small, which leads to fluctuations in transistor characteristics, resulting in reliability problems.

[Means for solving the problem]

A semiconductor device according to the present invention includes a second conductivity type well formed in a first conductivity type semiconductor substrate, a first conductivity type well provided in the second conductivity type well, and the first conductivity type well. A drain region of the first conductivity type formed in the well of the first conductivity type, a source region of the first conductivity type formed in the well of the second conductivity type, and formed between the drain and the source region,
And an insulating film provided on the first conductivity type well,
A gate electrode formed on the insulating film, and an impurity concentration near the boundary region between the wells of the first and second conductivity types under the gate electrode region is selectively formed to be low. It is a feature.

According to the present invention as described above, the gradient of the ion concentration in the vicinity of the boundary region between the first and second conductivity type wells is relaxed and the breakdown voltage is improved.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
FIG. 1 is a vertical sectional view of a high breakdown voltage transistor portion showing a first embodiment of the present invention. N formed on the P-type semiconductor substrate 1
P well 3 is formed in well 2 and P well 3 is formed in N well 2.
The type source diffusion layer 8 and the P type drain diffusion layer 7 are formed in the P well 3. Further, a gate electrode is formed on the channel portion between the source and the drain via the field oxide film 4 and the gate oxide film 5. Here, the N well 2 is formed with a low well concentration around the boundary region between the P well 3 and the N well 2 directly below the gate electrode 6. The manufacturing process of this embodiment is the same as that shown in the prior art, but when the N well 2 is formed by ion implantation in order to realize the structure of the present invention, the shaded portion (second part) in FIG. The hatched portion in the drawing is a mask pattern for convenience sake and is not shown in cross section), and the substrate at the boundary between the N well 2 and the P well 3 in the channel portion under the gate electrode 6 is shown. A mask 9'is formed on the top of the substrate to prevent ions from being implanted into the substrate when the N well is formed. Therefore, the N well in the region where the ion implantation is not performed is formed by the diffusion by the subsequent heat treatment, so that the N well concentration distribution in the cross section AA 'in FIG. 2 shows the N well 2 and the P well 3 as shown in FIG. The concentration is low near the boundary. In this embodiment, under the same implantation heat treatment conditions as in the conventional case, the area where the N well concentration is the lowest is approximately 35 × 10 ¹⁵ cm ⁻² , which is about one third of that in the conventional example. Therefore, the well concentration distribution obtained by combining the N well 2 and the P well 3 is as shown by the broken line in FIG. 3, and the gradient is gentler than that of the broken line in FIG. Can be expected to improve.

In this embodiment, the pattern of the mask material at the time of ion implantation for forming the N well in the mask forming step is shown for convenience in order to show the mask pattern 9 ″ in FIG. 4 (the hatched area in FIG. 4 shows the mask pattern). However, the P well 3 is formed on the entire boundary region in contact with the N well 2. In this case, the N well 2 is formed in the entire boundary region between the N well 2 and the P well 3. Since the concentration can be reduced, not only can the breakdown voltage of the transistor be improved, but the N
The junction breakdown voltage between the well and P well can also be improved. Therefore, since the junction breakdown voltage between the N well and the P well is lower than the breakdown voltage in the drain-gate electrode region of the high breakdown voltage transistor, it is possible to prevent the breakdown voltage of the transistor from being limited by the junction breakdown voltage of the well.

Although the depth of the N well 2 may be slightly shallower in the region where the ion implantation is not performed when the N well is formed, the ion implantation amount and the heat treatment time are set in advance so that the N well 2 is sufficiently deep. There is no problem if you keep it. Further, it is apparent from the above description that the structure of the present invention does not increase the number of mask steps as compared with the conventional manufacturing method, and can be realized without changing the ion implantation conditions and the heat treatment conditions during the well formation.

Although the P-type semiconductor substrate is used in this embodiment, a semiconductor integrated circuit device in which the N-type high breakdown voltage transistor is formed on the N-type semiconductor substrate by replacing the P-type and N-type is also included in the scope of the present invention.

〔The invention's effect〕

As described above, in the present invention, it is possible to easily improve the withstand voltage of the high withstand voltage transistor, and at the same time, the ratio of the withstand voltage fluctuation due to the alignment error at the time of forming the well and field oxide film is small. The effect is that you can do it. In addition, since it is possible to easily set the withstand voltage and the drive current of the high breakdown voltage transistor to appropriate values, it is easy to optimize the characteristics when designing the transistor.

[Brief description of the drawings]

FIG. 1 is a vertical sectional view of a first embodiment of a high breakdown voltage transistor of the present invention, FIG. 2 is a plan view of the first embodiment, and FIG. 3 is a well concentration distribution in the AA 'section of FIG. FIG. 4, FIG. 4 is a plan view showing a second embodiment of the present invention, and FIG.
FIG. 6 is a vertical sectional view of a high breakdown voltage transistor according to a conventional technique, FIG. 6 is a plan view of a conventional example, and FIG. 7 is a diagram showing a well concentration distribution in a BB ′ cross section of FIG. 1 ... P-type semiconductor substrate, 2 ... N well, 3 ... P well, 4 ... field oxide film, 5 ... gate oxide film, 6
...... Gate electrode, 7 ... P-type drain diffusion layer, 8 ... P
Type source diffusion layer, 9,9 ′, 9 ″ …… Mask.

Claims (1)

(57) [Claims] A first conductive type semiconductor substrate formed on a first conductive type semiconductor substrate;
A well of conductivity type; a well of first conductivity type provided in the well of second conductivity type; a diffusion region of first conductivity type formed in the well of first conductivity type; A second diffusion region of a first conductivity type formed in a well of a conductivity type, and a first diffusion region formed between the first and second diffusion regions, and
An insulating film provided on the conductive type well and an electrode formed on the insulating film, and the first electrode under the electrode region.
And a semiconductor device characterized in that the impurity concentration in the vicinity of the boundary region between the wells of the second conductivity type is formed selectively low.