JPH01253273A - Bipolar transistor - Google Patents

Abstract

PURPOSE:To decrease base-to-collector capacity by a method wherein a second base region, lower in concentration than a first base region just under an emitter region, is formed to be in contact with a high concentration buried collector layer. CONSTITUTION:An N<+>-type buried collector layer 2 is provided on a P-type silicon substrate 1 and, in contact with the N<+>-type buried collector Iayer 2, a P<->-type base region 6 and P<+>-type base region 7 are formed. A P<++>-type base region 8 is formed on the P<->-type base region 6 and, on the P<+>-type base region 7, an N<+>-type emitter region 9 is formed. Further, surrounding the element forming region, a P-type channel stopper layer 3 is formed to serve as a dielectric isolating region. In a bipolar type transistor designed as such, base- to-collector capacity may be decreased and base resistance may also be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar transistor capable of high speed and high current operation.

[Prior Art] Conventionally, in a semiconductor device having a bipolar transistor, it is necessary to electrically isolate the elements, so as shown in FIG.
''Epitaxial layer 4 is made long, this epitaxial layer 4 is used as a collector region, and a P'''' type base region 7 and an N+ type emitter region 9 are formed in the epitaxial layer 4.
form. Then, in order to reduce the series resistance between the transistor operating region and the collector electrode of the device, an N''-type buried collector layer 2 is formed at the boundary between the epitaxial layer 4 and the substrate 1, and around the device. A P-type channel stopper layer 3 was provided as an insulating isolation region.

[Problems to be Solved by the Invention] Generally, in order to increase the speed of a bipolar transistor, it is effective to shorten the traveling distance of carriers by reducing the depth of the base region 7. During current operation, the effective base depth increases due to a phenomenon called the Kirk effect, so it is necessary to suppress the above phenomenon by increasing the impurity concentration in the epitaxial layer 4, which is the collector region.

However, in order to reduce the depth of the base region 7, it is necessary to increase the impurity concentration in the base region 7 so as not to lower the breakdown voltage due to bunch through between the emitter and the collector. Further, as described above, since the impurity concentration in the epitaxial layer 4 is increased, the junction capacitance between the collector and the base increases significantly. For this reason,
The structure of conventional bipolar transistors has a major drawback in increasing the speed of bipolar transistors. Furthermore, since the concentration of the epitaxial layer 4 is high, the concentration of the channel stopper layer 3 in the element isolation region must also be high, and the capacitance also increases when forming a MOS transistor. Increasing the concentration of the epitaxial layer 4 in this manner has been a major drawback not only in increasing the speed of the bipolar transistor but also in composing it with other devices.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a bipolar transistor that can operate at high speed and operate at high current.

[Means for Solving the Problems] A bipolar transistor according to the present invention includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type covering the semiconductor substrate; a heavily doped buried collector region of a second conductivity type selectively formed in a boundary portion of a semiconductor substrate; a first base region of a first conductivity type selectively formed in the semiconductor layer; and a second conductivity type emitter region formed above the region, wherein the first base region directly below the emitter region is formed so as to be in contact with the highly doped buried collector region. and the first
A second base region having a lower impurity concentration of the first conductivity type than the base region of the base region is formed in contact with the buried collector region of the second conductivity type at a position not directly under the emitter region, and is in contact with the buried collector region of the second conductivity type.
Above the base region, a first
A third base region having a high conductivity type impurity concentration is formed.

[Operations] In the present invention, the first base region directly below the emitter region is formed so as to be in contact with the highly doped buried collector region,
A second base region having a lower impurity concentration of the first conductivity type than the first base region is formed in contact with the buried collector region at a position not directly under the emitter region, and has a lower impurity concentration of the first conductivity type than the first base region. A third base region is formed above the second base region with an impurity concentration of .

In this way, since the low concentration second base region contacts the high concentration buried collector region, the base-collector capacitance is reduced. Furthermore, since the third base region can be made highly concentrated, the base resistance value is reduced. Furthermore, the first
Since the base region is in contact with the highly doped buried collector region, the so-called Kirk effect can be suppressed. Therefore,
In the present invention, it is possible to increase the speed and current of a bipolar transistor.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a longitudinal sectional view showing a bipolar transistor according to an embodiment of the present invention.

An N+ type buried collector layer 2 is provided on a P type silicon substrate 1, and a P− type base region 6 and a P″− type base region 7 are formed in contact with it. A P+" type base region 8 is formed on the P+ type base region 7, and an N+ type emitter region 9 is formed on the P+ type base region 7. Further, a P-type channel stopper layer 3 is provided as an insulating isolation region so as to surround this element formation region.

In the bipolar transistor configured in this manner, a P− type base region 6 having a lower concentration than the P+ type base region 7 directly under the N+ type emitter region 9 is provided in contact with the N+ type buried collector layer 2. Therefore, the capacitance between the base and collector can be reduced.

Further, on the low concentration P-type base region 6, there is a high concentration p-type base region 6.
Since the + + type base region 8 is provided, the base resistance is reduced.

Furthermore, since the P+ type base region 7 directly under the N1 type emitter region 9 is in contact with the highly doped N+ type buried collector layer 2, the so-called Kirk effect is suppressed, and high-speed and high-current operation is possible. It is possible.

Next, a method for manufacturing the above bipolar transistor will be described.

FIG. 2 is a cross-sectional view showing this manufacturing method in the order of steps. First, as shown in FIG. 2(a), an N+ type buried collector layer 2 and a P type channel stopper layer 3 are formed on a P type silicon substrate 1 by ion implanting, for example, arsenic and boron, respectively.

Next, as shown in FIG. 2(b), an N-type epitaxial layer 4 is grown, and using the photoresist 11 as a mask, a P-type layer is formed by, for example, boron ion implantation into the areas other than the emitter and collector forming regions. A base region 6 is formed.

Next, as shown in FIG. 2(c), after forming an oxide film 5 by the usual LOCO3 method, a photoresist 11 covering the area other than the area where the base area is to be formed is re-deposited. Then, for example, by implanting boron ions, a P+" type base region 8 and a P+ type base region 7, which are shallower and have a higher concentration than the previous P- type base region 6, are formed.

Thereafter, as shown in FIG. 2(d), using the newly formed photoresist 11 as a mask, for example, arsenic ions are implanted into the surface side of the P+ type base region 7.
Forming a type emitter region 9 Next, a normal contact is opened in the oxide film 5 and a wiring layer of a metal electrode 10 is formed to obtain a bipolar transistor having the structure shown in FIG.

FIGS. 3(a) to 3(d) are cross-sectional views showing, in order of steps, another method of manufacturing a bipolar transistor having the above-described structure. FIG. 3(a): As shown, in order to form an N+ type buried collector layer 2 and a P-type channel stopper layer 3 on a P-type silicon substrate 1, the process is similar to that shown in FIG. 2(a). Then, arsenic and boron ions are implanted into the substrate surface, respectively.

Next, as shown in FIG. 3(b), after forming an N-type epitaxial layer 4, an oxide film 5 is formed by the usual LOCO8 method.

Thereafter, as shown in FIG. 3(C), areas other than the emitter and collector forming regions are masked with a photoresist 11, and for example, boron ion implantation with low ion implantation energy and high concentration boron, and high concentration boron ion implantation with high ion implantation energy are performed. By performing ion implantation of boron at a low concentration, a P- type base region 6 and a P+ type base region 8 are formed.

Next, as shown in FIG. 3(d), a new photoresist 11 with an open emitter formation area is formed, and using this photoresist 11 as a mask, the emitter formation area is exposed.
P+ type base region 7 is formed by implanting boron ions at an intermediate concentration between the two types of boron ion implantation concentrations in the step of FIG. 3(C). After that, for example,
A shallow N+ type emitter region 9 is formed by arsenic ion implantation. By employing such a method, the bipolar transistor according to the embodiment of the present invention can be manufactured.

[Effects of the Invention] As explained above, according to the present invention, the second base region having a lower concentration than the first base region directly below the emitter region is provided in contact with the highly doped buried collector layer. Since the base-collector capacitance can be reduced and at the same time the concentration of the third base region above the low concentration second base region can be increased, the base resistance value is reduced. Further, since the first base region under the emitter region is in contact with the highly doped buried collector layer, the so-called Kirk effect phenomenon can be suppressed, so that according to the present invention, the speed increase and the current increase It is possible to obtain a bipolar type transistor that is possible.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view showing a bipolar transistor according to an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views showing a method for manufacturing a bipolar transistor according to an embodiment of the present invention in order of steps. 3(a) to 3(d) are cross-sectional views showing another manufacturing method in the order of steps, and FIG. 4 is a cross-sectional view showing a conventional bipolar transistor. 1; P type silicon substrate, 2; N+ type buried collector layer, 3
P-type channel stopper layer, 4; N-epitaxial layer, 5; oxide film, 6. P− type base region, 7; P+ type base region, 8; P+“ type base region, 9; N+ type emitter region, 10; metal electrode, 11; photoresist 1; P type silicon toad @ 6; P− type base Region 2; N+ type buried flexor layer 7; P+ type base region 3; PW channel store 1 end 8: I/+ type base region 4; N-m epitaxial layer 9;
N+! l! Emi/re area 5; oxidation vA
10; Metallic wire 1 Figure 1: P-type silicon plate 4; N-type epitaxial layer 2; N+-type buried collector layer 6; P-type base W region 3; PM channel resist 7 11; Photoresist (a) (b) Fig. 2 (1) 5; Oxidation result 7; P+ type base region 8; F? ``!1 Base II region 9; N nine deaf emitter region 11: Photoresist (C) Figure 2 (2) 1: P-type silicon vine plate 2; N+ type buried collector layer 3; P-type channel resist/ 1 4; N- type epitaxial layer 5; oxide film (a) (b) Fig. 3 (1) 6: P- type base region 9; N+ type emitter region 8; Z+ type base region (d) 3 Figure (2)

Claims (1)

[Claims] (1) A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type covering the semiconductor substrate, and a second conductivity type selectively formed at the boundary between the second conductivity type semiconductor layer and the semiconductor substrate. a heavily doped buried collector region of the mold, a first base region of a first conductivity type selectively formed in the semiconductor layer, and an emitter of a second conductivity type formed above the first base region. In the bipolar transistor having a region, the first base region directly below the emitter region is formed so as to be in contact with the heavily doped buried collector region, and a region of a first conductivity type is formed from the first base region. A second base region with a low impurity concentration is formed in contact with the second conductivity type buried collector region at a position other than directly under the emitter region, and a second base region with a lower impurity concentration than the first base region is formed above the second base region. A bipolar transistor characterized in that a third base region having a high impurity concentration of one conductivity type is formed.