KR100253353B1 - Method of fabricating mos transistor - Google Patents

Method of fabricating mos transistor Download PDF

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KR100253353B1
KR100253353B1 KR1019970061440A KR19970061440A KR100253353B1 KR 100253353 B1 KR100253353 B1 KR 100253353B1 KR 1019970061440 A KR1019970061440 A KR 1019970061440A KR 19970061440 A KR19970061440 A KR 19970061440A KR 100253353 B1 KR100253353 B1 KR 100253353B1
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well
mos transistor
region
field oxide
forming
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KR1019970061440A
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Korean (ko)
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KR19990040927A (en
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김성진
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

PURPOSE: A method of fabricating a MOS transistor is provided to be able to shield current passing through a well for preventing leakage current by forming a current limit region on a bottom of an ion implantation region, thereby enhancing the characteristics and reliability of the transistor. CONSTITUTION: A p well(2) is formed by implanting impurity ions into a substrate(1), a field oxide(3) is deposited on the p well(2). Then, a current limit region(9) is formed on a bottom of the p well(2) by implanting n type impurity ions of high density into the p well(2). Next, an NMOS transistor(10) of LDD structure on the p well exposed between the field oxides(3), and a p type ion implantation region(8) is formed by implanting p type impurity ions of high density into the p well exposed between the NMOS transistor(10) and adjacent field oxide(3).

Description

모스 트랜지스터 제조방법MOS transistor manufacturing method

본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 특히 기판의 하부에 이온주입층을 형성하여 모스 트랜지스터의 동작시 기판으로 흐르는 기생전류를 방지하는데 적당하도록 한 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor manufacturing method, and more particularly, to a MOS transistor manufacturing method in which an ion implantation layer is formed under a substrate so as to be suitable for preventing parasitic current flowing to the substrate during operation of the MOS transistor.

일반적으로, 모스 트랜지스터는 기판의 상부에 엔형 웰(WELL) 및 피형 웰(WELL)을 형성하고, 그 상부에 각 타입에 맞는 모스 트랜지스터를 제조하게 된다. 즉, 엔형 웰에는 피모스 트랜지스터를 제조하고, 피형 웰에는 엔모스 트랜지스터를 제조하게 된다. 이중 주로 사용되는 모스 트랜지스터는 엔모스 트랜지스터이며, 이는 그 게이트에 고전위의 전압을 인가하여 소스와 드레인 사이의 피웰에 채널을 형성하는 동작을 한다.In general, a MOS transistor forms an N type well WELL and a well type WELL on a substrate, and manufactures a MOS transistor for each type thereon. In other words, a PMOS transistor is manufactured in the N well, and an NMOS transistor is manufactured in the well. The most commonly used MOS transistor is an NMOS transistor, which operates to apply a high-potential voltage to its gate to form a channel in a pewell between a source and a drain.

이와 같이 소스와 드레인사이에 전하가 이동할 수 있는 채널은 게이트전극에 고전위의 전압이 인가되면, 게이트 산화막의 하부에는 피웰에 전자홀 결합쌍에서 전자와 홀이 분리되고, 그 분리된 전자가 모여 형성된다. 이때, 분리된 홀은 피웰을 통해 이동하게 된다. 즉, 기판에는 마치 바이폴라 트랜지스터가 형성된 것과 동일한 효과로 누설전류가 발생하게 된다.As described above, when a high potential voltage is applied to the gate electrode, electrons and holes are separated from a pair of electron hole bonds to the pewell at the lower portion of the gate oxide layer, and the separated electrons are collected. Is formed. At this time, the separated hole is moved through the pewell. That is, the leakage current is generated in the substrate as if the bipolar transistor is formed.

상기 누설전류는 모스 트랜지스터의 동작에 심각한 영향을 주게 되며, 종래에는 이를 제거하기 위해 피웰에 배선을 형성하여 누설전류를 외부로 이동시켰으며, 이와 같은 종래 모스 트랜지스터 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The leakage current has a serious effect on the operation of the MOS transistor, and in the related art, a wiring is formed in the pewell to remove the current, and the leakage current is moved to the outside. Referring to the accompanying drawings of the conventional MOS transistor manufacturing method, It will be described in detail as follows.

도1은 종래 모스 트랜지스터의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 불순물 이온주입을 통해 피웰(2)을 형성하고, 그 피웰(2)의 상부에 소자간의 절연을 위한 필드산화막(3)을 증착하는 단계와; 상기 필드산화막(3)사이에 노출된 피웰(2)의 상부에 게이트산화막과 다결정실리콘을 순차적으로 증착하고, 사진식각공정을 통해 그 게이트산화막과 다결정실리콘의 일부를 식각하여 게이트(4)를 형성하는 단계와; 상기 게이트(4)와 필드산화막(3)의 사이에 노출된 피웰(2)에 저농도 엔형 불순물 이온을 주입하여 저농도 소스 및 드레인(5)을 형성하는 단계와; 상기 게이트(4)의 측면에 측벽(6)을 형성하는 단계와; 상기 측벽(6)과 필드산화막(3)의 사이 피웰(2)에 형성한 저농도 소스 및 드레인(5)에 고농도 엔형 불순물 이온을 이온주입하여 고농도 소스 및 드레인(7)을 형성하여 모스 트랜지스터를 제조하는 단계와; 상기 모스 트랜지스터가 제조되지 않은 노출된 피웰(2)영역에 고농도 피형 불순물 이온을 이온주입하여 고농도 피형 이온주입영역(8)을 형성하는 단계를 포함하여 구성된다.FIG. 1 is a cross-sectional view of a conventional MOS transistor. As shown in FIG. 1, a pwell 2 is formed on an upper surface of a substrate 1 by implanting impurity ions, and a field oxide film for insulating between devices is formed on the upper surface of the pwell 2. (3) depositing; The gate oxide film and the polysilicon are sequentially deposited on the exposed Pwell 2 between the field oxide films 3, and the gate oxide film and a portion of the polysilicon are etched through a photolithography process to form the gate 4. Making a step; Forming a low concentration source and drain (5) by implanting low concentration en-type impurity ions into the pewell (2) exposed between the gate (4) and the field oxide film (3); Forming a side wall (6) on the side of the gate (4); A high concentration source and drain 7 are formed by ion implanting high concentration en-type impurity ions into the low concentration source and drain 5 formed in the piwell 2 between the sidewall 6 and the field oxide film 3 to form a MOS transistor. Making a step; And implanting a high concentration of the doped ion implantation region 8 by ion implanting a high concentration of the doped impurity ions into the exposed pewell 2 region in which the MOS transistor is not manufactured.

이하, 상기와 같이 구성된 종래 모스 트랜지스터 제조방법을 좀 더 상세히 설명하면 다음과 같다.Hereinafter, the conventional MOS transistor manufacturing method configured as described above will be described in more detail.

먼저, 기판(1)의 상부에 피형 불순물 이온을 이온주입하여 피웰(2)을 형성한다.First, the pwell 2 is formed by ion implanting the impurity ions into the upper portion of the substrate 1.

그 다음, 상기 피웰(2)의 상부에 로코스(LOCOS)공정을 통해 다수의 필드산화막(3)을 증착하여, 소자가 형성될 영역을 정의하고, 그 상부에 형성되는 소자를 전기적으로 분리시킨다.Next, a plurality of field oxide films 3 are deposited on the Pwell 2 through a LOCOS process to define regions where devices are to be formed, and to electrically separate the devices formed thereon. .

그 다음, 상기 필드산화막(3)의 사이에 노출된 피웰(2)의 상부에 게이트산화막과 다결정실리콘을 순차적으로 증착한 후, 사진식각공정을 통해 상기 노출된 피웰(2)의 중심부에 위치하는 게이트(4)를 형성한다.Subsequently, a gate oxide film and polysilicon are sequentially deposited on the exposed pewells 2 between the field oxide films 3, and then positioned at the center of the exposed pewells 2 through a photolithography process. The gate 4 is formed.

그 다음, 상기 게이트(4)의 측면하부 피웰(2)에 저농도 엔형 불순물 이온을 이온주입하여 저농도 소스 및 드레인(5)을 형성한다.Thereafter, low concentration en-type impurity ions are ion-implanted into the lower side pwell 2 of the gate 4 to form the low concentration source and drain 5.

그 다음, 상기 게이트(4), 저농도 소스 및 드레인(5), 필드산화막(3)의 상부전면에 절연층을 증착하고, 이를 건식식각하여 상기 게이트(4)의 측면에 측벽(6)을 형성한다.Next, an insulating layer is deposited on the upper surface of the gate 4, the low concentration source and drain 5, and the field oxide film 3, and dry-etched to form sidewalls 6 on the side of the gate 4. do.

그 다음, 상기 측벽(6)과 필드산화막(3)의 사이에 노출된 저농도 소스 및 드레인(5)의 일부에 고농도 엔형 불순물 이온을 이온주입하여 고농도 소스 및 드레인(7)을 형성하여 LDD구조의 엔모스 트랜지스터를 제조한다.Next, a portion of the low concentration source and drain 5 exposed between the sidewall 6 and the field oxide film 3 is ion-implanted to form a high concentration source and drain 7 to form a high concentration source and drain 7. The NMOS transistor is manufactured.

그 다음, 부분적인 이온주입공정을 통해 상기 엔모스 트랜지스터가 제조되지 않은 필드산화막(3)사이에 노출된 피웰(2)에 고농도 피형 불순물 이온을 이온주입하여 이후에 기판전압이 인가되는 고농도 피형 이온주입영역(8)을 형성한다. 이때, 이온주입영역(8)은 피웰(2)에 직접 전극이 접속되는 경우 그 접촉저항이 커 피웰에 흐르는 전류를 외부로 이동시키지 못하게 되기 때문에 고농도의 이온을 주입하여 전극과의 접촉저항을 줄이는 역할을 한다.Subsequently, a high concentration of the dopant ion is implanted into the pwell 2 exposed between the field oxide layer 3 in which the NMOS transistor is not manufactured through a partial ion implantation process, and then a high concentration of the dopant ion is applied. The injection region 8 is formed. In this case, when the electrode is directly connected to the pewell 2, the ion implantation region 8 does not move the current flowing through the pewell to the outside, thereby injecting a high concentration of ions to reduce the contact resistance with the electrode. Play a role.

상기와 같은 구조에서는 피웰(2)과 고농도 소스 및 드레인(7)에 의해 NPN 바이폴라 트랜지스터가 형성된 것과 동일한 효과로, 채널 형성을 위해 게이트(4)에 고전위의 전압이 인가되면, 상기 기생 바이폴라 트랜지스터에 의해 과도한 전류가 피웰로 흐르게 되며, 이는 게이트(4)의 길이 즉, 채널길이가 짧아질수록 심화된다.In the above structure, when the high potential voltage is applied to the gate 4 to form a channel, the parasitic bipolar transistor is formed in the same effect as the NPN bipolar transistor is formed by the Pwell 2 and the high concentration source and drain 7. Excessive current flows into the pewell, which deepens as the length of the gate 4, i.e., the channel length becomes shorter.

상기한 바와 같이 종래 모스 트랜지스터 제조방법은 기생 바이폴라 트랜지스터를 형성시켜, 그 기생 바이폴라 트랜지스터의 베이스 에미터간 전압이 0.6V이상이 되면 웰에 흐르는 전류가 증가하고, 이는 소자의 신뢰성 및 래치업(LATCH-UP)현상을 가속시켜 모스 트랜지스터의 특성을 열화시키는 문제점이 있었다.As described above, the conventional MOS transistor manufacturing method forms a parasitic bipolar transistor, and when the voltage between the base emitters of the parasitic bipolar transistor becomes 0.6 V or more, the current flowing in the well increases, which is related to device reliability and latch-up. There is a problem of degrading the characteristics of the MOS transistor by accelerating the UP phenomenon.

이와 같은 문제점을 감안한 본 발명은 웰을 통해 흐르는 전류를 차단할 수 있는 모스 트랜지스터 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a method of manufacturing a MOS transistor that can block a current flowing through a well.

도1은 종래 모스 트랜지스터의 단면도.1 is a cross-sectional view of a conventional MOS transistor.

도2a 내지 도2c는 본 발명 모스 트랜지스터 제조공정 수순단면도.2A to 2C are cross-sectional views of a MOS transistor manufacturing process of the present invention.

도3은 도2a 내지 도2c에 의해 제조되는 모스 트랜지스터의 등가회로도.Fig. 3 is an equivalent circuit diagram of a MOS transistor manufactured by Figs. 2A to 2C.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

1:기판 2:피웰1: Substrate 2: Pewell

3:필드산화막 8:이온주입영역3: field oxide film 8: ion implantation zone

9:전류제한영역9: Current limit area

상기와 같은 목적은 기판의 상부에 이온주입공정으로 웰을 형성하는 웰형성단계와; 웰의 상부에 필드산화막을 증착하는 영역설정단계와; 상기 필드산화막의 사이에 노출된 웰의 일측 상부에 모스 트랜지스터를 형성하는 모스 트랜지스터 제조단계와; 필드산화막의 사이에 노출된 웰의 타측에 전극연결시 접촉저항을 감소시키는 이온주입영역을 형성하는 이온주입영역 형성단계를 포함하여 이루어지는 모스 트랜지스터 제조방법에 있어서, 상기 영역설정단계 후에 필드산화막의 사이에 노출된 웰의 하부에 전류제한영역을 형성하는 전류제한영역 형성단계를 더 포함하여 기생 바이폴라 트랜지스터의 전류흐름을 차단하는 기생 다이오드가 더 형성되도록 함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a well forming step of forming a well in the ion implantation process on the upper portion of the substrate; A region setting step of depositing a field oxide film on the wells; A MOS transistor manufacturing step of forming a MOS transistor on one side of the well exposed between the field oxide films; A method of manufacturing an MOS transistor comprising forming an ion implantation region for reducing contact resistance when connecting an electrode to the other side of a well exposed between field oxide films, wherein the MOS transistor is formed after the region setting step. It is achieved by forming a parasitic diode to block the current flow of the parasitic bipolar transistor further comprising a current limiting region forming step of forming a current limiting region in the lower part of the well exposed to When described in detail with reference to as follows.

도2a 내지 도2c는 본 발명 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 불순물 이온을 이온주입하여 피웰(2)을 형성하고, 그 피웰(2)의 상부에 필드산화막(3)을 증착하는 단계(도2a)와; 상기 필드산화막(3)의 사이에 노출된 피웰(2)에 고농도 엔형 불순물 이온을 고에너지로 이온주입하여 그 피웰(2)의 하부에 전류제한영역(9)을 형성하는 단계(도2b)와; 상기 필드산화막(3)의 사이에 노출된 피웰의 상부에 LDD구조의 엔모스 트랜지스터(10)를 제조하고, 상기 엔모스 트랜지스터(10)와 인접한 필드산화막(3) 사이에 노출된 피웰(2)에 고농도 피형 불순물 이온을 이온주입하여 고농도 피형 이온주입영역(8)을 형성하는 단계(도2c)로 이루어진다.2A to 2C are cross-sectional views illustrating a manufacturing process of the MOS transistor according to the present invention. As shown in FIG. 2A to 2C, an impurity ion is implanted into an upper portion of the substrate 1 to form a pewell 2, and an upper portion of the pewell 2 is illustrated. Depositing a field oxide film 3 on the substrate (FIG. 2A); Implanting a high concentration of en-type impurity ions with high energy into the pewell 2 exposed between the field oxide films 3 to form a current limiting region 9 under the pewell 2 (FIG. 2B) and ; An NMOS transistor 10 having an LDD structure is manufactured on an upper part of the pewell exposed between the field oxide film 3, and the pewell 2 exposed between the NMOS transistor 10 and the adjacent field oxide film 3. Ion implantation of highly concentrated dopant ions to form a highly concentrated dopant ion implantation region 8 (FIG. 2C).

이하, 상기와 같이 구성된 본 발명 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the MOS transistor manufacturing method of the present invention configured as described above will be described in more detail.

먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 제조할 모스 트랜지스터의 소스 및 드레인과는 그 형이 반대인 불순물 이온을 이온주입하여 웰을 형성한다. 즉, 엔모스 트랜지스터를 제조하기 위해 피형 불순물 이온을 이온주입하여 피웰(2)을 형성한다.First, as shown in FIG. 1A, a well is formed by ion implantation of impurity ions having a type opposite to that of a MOS transistor to be manufactured on the substrate 1. That is, in order to manufacture the NMOS transistor, the implanted ion impurity ions are implanted to form the pewell 2.

그 다음, 상기 피웰(2)의 상부에 로코스(LOCOS)공정을 통해 필드산화막(3)을 형성한다.Next, the field oxide layer 3 is formed on the pewell 2 through a LOCOS process.

그 다음, 도2b에 도시한 바와 같이 상기 필드산화막(3)의 사이에 노출된 피웰(2)에 고농도 엔형 불순물 이온을 고에너지로 이온주입하여 피웰(2)의 하부 영역에 전류제한영역(9)을 형성한다.Next, as shown in FIG. 2B, a high concentration of en-type impurity ions are implanted into the pwell 2 exposed between the field oxide films 3 at high energy so as to provide a current limiting region 9 in the lower region of the pwell 2. ).

이때, 전류제한영역(9)은 제조하려는 모스 트랜지스터의 형과 동일한 형의 불순물이온을 주입하여 형성한다.At this time, the current limiting region 9 is formed by implanting impurity ions of the same type as that of the MOS transistor to be manufactured.

그 다음, 도2c에 도시한 바와 같이 상기 그 하부에 전류제한영역(9)이 형성된 피웰(2)의 상부에 엔모스 트랜지스터(10)를 제조하고, 그 엔모스 트랜지스터(10)와 인접한 필드산화막(3)의 사이에 노출된 피웰(2)의 상부에 고농도 피형 불순물 이온을 이온주입하여 이온주입영역(8)을 형성한다.Next, as shown in FIG. 2C, the NMOS transistor 10 is manufactured on the Pwell 2 having the current limiting region 9 formed thereon, and the field oxide film adjacent to the NMOS transistor 10 is formed. An ion implantation region 8 is formed by ion implantation of highly concentrated cortical impurity ions on the upper part of the pewell 2 exposed between (3).

또한, 도3은 도2c에 도시한 본 발명 모스 트랜지스터 제조방법으로 제조한 모스 트랜지스터의 등가회로도로서, 이에 도시한 바와 같이 엔모스 트랜지스터(10)의 고농도 소스 및 드레인, 피웰(2), 전류제한영역(9)에 의해 베이스가 상호접속되고, 에미터에는 드레인 또는 소스에 인가되는 전압을 인가받는 NPN 바이폴라 트랜지스터(BT1),(BT2)를 형성하게 되나, 각 전류제한영역(9)과 그 하부의 피웰(2)에 의해 다이오드(D2,D4)가 형성되어 전류의 흐름을 차단하게 된다. 여기서 미설명 부호 R1은 피웰(2)의 저항성분이며, BT3는 이온주입영역(8), 이온주입영역(8) 하부의 전류제한영역(9), 피웰(2)에 의한 PNP 바이폴라 트랜지스터이며, D1, D3는 각각 엔모스 트랜지스터(10) 하부의 피웰(2)과 전류제한영역(9), 이온주입영역(8)과 전류제한영역(9)에 의한 다이오드를 나타낸다.FIG. 3 is an equivalent circuit diagram of a MOS transistor manufactured by the method of manufacturing the MOS transistor of the present invention shown in FIG. 2C. As shown in FIG. 3, the high concentration source and drain of the NMOS transistor 10, the pewell 2, and the current limit are shown. The bases are interconnected by the regions 9, and the emitters form NPN bipolar transistors BT1, BT2 to which a voltage applied to the drain or source is applied, but each current limiting region 9 and its lower portion. Diodes (D2, D4) are formed by the Pwell 2 of the to block the flow of current. Here, reference numeral R1 is a resistance component of the pewell 2, BT3 is a PNP bipolar transistor by the ion implantation region 8, the current limiting region 9 below the ion implantation region 8, the pewell 2, D1 and D3 represent diodes formed by the Pwell 2, the current limiting region 9, the ion implantation region 8 and the current limiting region 9 under the NMOS transistor 10, respectively.

상기한 바와 같이 본 발명은 모스 트랜지스터와 기판전압의 인가를 위한 이온주입영역의 하부에 전류제한영역을 형성하여, 모스 트랜지스터의 동작시 기생 바이폴라 트랜지스터 외에 그 기생 바이폴라 트랜지스터를 통해 흐르는 전류를 차단하는 기생 다이오드를 더 형성시켜, 모스 트랜지스터의 동작으로 기판에 누설전류가 발생하는 것을 방지함으로써, 소자의 특성 및 신뢰도를 향상시키는 효과가 있다.As described above, the present invention forms a current limiting region under the ion implantation region for the application of the MOS transistor and the substrate voltage, thereby blocking the current flowing through the parasitic bipolar transistor in addition to the parasitic bipolar transistor during operation of the MOS transistor. By further forming a diode to prevent leakage current from occurring in the substrate by the operation of the MOS transistor, there is an effect of improving the characteristics and reliability of the device.

Claims (2)

기판의 상부에 이온주입공정으로 웰을 형성하는 웰형성단계와; 웰의 상부에 필드산화막을 증착하는 영역설정단계와; 상기 필드산화막의 사이에 노출된 웰의 일측 상부에 모스 트랜지스터를 형성하는 모스 트랜지스터 제조단계와; 필드산화막의 사이에 노출된 웰의 타측에 전극연결시 접촉저항을 감소시키는 이온주입영역을 형성하는 이온주입영역 형성단계를 포함하여 이루어지는 모스 트랜지스터 제조방법에 있어서, 상기 영역설정단계 후에 필드산화막의 사이에 노출된 웰의 하부에 전류제한영역을 형성하는 전류제한영역 형성단계를 더 포함하여 된 것을 특징으로 하는 모스 트랜지스터 제조방법.Forming a well by an ion implantation process on an upper portion of the substrate; A region setting step of depositing a field oxide film on the wells; A MOS transistor manufacturing step of forming a MOS transistor on one side of the well exposed between the field oxide films; A method of manufacturing an MOS transistor comprising forming an ion implantation region for reducing contact resistance when connecting an electrode to the other side of a well exposed between field oxide films, wherein the MOS transistor is formed after the region setting step. And a current limiting region forming step of forming a current limiting region in a lower portion of the well exposed to the MOS transistor. 제 1항에 있어서, 상기 전류제한영역 형성단계는 웰에 그 웰과는 형이 다른 고농도 불순물 이온을 고에너지로 주입하여 된 것을 특징으로 하는 모스 트랜지스터 제조방법.The method of claim 1, wherein the forming of the current limiting region is performed by implanting high concentration impurity ions having a different type from the well into the well with high energy.
KR1019970061440A 1997-11-20 1997-11-20 Method of fabricating mos transistor KR100253353B1 (en)

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