JPH07153860A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to provide an N-channel DMOS transistor having stable electric characteristics without specially adding production processes by forming a high concentration P-type isolation region between elements and, at the same time, forming a high concentration P-type buried in region. CONSTITUTION:A high concentration P-type buried region 30 is formed in a DMOS transistor forming region of a semiconductor substrate 5 by diffusing P-type impurities and, at the same time, a high concentration P-type isolation region between elements 51 is formed in a bipolar transistor forming region. A P-type body region 31 reaching the P-type buried region 30 is formed on the surface portion of a semiconductor substrate 5 of the DMOS transistor forming region. Also, an N-channel DMOS transistor 3 equipped with a P-type back gate region 34 and an N-type source.drain region 33 is formed in the P-type body region 31, and a bipolar transistor 1 is formed. By doing this, the N-channel DMOS transistor can be produced without specially adding production processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device in which an N channel DMOS transistor and a bipolar transistor are formed on the same semiconductor substrate.

[0002]

2. Description of the Related Art DMOS transistors (double diffused MOS
Transistors) are used for high current and high breakdown voltage applications. For example, in the lateral N-channel DMOS transistor therein, as shown in FIG. 11, an N-type epitaxial layer 7 is formed on the surface portion of a semiconductor substrate 5, and in this epitaxial layer 7, a P-type body region 31 and one N-type body region 31 are formed. Type source
A drain region 32 is formed, and another N-type source / drain region 33 and a P-type back gate region 34 for stabilizing the potential of the source / drain region 33 are formed adjacent to each other in the body region 31, and both sources are formed. A gate electrode 35 with the gate insulating film 8 interposed between the drain regions 32 and 33
It has a structure in which

Here, the N-channel DMOS as described above is used.
Due to the structure of the transistor, a parasitic NPN transistor composed of an N-type source / drain region 33, a P-type body region 31, and an N-type epitaxial layer 7 is formed in the vertical direction, and when this parasitic transistor operates. Has a problem that the source-drain breakdown voltage BVDS of the N-channel DMOS transistor becomes unstable.

[0004]

Therefore, in the prior art, P
A high-concentration P-type region 38 is formed under the mold body region 31 to prevent the operation of the parasitic transistor. However, the high-concentration P-type region 38 is formed by deeply implanting and diffusing P-type impurities from the front surface side of the semiconductor substrate 5, and the P-type high-concentration region 38 is formed.
There is a problem in that the manufacturing process must be increased by one in order to form the film, which leads to an increase in product cost.

The present invention has been made in view of the above conventional circumstances, and in a semiconductor integrated circuit device in which an N-channel DMOS transistor is mixed with a bipolar transistor,
N-channel D with stable source-drain breakdown voltage BVDS
It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device, which can manufacture a MOS transistor without increasing the number of manufacturing steps.

[0006]

The method of manufacturing a semiconductor integrated circuit device according to the present invention, which achieves the above objects, is an N channel DM.
In a method of manufacturing a semiconductor integrated circuit device in which an OS transistor and a bipolar transistor are formed on the same semiconductor substrate, a P-type impurity is diffused from the lower surface side of an epitaxial layer of the semiconductor substrate to form a high concentration DMOS transistor forming region of the semiconductor substrate. Forming a P-type buried region and simultaneously forming a high-concentration P-type element isolation region in the bipolar transistor forming region; and P reaching the P-type buried region on the surface of the semiconductor substrate in the DMOS transistor forming region. A step of forming a type body region, and an N-channel DMOS transistor having an N type source / drain region and a P type back gate region in the P type body region,
Sequentially forming in the transistor formation region and sequentially forming the bipolar transistor in the bipolar transistor formation region.

[0007]

A high-concentration P-type element isolation region which is inevitably provided in the bipolar transistor structurally is formed, and at the same time, a high-concentration P-type buried region for preventing the operation of the parasitic bipolar transistor of the N-type DMOS transistor is formed. It is possible to eliminate the step of forming the high-concentration P-type region for preventing the parasitic transistor operation.

[0008]

First, a semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIG. In this semiconductor integrated circuit device, an NPN bipolar transistor 1, an N-channel MOS transistor 2 and an N-channel DMOS transistor 3 are sequentially formed on the same P-type silicon semiconductor substrate 5 from the right side in the figure.

In the portion of the NPN bipolar transistor 1, an N ⁺ type buried layer 6 is formed on the semiconductor substrate 5 in order to reduce the on resistance, an N type epitaxial layer 7 is formed on the N ⁺ type buried layer 6, and a surface portion thereof is formed. A P-type base region 10 and an N ⁺ -type collector contact region 11 are formed, an N ⁺ -type emitter region 12 is formed on the surface portion of the P-type base region 10, and the surface is covered with an oxide insulating film 8. Then, the metal electrodes 13, 11 are respectively provided in the respective regions 10, 11, 12.
14, 15 are ohmic-connected.

In the portion of the N-channel MOS transistor 2, a high-concentration P ⁺ type buried region 20 is formed in the lower layer portion of the semiconductor substrate 5, and a P ⁺ type well region 21 is formed in the upper layer thereof.
Is formed, and a pair of Ns is formed on the surface of the well region 21.
^{A +} type source / drain region 22 is formed, the surface is covered with an oxide insulating film 8, and a gate electrode 23 made of polysilicon is provided through the gate insulating film 8. The metal electrode 2 is formed on each of the source / drain regions 22.
4 is ohmic connected.

In the portion of the N-channel lateral DMOS transistor 3, an N ⁺ type buried layer 6 is formed on the semiconductor substrate 5 to separate the element forming region, and an N type epitaxial layer 7 is formed on the N ⁺ type buried layer 6. A high-concentration P ⁺ -type buried region 30 is formed in the type epitaxial layer 7, and the lower surface of the N-type epitaxial layer 7 is covered with the P ⁺ -type buried region 3.
Low concentration P ⁻ -type body region 31 in contact with 0 and one N −
The type source / drain region 32 is formed, and the body region 3 is formed.
The other N-type source / drain region 33 and the P-type back gate region 34 that stabilizes the potential of the source / drain region 33 are formed on the surface portion of 1, and the surface is covered with the oxide insulating film 8. A gate electrode 35 made of polysilicon is provided therethrough. Then, both the source / drain regions 32 and 33 and the back gate region 34
The metal electrodes 36 are ohmic-connected to each of them.

A field oxide film (LOCOS) 50 is provided on the front surface of the semiconductor substrate 5 in order to separate the formation regions of the transistors 1, 2, and 3, and the inside of the semiconductor substrate 5 is from the back surface side of the substrate. A high-concentration P ⁺ -type isolation region 51 that extends and a high-concentration P ⁺ -type isolation region 52 that extends from the front surface side of the substrate are formed. In addition, each transistor 1,
The surfaces of 2 and 3 are protected by being covered with an oxide film 53.

In the semiconductor integrated circuit device having the above structure, since the high-concentration P-type buried region 30 is formed under the P-type body region 31, the N-type source / drain regions 33,
The source-drain breakdown voltage BVDS of the N-channel DMOS transistor is prevented by preventing the operation of the parasitic NPN transistor composed of the P-type body region 31 and the N-type epitaxial layer 7.
Can be stabilized.

Next, a method of manufacturing the above-mentioned semiconductor integrated circuit device will be described with reference to FIGS. First, FIG.
As shown in FIG. 5, a P ⁺ type impurity is implanted and diffused into the lower surface side of the epitaxial layer of the semiconductor substrate 5 using a photoresist mask to form high concentration P ⁺ type buried regions 20, 30, and 51. An N ⁺ type impurity is injected and diffused into the lower surface side of the epitaxial layer of the substrate using a resist mask to form an N ⁺ type buried layer 6, and an N type epitaxial layer 7 is further formed by a vapor phase growth method. Therefore, N-type DM
The high-concentration P ⁺ -type buried region 30 for preventing the operation of the parasitic transistor of the OS transistor 3 is the P ⁺ -type element isolation region 51 of the NPN bipolar transistor 1 which has been conventionally performed without any special process. Are simultaneously formed in the forming step.

Next, as shown in FIG. 3, a P ⁺ type well region 21 is formed by implanting and diffusing P type impurities from the surface of the epitaxial layer 7 using a photoresist mask. Then, as shown in FIG. 4, a high-concentration P-type impurity is implanted and diffused from the front surface side of the substrate using a photoresist mask to form a high-concentration P-type isolation region 52. Then, as shown in FIG. 5, the surface is selectively oxidized to form a field oxide film 50. Then, as shown in FIG. 6, thermal oxidation is performed to grow a thin oxide insulating film 8 on the entire surface, a polysilicon layer is deposited by the CVD method, and the DMOS transistor 1 is photoetched from this polysilicon layer. Gate electrodes 23 and 35 are formed.

Then, as shown in FIG. 7, a P-type impurity is injected from the front surface side of the substrate using a photoresist mask and diffused to form a P-type base region 10, and the gate electrode 35 and the field oxide film 50 are formed. The P-type body region 3 which reaches the high-concentration P ⁺ -type buried region 30 by injecting and diffusing P-type impurities by self-alignment utilizing
1 is formed. Then, as shown in FIG. 8, P-type impurities are implanted and diffused using a photoresist mask, and P
A back gate region 34 of the mold is formed. Then, as shown in FIG. 9, it is diffused by injecting N ⁺ type impurities by using a photoresist mask, N ⁺ -type collector contact region 11, emitter region 12, the source-drain region 22
And source / drain regions 32 and 33 are formed.

Then, as shown in FIG. 10, a contact hole is formed after depositing an oxide film 53 by a CVD method, and a metal layer (aluminum layer) is further deposited and then photoetching is performed to form electrodes 13, 14 ,. 15, 24 and 36 are formed to manufacture the integrated circuit device shown in FIG. In the above embodiment, the lateral type of N-channel DMOS transistors is taken as an example, and the NPN transistor of bipolar transistors is taken as an example. However, the present invention is applicable to vertical N-channel DMOS transistors. Further, it can be similarly applied to a PNP transistor.

[0018]

As described above, according to the present invention,
The high-concentration P-type region formed in the bipolar transistor is also formed in the N-channel DMOS transistor portion in the same manufacturing process, and this is used to prevent the operation of the parasitic transistor of the N-channel DMOS transistor. It is possible to manufacture a semiconductor integrated circuit device including an N-channel DMOS transistor having a stable breakdown voltage between the source and the drain without increasing the number of the semiconductor integrated circuit devices.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor integrated circuit device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a semiconductor integrated circuit device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor integrated circuit device according to the present invention.

FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor integrated circuit device according to the present invention.

FIG. 6 is a cross-sectional view illustrating the manufacturing process of the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a cross-sectional view illustrating the manufacturing process of the semiconductor integrated circuit device according to the present invention.

FIG. 8 is a cross-sectional view illustrating the manufacturing process of the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a cross-sectional view illustrating the manufacturing process of the semiconductor integrated circuit device according to the present invention.

FIG. 10 is a cross-sectional view illustrating the manufacturing process of the semiconductor integrated circuit device according to the present invention.

FIG. 11 is a cross-sectional view of a conventional semiconductor integrated circuit device.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device in which an N-channel DMOS transistor and a bipolar transistor are formed on the same semiconductor substrate, wherein a P-type impurity is diffused from a lower surface side of an epitaxial layer of the semiconductor substrate to form a DMOS of the semiconductor substrate. Forming a high-concentration P-type buried region in the transistor forming region and simultaneously forming a high-concentration P-type element isolation region in the bipolar transistor forming region; and forming the P-type element isolation region on the surface portion of the semiconductor substrate in the DMOS transistor forming region. Forming a P type body region reaching the type buried region, and sequentially forming an N channel DMOS transistor having an N type source / drain region and a P type back gate region in the P type body region in the DMOS transistor forming region, Bipolar transistor in the bipolar transistor formation area A method of manufacturing a semiconductor integrated circuit device, comprising: