JPH01272163A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01272163A JPH01272163A JP19738787A JP19738787A JPH01272163A JP H01272163 A JPH01272163 A JP H01272163A JP 19738787 A JP19738787 A JP 19738787A JP 19738787 A JP19738787 A JP 19738787A JP H01272163 A JPH01272163 A JP H01272163A
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- layer
- gate electrode
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 26
- 230000000694 effects Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電力用縦形ＭＯ３）ランジスタあるいは絶縁
ゲート型バイポーラトランジスタのように、第一導電形
の層の一面側に形成された第二導電形の領域中にさらに
第一導電形の領域を有し、第一導電形の層と第一導電形
の領域の間の第二導電形の領域の表面に絶縁膜を介して
ゲート電極が設けられる半導体装置の製造方法に関する
。Detailed Description of the Invention [Industrial Field of Application] The present invention is directed to a second conductive layer formed on one side of a layer of a first conductive type, such as a power vertical MO3) transistor or an insulated gate bipolar transistor. The shaped region further has a first conductivity type region, and a gate electrode is provided on the surface of the second conductivity type region between the first conductivity type layer and the first conductivity type region via an insulating film. The present invention relates to a method of manufacturing a semiconductor device.
第２図は絶縁ゲート型バイポーラトランジスタ（以下Ｉ
ＧＢＴ）の断面構造を示し、ｎ形シリコン基板の一方に
ｎ０バッファ層２を介して９０層３が設けられ、残りの
ｎ−層１の中にｐ領域４が、さらにその中央にそれより
深いｐ″領域４１が設けられてＰＮＰバイポーラトラン
ジスタを構成する。Figure 2 shows an insulated gate bipolar transistor (I
GBT), in which a 90 layer 3 is provided on one side of an n-type silicon substrate via an n0 buffer layer 2, a p region 4 is provided in the remaining n- layer 1, and a deeper layer is provided in the center of the 90 layer 3. A p'' region 41 is provided to constitute a PNP bipolar transistor.
またｐ ｓＩ域４の表面層に形成されたｎ”＊域５と、
ｐＨ域４を取囲むｎ°層１と、その間に存在するｐ ８
１域４の表面上に酸化膜６を介して設けられる多結晶シ
リコンのゲート電極７とによってＭＯＳＦＥＴが構成さ
れる。ｐ″領域４１およびｎ０領域５にはソース・エミ
ッタ電極８が接触する。このようなＩ ＧＢＴのゲート
電極７にゲート端子Ｇから電圧を印加することにより電
子電流Ｊｅが流れる。In addition, an n''* region 5 formed in the surface layer of the psI region 4,
n° layer 1 surrounding pH range 4 and p 8 existing between
A MOSFET is constituted by a polycrystalline silicon gate electrode 7 provided on the surface of region 1 with an oxide film 6 interposed therebetween. A source/emitter electrode 8 is in contact with the p'' region 41 and the n0 region 5. By applying a voltage from the gate terminal G to the gate electrode 7 of such IGBT, an electron current Je flows.
しかし、ｎ′″領域５．ｐＨ域４，４１およびｎ−層１
により寄生ＮＰＮバイポーラトランジスタが生ずる。こ
の寄生トランジスタが、ｎ″領域５の直下の拡散抵抗Ｒ
ｂによる電圧降下によりベースが駆動されてオンすると
、正札電流Ｊｈが流れ、いわゆるラッチアンプ現象が起
こる。このラッチアップ現象は、ｐ′″層３の代わりに
ｎ９層を設けた電力用縦形ＭＯＳトランジスタでも同様
に起こる。このようなラッチアップ現象を回避するこめ
には、拡散抵抗１１を低減することが有効である。However, n''' region 5. pH range 4,41 and n-layer 1
This results in a parasitic NPN bipolar transistor. This parasitic transistor is a diffused resistor R directly under the n'' region 5.
When the base is driven and turned on by the voltage drop caused by b, the current Jh flows and a so-called latch amplifier phenomenon occurs. This latch-up phenomenon similarly occurs in a power vertical MOS transistor in which an n9 layer is provided instead of the p'' layer 3. To avoid such a latch-up phenomenon, it is necessary to reduce the diffusion resistance 11. It is valid.
拡散抵抗Ｒｈを低減するためにはいろいろな対策が立て
られている。その例を第２図のＡ部を拡大して示した第
３図を引用して説明する。Various measures have been taken to reduce the diffusion resistance Rh. An example of this will be explained with reference to FIG. 3, which shows part A in FIG. 2 enlarged.
（１） チャネル拡散領域４の深さを深くするか拡散
濃度を高める。(1) Increase the depth of the channel diffusion region 4 or increase the diffusion concentration.
（２） 距離ｌを小さくする。(2) Reduce the distance l.
＋３＋ｐＨ域４１を深くし、ゲート電極に近付ける。The +3+ pH region 41 is made deeper and closer to the gate electrode.
（４）ｐ″領域４１の表面層に図のようにｐ−領域４２
を形成する。(4) A p- region 42 is formed on the surface layer of the p'' region 41 as shown in the figure.
form.
（５）ｎ″領域５を浅くする。(5) Make the n″ region 5 shallower.
しかし、これらの各対策はプロセス精度などの技術的制
限の拡大あるいは工程数の増大を必要とするほか、それ
ぞれ次のような問題を有する。However, each of these measures requires expansion of technical limitations such as process accuracy or an increase in the number of steps, and each of them has the following problems.
（１１に対しては、オン抵抗の増大、ＭＯＳ Ｆ ＥＴ
のしきい値電圧の増大がもたらされる。(For 11, increase in on-resistance, MOS FET
This results in an increase in the threshold voltage of .
（２）に対しては、プロセス精度上２〜３ｎが限度であ
る。For (2), the limit is 2 to 3n in terms of process accuracy.
（３）に対しては、オン抵抗の増大がもたらされる。For (3), an increase in on-resistance results.
（４）に対しては、フォトプロセス回数が増加するほか
、拡散精度の上から抵抗Ｒｂの低減に限度がある。Regarding (4), in addition to the increase in the number of photoprocesses, there is a limit to the reduction of the resistance Rb due to diffusion accuracy.
（５）に対しては、０．２ ＃ＩＩレベルにしてもこれ
だけでは十分な効果が得られない。Regarding (5), even if the level is set to 0.2 #II, a sufficient effect cannot be obtained by this alone.
本発明の目的は、以上の問題点に鑑みて、他の特性に影
響を与えず、工程を増加させることなしに拡散抵抗Ｒｂ
を低減し、ラッチアンプ耐量の増大した半導体装置の製
造方法を提供することにある。In view of the above problems, an object of the present invention is to provide a diffusion resistance Rb without affecting other characteristics and without increasing the number of steps.
An object of the present invention is to provide a method for manufacturing a semiconductor device in which latch amplifier durability is increased.
ｃ問題点を解決するための手段〕
上記の目的を達成するために、本発明の方法は、第一導
電形の層上にｗ７Ａ縁膜を介して多結晶シリコン層を形
成後、その表面にレジスト膜のパターンを形成し、エツ
チングによって多結晶シリコンよりなるゲート電極を形
成する際に、レジスト膜の下の横方向エツチングを助長
し、そのあと先ず前記レジスト膜をマスクにして高濃度
の第二導電形のためのイオン注入を深く行い、次いでゲ
ート電極をマスクとして低濃度の第二導電形のためのイ
オン注入を浅く行い、高濃度に注入された不純物がゲー
ト電極の端部直下近傍に達するまでの拡散を行つたおち
、その拡散領域内に第一導電形の領域を形成すものとす
る。Means for Solving Problems] In order to achieve the above object, the method of the present invention includes forming a polycrystalline silicon layer on the first conductivity type layer via a W7A edge film, and then forming a polycrystalline silicon layer on the surface of the layer. When a resist film pattern is formed and a gate electrode made of polycrystalline silicon is formed by etching, lateral etching under the resist film is promoted, and then a highly concentrated second film is first etched using the resist film as a mask. Deep ion implantation for the conductivity type is performed, then shallow ion implantation is performed for the second conductivity type using the gate electrode as a mask, and the highly concentrated impurity implants reach the vicinity directly below the edge of the gate electrode. After performing the diffusion up to this point, a region of the first conductivity type is formed within the diffusion region.
ゲート電極形成のために用いたレジスト膜をゲート電極
の上に張り出させておき、そのレジスト膜をマスクにし
て注入した不純物の横方向拡散により、ゲート電極直下
近傍まで達する高不純物濃度の第二導電影領域ができ、
その中に形成される第−導電影領域の直下の拡散抵抗が
大幅に小さくなる。そしてこの高不純物濃度の第二導電
影領域も、ゲート電極をマスクとするチャネル領域とし
ての低不純物濃度の第二導電影領域もセルフアライメン
トにより精度よく形成され、工程を増や。すことがない
。The resist film used for forming the gate electrode is extended over the gate electrode, and by using the resist film as a mask and lateral diffusion of the implanted impurity, a second layer with a high impurity concentration reaches the vicinity directly below the gate electrode. A conductive shadow area is formed,
The diffusion resistance directly beneath the first conductive shadow region formed therein is significantly reduced. The second conductive shadow region with a high impurity concentration and the second conductive shadow region with a low impurity concentration as a channel region using the gate electrode as a mask are formed with high precision by self-alignment, and the number of steps is increased. I have nothing to do.
以下、第２図、第３図と共通な部分に同一符号を付した
第１図（ａｌ〜（ｄｌを引用して本発明の一実施例につ
いて説明する。Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1A to 1D, in which parts common to FIGS.
ｎ−層１の下面にｎ０層２を介してｐ゛層３、上面側の
一部にｐ”ｔＪｌ域４１を形成した半導体基板上に酸化
膜６を介して多結晶シリコン膜を被着し、レジスト膜９
のマスクを用いてエツチングしてゲート電極７を形成し
た状態を第１図ｔａ＋に示す、そのエツチングの際、５
１０重、 レジスト、多結晶Ｓｌの選択比を改善し、
さらに多結晶３１の横方向エッチングを助長することに
より、レジスト膜９がゲート電極７より張り出した幅り
を約５４で±１０％以内の精度にすることを可能にした
。このレジスト膜をマスクにしてｐ′。層４２のための
高濃度で深いＢ４のイオン注入を行う６次いでレジスト
膜９を除去し、２層４のための低濃度で浅いＢｏのイオ
ン注入を第１図（ｂｌに示すように行う、このあと、拡
散を行って第１図（Ｃ１に示すように深い９１１４層４
２がゲート電極７の端の下にまで達するようにする。A polycrystalline silicon film is deposited via an oxide film 6 on a semiconductor substrate in which a p' layer 3 is formed on the lower surface of the n- layer 1 via an n0 layer 2, and a p"tJl region 41 is formed on a part of the upper surface side. , resist film 9
The gate electrode 7 is formed by etching using the mask shown in FIG.
Improved selectivity of 10 layers, resist, and polycrystalline Sl,
Furthermore, by promoting the lateral etching of the polycrystal 31, it is possible to make the width of the resist film 9 extending beyond the gate electrode 7 approximately 54, with an accuracy within ±10%. p' using this resist film as a mask. High concentration and deep B4 ion implantation for the layer 42 is performed 6. Next, the resist film 9 is removed and a low concentration and shallow Bo ion implantation for the second layer 4 is performed as shown in FIG. 1 (bl). After this, diffusion is performed to form a deep 9114 layer 4 as shown in Figure 1 (C1).
2 reaches below the edge of the gate electrode 7.
同時に浅い２層４がゲート電極７の下に約２−入り込ん
で形成される。このあとｎ９ソース領域５を第１図（ｄ
）に示すように形成すれば、ソース領域５の下には高濃
度のｐ”ｆｆ域４２が存在するため、その拡散抵抗Ｒｈ
は小さくなる。第４図は従来の三つのラッチアップ耐量
増大方法と本発明の実施例の場合のＲｈを示し、その結
果ランチアップの発生する電流は第５図に示すように大
きくなり、ランチアンプ耐量が改善される０以上の工程
は、そのまま電力用縦形ＭＯ３）ランジスタの製造にも
適用できる。At the same time, two shallow layers 4 are formed extending approximately 2-into the bottom of the gate electrode 7. After this, the n9 source region 5 is
), a highly doped p''ff region 42 exists under the source region 5, and its diffusion resistance Rh
becomes smaller. Figure 4 shows Rh in the case of the three conventional latch-up resistance increasing methods and the embodiment of the present invention. As a result, the current that occurs during launch-up increases as shown in Figure 5, and the launch amplifier resistance improves. The 0 or more steps described above can be directly applied to the manufacture of vertical power MO3) transistors.
本発明によれば、ゲート電極のパターニングに用いたレ
ジストマスクを用いて、第一導電形のソース領域の下ま
で延びる深い第二導電形の高不純物濃度の領域を、ゲー
ト電極をマスクにして浅い低不純物濃度の第二導電形の
チャネル領域を形成することにより、ゲート電極の端部
直下近傍にまで達する低抵抗の領域がセルアライメント
により精度よ（ソース領域の下に形成されるので、その
部分の拡散抵抗が低減し、フォトプロセスの工程の付加
の必要もなく、何等特性のトレードオフもなしにラッチ
アンプ耐量の高い半導体装置が得られる。According to the present invention, using the resist mask used for patterning the gate electrode, a deep high impurity concentration region of the second conductivity type extending below the source region of the first conductivity type is formed into a shallow region using the gate electrode as a mask. By forming a channel region of the second conductivity type with a low impurity concentration, a low resistance region that reaches just below the edge of the gate electrode can be formed with precision through cell alignment (because it is formed under the source region, The diffusion resistance of the semiconductor device is reduced, and a semiconductor device with high latch amplifier durability can be obtained without the need for additional photoprocessing steps and without any trade-off in characteristics.
第１図Ｃａ）〜（ｄｌは本発明の一実施例の工程を順次
示す要部断面図、第２図は従来のＩ ＧＢＴの要部断面
図、第３図は第２図のＡ部拡大図、第４図は本発明のＲ
ｂ減少に及ぼす効果を示す線図、第５図は本発明のラン
チアンプ電流増大に及ぼす効果を示す線図である。
４：チャネル領域、５：ソース領域、６：酸化膜、７：
ゲート電極、９ニレジスト膜。
↑゛
第１図
◆ 〜２
Ｐ９
第２図
第４図Figures 1 (Ca) to (dl) are sectional views of essential parts sequentially showing the steps of an embodiment of the present invention, Figure 2 is a sectional view of essential parts of a conventional IGBT, and Figure 3 is an enlarged view of part A in Figure 2. Figure 4 shows R of the present invention.
FIG. 5 is a diagram showing the effect of the present invention on increasing the launch amplifier current. 4: Channel region, 5: Source region, 6: Oxide film, 7:
Gate electrode, 9-layer resist film. ↑゛Figure 1◆ ~2 P9 Figure 2 Figure 4
Claims (1)
の領域中にさらに第一導電形の領域を有し、前記第一導
電形の層と該第一導電形の領域の間の前記第二導電形の
領域の表面に絶縁膜を介してゲート電極が設けられる半
導体装置の製造方法において、第一導電形の層上に絶縁
膜を介して多結晶シリコン層を形成後、該多結晶シリコ
ン層上にレジスト膜のパターンを形成し、エッチングに
より多結晶シリコンよりなるゲート電極を形成する際に
レジスト膜の下の横方向エッチングを助長し、そのあと
先ず前記レジスト膜をマスクにして高濃度の第二導電形
のためのイオン注入を深く行い、次いで前記ゲート電極
をマスクにして低濃度の第二導電形のためのイオン注入
を浅く行い、高濃度に注入された不純物がゲート電極の
端部直下近傍に達するまでの拡散を行ったのち、該拡散
領域内に第一導電形の領域を形成することを特徴とする
半導体装置の製造方法。(1) A region of the second conductivity type formed on one side of the layer of the first conductivity type further includes a region of the first conductivity type, and the layer of the first conductivity type and the region of the first conductivity type In the method for manufacturing a semiconductor device in which a gate electrode is provided on the surface of the second conductivity type region between the layers with an insulating film interposed therebetween, after forming a polycrystalline silicon layer on the first conductivity type layer with the insulating film interposed therebetween. , a resist film pattern is formed on the polycrystalline silicon layer, and when a gate electrode made of polycrystalline silicon is formed by etching, lateral etching is promoted under the resist film, and then the resist film is first masked. Then, using the gate electrode as a mask, shallowly implanting ions for the second conductivity type at a low concentration, so that the impurities implanted at a high concentration are 1. A method of manufacturing a semiconductor device, comprising performing diffusion until reaching the vicinity immediately below an end of a gate electrode, and then forming a region of a first conductivity type within the diffusion region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19738787A JPH01272163A (en) | 1987-08-07 | 1987-08-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19738787A JPH01272163A (en) | 1987-08-07 | 1987-08-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01272163A true JPH01272163A (en) | 1989-10-31 |
Family
ID=16373663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19738787A Pending JPH01272163A (en) | 1987-08-07 | 1987-08-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01272163A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0772242A1 (en) * | 1995-10-30 | 1997-05-07 | STMicroelectronics S.r.l. | Single feature size MOS technology power device |
| US5798554A (en) * | 1995-02-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
| US5841167A (en) * | 1995-12-28 | 1998-11-24 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
| EP0890994A2 (en) * | 1990-12-21 | 1999-01-13 | SILICONIX Incorporated | Power MOSFET and fabrication method |
| US5900662A (en) * | 1995-11-06 | 1999-05-04 | Sgs Thomson Microelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| US6030870A (en) * | 1995-10-30 | 2000-02-29 | Sgs-Thomson Microelectronics, S.R.L. | High density MOS technology power device |
| US6090669A (en) * | 1995-10-09 | 2000-07-18 | Consorzio Per La Ricerca Sulla Microelectronics Nel Mezzogiorno | Fabrication method for high voltage devices with at least one deep edge ring |
| US6228719B1 (en) | 1995-11-06 | 2001-05-08 | Stmicroelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| CN102034707A (en) * | 2009-09-29 | 2011-04-27 | 比亚迪股份有限公司 | Method for manufacturing IGBT |
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| JPS61156810A (en) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | Manufacture of semiconductor device |
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| JPS61156810A (en) * | 1984-12-28 | 1986-07-16 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0890994A3 (en) * | 1990-12-21 | 2000-02-02 | SILICONIX Incorporated | Power MOSFET and fabrication method |
| EP0890994A2 (en) * | 1990-12-21 | 1999-01-13 | SILICONIX Incorporated | Power MOSFET and fabrication method |
| US5798554A (en) * | 1995-02-24 | 1998-08-25 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
| US6111297A (en) * | 1995-02-24 | 2000-08-29 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS-technology power device integrated structure and manufacturing process thereof |
| US6090669A (en) * | 1995-10-09 | 2000-07-18 | Consorzio Per La Ricerca Sulla Microelectronics Nel Mezzogiorno | Fabrication method for high voltage devices with at least one deep edge ring |
| US5981998A (en) * | 1995-10-30 | 1999-11-09 | Sgs-Thomson Microelectronics S.R.L. | Single feature size MOS technology power device |
| US5981343A (en) * | 1995-10-30 | 1999-11-09 | Sgs-Thomas Microelectronics, S.R.L. | Single feature size mos technology power device |
| US5985721A (en) * | 1995-10-30 | 1999-11-16 | Sgs-Thomson Microelectronics, S.R.L. | Single feature size MOS technology power device |
| US6030870A (en) * | 1995-10-30 | 2000-02-29 | Sgs-Thomson Microelectronics, S.R.L. | High density MOS technology power device |
| US6064087A (en) * | 1995-10-30 | 2000-05-16 | Sgs-Thomson Microelectronics, S.R.L. | Single feature size MOS technology power device |
| EP0772242A1 (en) * | 1995-10-30 | 1997-05-07 | STMicroelectronics S.r.l. | Single feature size MOS technology power device |
| US5900662A (en) * | 1995-11-06 | 1999-05-04 | Sgs Thomson Microelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| US6228719B1 (en) | 1995-11-06 | 2001-05-08 | Stmicroelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| US6051862A (en) * | 1995-12-28 | 2000-04-18 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
| US5841167A (en) * | 1995-12-28 | 1998-11-24 | Sgs-Thomson Microelectronics S.R.L. | MOS-technology power device integrated structure |
| CN102034707A (en) * | 2009-09-29 | 2011-04-27 | 比亚迪股份有限公司 | Method for manufacturing IGBT |
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