JPS59147453A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce contact resistance without enlarging a contact hole by boring an indentation in an extent that penetrates a shallow region in P type and N type two regions of different diffusion depth to the shallow region and attaching an electrode to the indentation when the metallic electrode is placed simultaneously in the two regions through one contact hole. CONSTITUTION:An N type layer 2 is grown on an N<-> type Si substrate 1 in an epitaxial manner, and P type ions are implanted while using a photo-resist as a mask, and driven in to form a P type region 3 first. N Type ions are implanted, and driven in similarly to form two N type regions 4, an oxide film 8 with an opening 12 is generated between the two regions 4 on the two regions, and an end section is thinned and used as a gate oxide film 7. The exposed surfaces of the films 8 and 7 are coated with a photo-resist film 13, and a groove 14 slightly deeper than the depth of the opening is bored between the two regions 4 through etching. An electrode 5 is attached in the groove 14 while a gate electrode 6 is formed extending over the end section of the film 8 from the film 7.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a semiconductor device having a novel metal-to-impurity contact structure that reduces the contact resistance between a metal and an impurity region.

Conventional configurations and their problems In recent years, as semiconductor devices have become smaller, the area of contact between the metal electrodes used in these devices and the impurity regions formed on the substrate surface has become narrower. This poses a problem of increased contact resistance.

Vertical double diffused MO8FET (hereinafter referred to as VDIVIO
The problems of the conventional method will be explained by taking the example of 8) as an example. 1st
The figure is a diagram showing a schematic cross-sectional structure of a conventional VDMO3 and its equivalent circuit. In FIG. 1a, 1 is a heavily doped N-type substrate that serves as a drain, 2 is an N-type epitaxial layer, 3 is a P-type diffused region, 4 is a heavily doped N-type diffused region that is a source,
5 is a source metal electrode, 6 is a gate electrode, 7 is a gate oxide film, and 8 is an oxide film.

, is. This structure can be expressed as an equivalent circuit as shown in FIG. 'VDMO8 is a parasitic NPN (MOS) transistor 10 formed by the resistance component 9 of the epitaxial layer 2 connected in series with the transistor 8, the N-type regions 2, 4 and the P-layer region 3 parallel to them, and the source electrode 5 and the P-layer region 3. The contact resistance Rcs 11 between the layer region 3 and the layer region 3 is represented by Rcs11.

In order to improve the frequency characteristics, it is necessary to reduce the chip area, and therefore patterns are being made smaller.

On the other hand, if the width wc of the contact hole (shown in FIG. 1a) is narrowed, the drain-source breakdown voltage BvDs of VDMO8 will decrease when the contact resistance Rcs11 and LARC8 exceed a certain value. This means that as Rcs increases in FIG. 1, the potential of the P layer region 3 increases, and the collector-emitter breakdown voltage BvcE of the NPN transistor 10 decreases accordingly.
When VcE becomes lower than the drain-source breakdown voltage BvDs of the transistor 8 (MOS), the B V of this VDMO8
Let's explain that DS is determined by BvcE.

The reason why the contact resistance RCS11 increases as the width Wc of the contact hole is narrowed is that the width Wc' where the P region 3 is in contact with the electrode 5 becomes narrower along with Wc, and the P layer region surrounded by the source region 4 immediately below it becomes smaller. This is because the resistance of No. 3 increases in inverse proportion to Wc'. For this reason, conventionally B V
Due to the need to prevent a decrease in Ds, Wc could not be reduced to 8 microns or less.

Purpose of the Invention The present invention has been developed in view of the problem that when making contact with an electrode from one contact hole to two regions of P type and N type, contact resistance increases as the pattern becomes finer. The present invention provides a semiconductor device having a contact groove structure between an electrode and an impurity region, which can reduce contact resistance without changing the size of a contact hole.

Structure of the Invention The present invention provides a method for making contact with an electrode at the same time through one contact hole to both a P-type subregion and an N-type region having different diffusion depths. This semiconductor device is characterized in that a recess that is approximately or even deeper is formed at the boundary between the P-type region and the N-type region, and that the recess is brought into contact with the electrode there.

DESCRIPTION OF EMBODIMENTS Specific embodiments of the present invention will be described with reference to the drawings. Second
The figure is a sectional view when the present invention is applied to a VDMO3. For ease of explanation, components common to the conventional example are given the same numbers. 1 is a high concentration N-type silicon substrate, 2 is N
211 epitaxial layer.

3 is a P-type diffusion region, and 4 is a source N-type diffusion region.

Reference numerals 6 and 6 are source and gate electrodes, 7 is a gate oxide film, and 8 is an oxide film. As shown in the figure, the interface of the source contact region surrounded by a circle is recessed to a depth greater than source region 4, and contains impurities.

It can be seen that the contact area between the regions 3 and 4 and the metal electrode 5 is approximately double that of the conventional example. Especially this VDMO8
The contact resistance between the electrode 6 and the P-layer region 3, which was the cause of the decrease in the durability B V ps, was significantly reduced by the electrode 6 entering the inside of the P-layer region 3. Conventionally, the contact resistance to the N-type region 4 was relatively low, but the contact resistance to the P-layer region 3 varied greatly. As can be seen from FIG. 1a of the conventional example, this depends on the lateral diffusion situation of the N-type region 4 and the contact area between the P-layer region 3 and the electrode 5 and the P layer surrounded by the N-type region 4. This is considered to be because the width of the layer region 3 changes greatly. On the other hand, when the present invention is applied, as shown in FIG. 2, the electrode penetrates into the silicon in a trench about the bottom of the N-type region 4 or deeper than that, so the potential of the P-layer region 3 is reliably maintained. The source potential is maintained, and the situation where the breakdown voltage of VDMO3 is limited by the breakdown voltage of the NPN structure consisting of the 2.3.4 region as in the conventional case does not occur. Also, since the contact area of the N-pole 6 with the N-type region 4 is almost the same as before,
No increase in contact resistance was observed in response to this.

Figure 3 explains the manufacturing process of this example.
For example, 0.01°Q cm of n-type as shown in figure a.
A 2.6Ωcm N-type epitaxial layer 2 is applied to the substrate.
Grow to about 20 It m. Next, using the No. 7 photoresist as a mask, boron ions are implanted and driven in to form the P-type region 3. "J tc Arsenic is ion-implanted and driven in to form region 4. Oxide film 8 is formed by chemical vapor deposition, and gate wiring n' is formed by thermal oxidation.
Form A7. Up to this point, it is a well-known technology and conventional VD
Since it is the same as the manufacturing method of MO3, the details will not be described. Next, as shown in the figure, the entire surface of the wafer except for the central part 12 of the contact hole is covered with photoresist 13, and CC processing is performed. Reactive ion etching is performed in the gas atmosphere of the Kasa.

A groove 14 is formed which is approximately the same depth as the diffusion depth of the N-type region 4 or slightly deeper than the diffusion depth. When reactive ion etching is used, silicon is etched relatively vertically as shown in Figure C.
1. There is also little change in pattern width.

Next, as shown in Figure d, electrodes 6, 6 are attached to complete the VDMO3 device.

As described above, the semiconductor device of the present invention reduces the contact resistance by providing a depression at the interface between the electrode and the silicon, and the contact resistance can be reduced without enlarging the contact hole. This will greatly contribute to improving the performance of miniaturized elements and integrated circuits.

[Brief explanation of drawings]

3a to 3d are cross-sectional views of the structure of a heavy diffusion type MO3FET to which the present invention is applied (and are cross-sectional views of the manufacturing process of a vertical double diffusion type MO3FET. 1... N type silicon substrate, 2 ...N-type epitaxial layer, 3...P-type impurity region, 4...
...N-type impurity region, 5...metal electrode, 6...
...gate electrode, T...gate oxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 2 Figure 1 Display of the case 1986 Patent Application No. 20638 2 Name of the invention Semiconductor device 3 Person making the amendment Relationship to the case Patent application Address 1006 Kadoma, Kadoma City, Osaka Name Name (582) Representative of Matsushita Electric Industrial Co., Ltd.
Toshihiko Yamashita 4 Agent 571 Address 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Scope of Claims] to Two adjacent impurity regions of a first conductivity type and a second conductivity type formed on a surface of a semiconductor substrate and having different depths from the surface to the bottom, and a boundary between the adjacent impurity regions. a depression region formed including at least a portion of the surface of the
an electrode that includes the recessed region and is in contact with the impurity regions of the first conductivity type and the second conductivity type, and the depth of the recess is approximately the impurity region of the first conductivity type and the second conductivity type. A semiconductor device characterized in that the depth is equal to or greater than the shallower of the depths. (c) The semiconductor device according to claim 1, wherein the impurity regions and electrodes of the first conductivity type and the second conductivity type are a source region, a channel region, and a source electrode, respectively.