JPS63305564A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To decrease the manufacturing cost, by forming a groove, by masking with a gate protecting film, at the center of a first conductivity type region formed by masking with a polycrystalline gate, for the purpose of providing first conductivity type regions on the opposite side of a second conductivity type region having low resistance. CONSTITUTION:As<+> ions 22 are implanted with a mask of a polycrystalline silicon gate 8 formed on a substrate through an oxide film 7. A PSG film 9 is provided and annealed, whereby the As<+> implanted region form an N<+> type layer 60. Resist 21 on the PSG film 9 is patterned by photoetching, and the PSG film 9 is etched by masking with this resist pattern so that the central part of the N<+> type layer 60 is exposed. The layer 60 is divided into N<+> type layers 6 by etching the same with a mask of the PSG film 9 and the resist 21. The PSG film 9 is over etched to expose a part of the surface of the N<+> type layers 6 and the resist 22 is ashed. Thus, a metallic electrode 10 formed thereon is brought into contact with the surface of the P<+> layer 5, a part of the surface of the n<+> layers 6 and the side faces thereof. In this manner, the photoetching process for forming two regions can be omitted and, hence, the manufacturing cost can be decreased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an insulated gate bipolar conduction transistor.
(hereinafter referred to as I CBT) or power MO3 field effect transistor (hereinafter referred to as MO5FET), the low resistance region in the center of the second conductivity type region formed in the semiconductor layer of the first conductivity type is A gate is provided via an insulating film on a high-resistance second conductivity type region between the first conductivity type layer 0 and the outer first conductivity type layer, and a low-resistance second The present invention relates to a method of manufacturing a semiconductor device in which one common electrode contacts a two-conductivity type region and a first conductivity-type region sandwiching the second conductivity type region.

[Conventional technology]

IGBT is a bipolar transistor integrated with a MOS FET to drive it.
In this element, which has the structure shown in Fig. 2,
A P'' layer 3 is provided on one side of the N type silicon substrate via an N'' buffer layer 2, and a P-11 layer is provided in the remaining N layer 1.
4 is further provided with a deeper P"Jli5 in the center, forming a PNP bipolar transistor. Also, two N3 layers formed on the surface layer of the P layer 4
A MOSFET is constituted by the layer 6, the N layer 1 surrounding the P-N4, and the polycrystalline silicon gate 8 provided on the surface of the P-M4 existing therebetween with an oxide film 7 interposed therebetween. The gate 8 has a gate terminal 11 drawn out from another location (not shown) from which the insulating film 9 covering the gate 8 has been removed.
An emitter terminal 12 is connected to the 0 layer 3 via a contact metal electrode 10.
However, there is a contact metal electrode 10 on the P′″lW5 and N+ layer 6.
Collector terminal 13 is connected via. By applying a voltage to the gate electrode 11 of this element, a channel is formed in the surface layer of the P layer 4, and the base current of the aforementioned PNP bipolar transistor flows, turning this transistor on. This structure, especially when turned off, has 20 layers 3, N 1 layer 1. P one layer 4. Since the thyristor structure of the N9 layer 6 tends to latch and become difficult to control, in order to prevent this, t8ito is set to P''J!5 and N''l1 as described above.
Short-circuit with 6.

Furthermore, if an N''0 layer is provided in place of P''ji3 of this IGBT, a power MOSFET with terminal 13 as the source terminal and terminal 12 as the drain terminal will be obtained. In this case as well, N is 1. In order to prevent the NPN bipolar transistor consisting of the P layer 4 and the P'' layer 5 and N'' layer 6 from operating, the metal electrode 10 connected to the source terminal 13 is connected to the P'' layer 5.
and N' layer 6 are brought into common contact and short-circuited.

[Problem that the invention seeks to solve]

To create the upper structure of such an IGBT or power MO3FET, first, impurities are introduced into the top surface of the silicon substrate at a high concentration to form the P'' layer 5, and then impurities are doped at a low concentration into the upper surface of the silicon substrate. Introducing drive diffusion, deepening the diffusion depth of the P layer 5 and widening the width of the P layer 4.
form.

Next, the steps shown in FIGS. 3(al) to (al) are performed. In FIG. 3(al), a polycrystalline silicon layer is grown on the oxide film 7 on the surface and then buttered to form the gate 8. In FIG. 3, a pattern of resist 21 is formed in the central opening by photoetching, and then arsenic ions (As'') 22 are implanted.

In FIG. 3(C), the resist 21 is ashed, a phosphorus glass (PSG) film 9 is coated and annealed, and a N layer 6 is formed in the A3° implantation region. In dl, the pattern of the resist 21 is again formed by photoetching, and using this as a mask, PSGSe is
Perform O2 tucking, then ash the resist 21,
When the metal electrode 10 is deposited as shown in FIG. 3(8), an electrode connected to the collector terminal 13 of the device shown in FIG. 2 is completed.

However, when manufacturing devices using such a process, photoetching must be repeated, leading to increased costs.

In contrast, an object of the present invention is to provide a method for manufacturing a semiconductor device in which patterning by photoetching is reduced.

[Means for solving problems]

In order to achieve the above object, the method of the present invention provides a method for forming two conductive shadow regions in a second conductive shadow region formed in a semiconductor layer of a first conductivity type. A gate made of polycrystalline silicon is provided via an insulating film over the high-resistance second conductive shadow region between the region and the first conductivity type layer outside the region, and then impurities are introduced using the gate as a mask. One first conductive shadow region is formed, then an insulating protective film is coated, an opening is provided in the center of the first conductive shadow region, and the first conductive shadow region is etched using the insulating protective film as a mask. The shadow region is divided to expose a low resistance region of the second conductivity type in the center, and the insulating protective film is further etched to expose a part of the first conductivity shadow region, and a common electrode is formed in contact with both exposed regions. shall be formed.

[Effect]

The first conductive shadow region divided into two is formed by dividing one region formed by introducing impurities using the gate as a mask by etching using the insulating protective film on the gate as a mask. The photo-etching process for forming two regions is omitted.

〔Example〕

1 fal to (el indicate steps corresponding to the steps in FIG. 3 of an embodiment of the present invention, and parts common to FIGS. 2 and 3 are given the same reference numerals. In FIG. 1 fat, As' 22 is implanted using the polycrystalline silicon gate 8 formed through the oxide film 7 as a mask, and when the PSG film 9 is coated and annealed (in FIG. 1), the As' implanted region is completely N"Jli60 becomes 0 then Figure 1fd
), a pattern of resist 21 is formed on PSG film 9 by photoetching as in FIG.
Expose the center part of 0.

Then, by etching the PSG film 9 and resist 21 as masks, grooves 2 are etched as shown in FIG. 1(d).
3 into N0 layers 6. After this, Figure 1 (e
1, the PSG film 9 is further over-etched to expose a part of the surface of the n' layer 6, the resist 22 is ashed, and the metal electrode 10 is formed.
The surface of the layer 5 and a part of the surface and side surfaces of the N layer 6 are contacted. In such a process, patterning by photo-etching of the resist 21 for dividing the N° layer into six parts as shown in FIG.

FIG. 4 is a perspective plan view of each pattern in FIG. 1 viewed from above. The central portion of the N layer 60 formed by implanting As'' into the inner region of the polycrystalline Si pattern shown by line 41 is removed by etching using the PSG film 9 as a mask to form a groove 23 having a pattern shown by line 42. As a result, the area indicated by dotted diagonal lines is N''16. Further, the PSG film 9 is over-etched to have a pattern of lines 43 and the N° layer 6 is exposed. However, at the end of the N'' layer 6, the P° layer 3, the N layer 1.P° layer 5.
Since the NPN structure tends to cause thyristor operation, so-called launch-up, the oxide film produced during drive diffusion is left in the region 44 indicated by solid diagonal lines.
It is effective to prevent latch amplifiers by not injecting As'' into this region and leaving it as P-@4.

〔Effect of the invention〕

According to the present invention, IGBT or MO3FE for power
A region of the second conductivity type sandwiching the low resistance region of the second conductivity type of T is formed by providing a groove formed using a gate protective film as a mask in the center of a first conductive shadow region formed using a polycrystalline gate as a mask. By creating this, the number of photoetching steps for dividing the first conductive shadow region can be reduced by one, which is extremely effective for cost reduction.

[Brief explanation of the drawing]

Figures 1 fal to +Ill are cross-sectional views sequentially showing the main parts of the steps of an embodiment of the present invention, Figure 2 is a structural cross-sectional view of a conventional IGBT, and Figure 3 is a cross-sectional view of the steps of a conventional IGBT manufacturing method. 4 is a perspective plan view showing each pattern in the process of FIG. 1. FIG. 4: P single layer, 5: P” 71.6.60: N single layer, 7: Oxide film, 8: Polycrystalline S1 pattern, 9: PS
G film, 1!3 Figure 2 Figure 3

Claims (1)

[Claims] 1) A first conductivity type region sandwiches a low resistance region in the center of a second conductivity type region formed in a first conductivity type semiconductor layer, and the first conductivity type region and the outer first conductivity type layer A gate is provided via an insulating film on a high-resistance second conductivity type region between the regions, and one common electrode is in contact with the low-resistance second conductivity type region and a first conductivity type region sandwiching the region. In a method for manufacturing a semiconductor device, when forming a first conductivity type region in a second conductivity type region, a gate made of polycrystalline silicon is provided over the high resistance first conductivity type region with an insulating film interposed therebetween. Later,
Using the gate as a mask, impurities are introduced to form one first conductivity type region, then an insulating protective film is coated, an opening is provided above the center of the first conductive type region, and then the insulating protective film is formed. By etching the first conductivity type region as a mask, the first conductivity type region is divided to expose a second conductivity type low resistance region in the center, and the insulating protective film is further etched to divide the first conductivity type region. 1. A method for manufacturing a semiconductor device, comprising: exposing both exposed portions, and forming a common electrode in contact with both exposed portions.