JPH03209773A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03209773A JPH03209773A JP418690A JP418690A JPH03209773A JP H03209773 A JPH03209773 A JP H03209773A JP 418690 A JP418690 A JP 418690A JP 418690 A JP418690 A JP 418690A JP H03209773 A JPH03209773 A JP H03209773A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- point metal
- high melting
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000002844 melting Methods 0.000 claims abstract description 40
- 230000008018 melting Effects 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 150000002736 metal compounds Chemical class 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 6
- 239000011574 phosphorus Substances 0.000 claims abstract description 6
- 150000001875 compounds Chemical class 0.000 claims abstract description 4
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 14
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 14
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 210000004709 eyebrow Anatomy 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- GNKTZDSRQHMHLZ-UHFFFAOYSA-N [Si].[Si].[Si].[Ti].[Ti].[Ti].[Ti].[Ti] Chemical compound [Si].[Si].[Si].[Ti].[Ti].[Ti].[Ti].[Ti] GNKTZDSRQHMHLZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野１
本発明は、ＭＯＳ型電界効果トランジスタの構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to the structure of a MOS field effect transistor.
従来のＭＯＳ型電界効果トランジスタにおける埋め込み
コンタクトの構造は、ゲート電極と同一の構造を持つ配
線が、ソース、あるいは、ドレインの部分のシリコン基
板に直接接触し、ソース電極、あるいはドレイン電極の
少なくとも一方の電極を形成するものであった。In the structure of a buried contact in a conventional MOS field effect transistor, a wiring having the same structure as the gate electrode is in direct contact with the silicon substrate in the source or drain part, and the wiring has the same structure as the gate electrode. It was intended to form an electrode.
［発明が解決しようとする課朋１
しかし、前述の従来技術では、回連イオンによる閾値電
圧の不安定性を少なくするために、−Ｍ的に、燐を含ん
だ多結晶シリコン膜を、あるいは、燐を含んだ多結晶シ
リコンと高融点金属の積層膜（ポリサリイド構造）をゲ
ート電極、ソース電極、あるいはドレイン電極に用いて
いるため、Ｎ形ＭＯＳ型電界効果トランジスタのみにし
か埋め込みコンタクトの構造を使用できないという間朋
点を有していた。[Problem to be Solved by the Invention 1 However, in the above-mentioned conventional technology, in order to reduce the instability of the threshold voltage due to repeated ions, -M-wise, a polycrystalline silicon film containing phosphorus or Since a laminated film (polysalide structure) of polycrystalline silicon containing phosphorus and a high-melting point metal is used for the gate, source, or drain electrodes, a buried contact structure is used only for N-type MOS field effect transistors. I had a certain point that I couldn't do it.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは１Ｍ４を含んだ多結晶シリコンと
高融点金属の積層膜（ポリサリイド構造）をゲート電極
に用いながら、Ｎ形、及び、Ｐ形ＭＯ５型電界効果トラ
ンジスタに、埋め込みコンタクトが可能な半導体装置を
提供するところにある。The present invention is intended to solve these problems, and its purpose is to use a stacked film (polysalide structure) of polycrystalline silicon containing 1M4 and a high-melting point metal for the gate electrode, and to The present invention provides a semiconductor device in which a buried contact can be made to a P-type MO5 field effect transistor.
［ｉｌ １Ｍを解決するための手段］
本発明の半導体装置は、ゲート電極が、シリコンを主成
分とする膿と、第１の高融点金属化合物膜と、高融点金
属あるいは第２の高融点金属化合物膜の積層膜、あるい
は、シリコンを主成分とする膿と、高融点金属あるいは
第２の高融点金属化合物膜の積層膜からなり、ソース電
極、あるいはドレイン電極の少なくとも一方の電極が、
少なくとも埋め込みコンタクト領域のみ、前記第１の高
融点金属化合物膜と、高融点金属あるいは第２の高融点
金属化合物膜の積層膜からなることを特徴とする。[Means for Solving Il 1M] In the semiconductor device of the present invention, the gate electrode is made of pus mainly composed of silicon, a first high melting point metal compound film, and a high melting point metal or a second high melting point metal. A laminated film of a compound film, or a laminated film of a pus mainly composed of silicon and a high melting point metal or a second high melting point metal compound film, and at least one of the source electrode and the drain electrode is
At least only the buried contact region is characterized by being made of a laminated film of the first high melting point metal compound film and a high melting point metal or a second high melting point metal compound film.
［実 施 例］
第１図は、本２発明の実施例における半導体装置の断面
図を示す、１０１は、Ｎ形シリコン基板、１０２は、シ
リコン酸化膜、１０３は、ゲート酸化膜、１０４はＮ型
多結晶シリコン膜、１０５は、硅化チタニウム膿、１０
６は、硅化モリブデン膜、１０７は、Ｐ膨拡散層、１０
８は、眉間絶縁膜、１０９は、アルミニウム配線膜であ
る１本実施例のように、ゲート電極を燐を含んだＮ形多
結晶シリコン膜と硅化チタニウム膜と硅化モリブデン膜
で形成することによって、回連イオンによる閾値電圧の
不安定性を少なくなり、ソース、あるいは、ドレイン電
極は、シリコン基板上に形成された硅化チタニウム膜と
、その上に積層された硅化モリブデン膜によって、直接
、シリコン基板に接触し、ゲート電極、及び、埋め込み
コンタクト領域の電極形成後に、ソースおよびトレイン
拡散を１行うことによって、同一タイプの不純物がシリ
コン基板上に形成された硅化チタニウム膓と、その上に
積層された硅化モリブデン瞑、及びその直下のシリコン
基板、及びそれに隣接するジノコン基板に拡散されるた
めに、Ｎ形はもちろんのことＰ形ＭＯ５型電界効果トラ
ンジスタにおいても、ソースあるいはドレインから直接
シリコン基板に接続し、自己整合的に電極をとることが
可能となる。[Embodiment] FIG. 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the second invention. 101 is an N-type silicon substrate, 102 is a silicon oxide film, 103 is a gate oxide film, and 104 is an N-type silicon substrate. type polycrystalline silicon film, 105, titanium silicide, 10
6 is a molybdenum silicide film, 107 is a P swelling diffusion layer, 10
8 is an insulating film between the eyebrows, and 109 is an aluminum wiring film.1 As in this embodiment, by forming the gate electrode with an N-type polycrystalline silicon film containing phosphorus, a titanium silicide film, and a molybdenum silicide film, The instability of the threshold voltage due to circulating ions is reduced, and the source or drain electrode is in direct contact with the silicon substrate through the titanium silicide film formed on the silicon substrate and the molybdenum silicide film laminated thereon. After forming the gate electrode and the buried contact region electrodes, one source and train diffusion is performed to inject the same type of impurity into the titanium silicide layer formed on the silicon substrate and the molybdenum silicide layered thereon. In order to diffuse into the silicon substrate immediately below it, and the Zinocon substrate adjacent to it, in not only N-type but also P-type MO5 field effect transistors, the source or drain is directly connected to the silicon substrate, and the self It becomes possible to take the electrodes in a consistent manner.
次に、本発明の製造方法について第１図を用いて説明す
る。まず、Ｎ形シリコン基板１０１に、シリコン酸化膜
１０２を形成し、活性領域２０１にゲート酸化１ｌｌｌ
Ｏ３を２０ｎｍ成長し、その上にＣＶＤ法により多結晶
シリコン膜を２００ｎｍ成長し、燐の雰囲気中で多結晶
シリコン膜に燐を拡散し、Ｎ形多結晶シリコン膜及びゲ
ート酸化膜をホトエツチング法により、埋め込みコンタ
クト領域のみ除去する。Next, the manufacturing method of the present invention will be explained using FIG. 1. First, a silicon oxide film 102 is formed on an N-type silicon substrate 101, and a gate oxide film 1llll is formed on the active region 201.
20 nm of O3 is grown, a 200 nm polycrystalline silicon film is grown on it by CVD, phosphorus is diffused into the polycrystalline silicon film in a phosphorous atmosphere, and the N-type polycrystalline silicon film and gate oxide film are photoetched. , only the buried contact area is removed.
次に、その上に、チタニウムを５０ｎｍスパックー法に
より蒸着し、ハロゲンランプにより８００℃３０秒加熱
し、硅化チタニウムにかえた後、スパッターエツチング
を行い、硅化モリブデン膜を２００ｎｍスパックー法に
より蒸着し、ホトエツチング法により、配線領域以外の
硅化チタニウム膜と硅化モリブデン賎あるいは、硅化モ
リブデン膜と硅化チタニウム膜とＮ形多結晶シリコン膿
を除去し、第１図に示すＮ型多結晶シリコン膜１０４、
と硅化チタニウムｌ１ｉ１０５と硅化モリブデン１０Ｂ
を形成する。Next, a 50 nm film of titanium was deposited using the Spac-method, heated for 30 seconds at 800°C using a halogen lamp, and then sputter etched after changing to titanium silicide. The titanium silicide film and molybdenum silicide film, or the molybdenum silicide film, titanium silicide film, and N-type polycrystalline silicon pus in areas other than the wiring area are removed by the method, and the N-type polycrystalline silicon film 104 shown in FIG.
and titanium silicide l1i105 and molybdenum silicide 10B
form.
最後に、Ｎ型多結晶シリコンＩＩ！１０４と硅化モリブ
デン１１１０６をマスクにして、硼素を２×１０”ｃｍ
−”イオン打ち込みし、Ｐ膨拡散層１０７を形成した後
、ＣＶＤ法により、酸化シリコン膜を６００ｎｍ成長し
、眉間絶縁ｉ１！ １０ Ｂを形成し、１０００℃２０
分アニールを行い、スルーホールを眉間絶縁１！ １０
８に開け、アルミニウムを１１０００ｎスパツタ法によ
り蒸着し、所望のパターンにホトエツチング法により加
工し、アルミニウム配線１１１１０９を形成する。Finally, N-type polycrystalline silicon II! Using 104 and molybdenum silicide 11106 as a mask, apply boron to 2 x 10”cm.
-" After ion implantation and forming the P expansion diffusion layer 107, a silicon oxide film was grown to a thickness of 600 nm by CVD method, forming a glabellar insulation i1!10 B, and heating at 1000° C. 20
Anneal for 1 minute and insulate the through hole between the eyebrows! 10
8, aluminum is deposited by 11000n sputtering method, and processed into a desired pattern by photoetching method to form aluminum wiring 111109.
以上の工程を経て、本発明の半導体装！が充成する。After the above steps, the semiconductor device of the present invention is completed! will be fulfilled.
上記実施例では、Ｐ形ＭＯＳ型電界効果トランジスタに
ついて説明したが、Ｎ形ＭＯＳ型電界効果トランジスタ
においても、ソース、ドレイン形成のためのイオン打ち
込み不純物タイプが異なるだけで、同様に実施でき、又
、相補形ＭＯＳ型電界効果トランジスタにも実施できる
。さらには、第１の金属としてチタニウム膜を用いて説
明したが、モリブデン膜、タングステン膿などの高融点
金属でも同等の効果が得られ、また第２の金属として、
硅化モリブデン膜を用いて説明したが、硅化タングステ
ン肋、硅化チタニウム膜などの高融点金属化合物や、モ
リブデン賎、タングステン膿などの高融点金属でも同等
の効果が得られる。さらには、シリサイド化の際のスト
レスによるゲート膜破壊を少なくするために、高濃度の
燐を含む多結晶シリコン上にシリサイドができにくいこ
とをつがい、選択的にシリサイド化を行い、ゲート領域
に硅化チタニウム謹を形成しないことも可能である０本
発明の趣旨を逸脱しない範囲において、種々変更可能な
事は言うまでもない。In the above embodiment, a P-type MOS field effect transistor was described, but the same method can be applied to an N-type MOS field effect transistor, with the only difference being the type of ion implantation impurity for forming the source and drain. It can also be implemented in complementary MOS type field effect transistors. Furthermore, although the explanation has been made using a titanium film as the first metal, the same effect can be obtained with a high melting point metal such as a molybdenum film or tungsten.
Although the explanation has been made using a molybdenum silicide film, the same effect can be obtained with a high melting point metal compound such as a tungsten silicide rib or a titanium silicide film, or a high melting point metal such as molybdenum paste or tungsten pus. Furthermore, in order to reduce gate film breakdown due to stress during silicidation, we took advantage of the fact that silicide is difficult to form on polycrystalline silicon that contains a high concentration of phosphorous, and selectively silicided the gate region. It is also possible not to form titanium. It goes without saying that various changes can be made without departing from the spirit of the present invention.
［発明の効果］
以上述べたように本発明によれば、ゲート電極が、シリ
コンを主成分とする膜と、第１の高融点金属化合物膜と
、高融点金属あるいは第２の高融点金属化合物膜の積層
膜、あるいは、シリコンを主成分とする膿と、高融点金
属あるいは第２の高融点金属化合物膜の積層膜からなり
、ソース電極、あるいはドレイン電極の少なくとも一方
の電極が、少なくとも埋め込みコンタクト領域のみ、前
記第１の高融点金属化合物膜と、高融点金属あるいは第
２の高融点金属化合物膜の積層膜からなることにより、
燐を含んだ多結晶シリコンと高融点金属の積層１ｍ（ポ
リサリイド構造）をゲート電極に用いながら、Ｎ形、及
び、Ｐ形ＭＯＳ型電界効果トランジスタにおいて、埋め
込みコンタクトが可能となり、相互配線の自由度が高く
なり、回連イオンにたいして安定な相補形ＭＯＳ型電界
効果トランジスタ集積回路が、よりコンパクトできると
いう効果を有する。更には、第２の高融点金属化合物膜
である硅化モリブデン膜が、シリコン基板との化合物で
ある第１の高融点金属化合物膜硅化チタニウム膜を介し
てシリコン基板に接続しているため、硅化モリブデン膜
とシリコン基板との接触抵抗が低下するという効果を有
する。[Effects of the Invention] As described above, according to the present invention, the gate electrode includes a film mainly composed of silicon, a first high melting point metal compound film, and a high melting point metal or a second high melting point metal compound. It consists of a laminated film of a film, or a laminated film of a film mainly composed of silicon and a high melting point metal or a second high melting point metal compound film, and at least one of the source electrode and the drain electrode is connected to at least the buried contact. Only the region is made of a laminated film of the first high melting point metal compound film and the high melting point metal or the second high melting point metal compound film,
By using a 1 m laminated layer (polysalide structure) of phosphorous-containing polycrystalline silicon and a high-melting point metal for the gate electrode, buried contacts are possible in N-type and P-type MOS field effect transistors, allowing for greater freedom in interconnection. This has the effect that the complementary MOS type field effect transistor integrated circuit, which is stable against repeated ions, can be made more compact. Furthermore, since the molybdenum silicide film, which is the second high melting point metal compound film, is connected to the silicon substrate via the first high melting point metal compound film, titanium silicate film, which is a compound with the silicon substrate, molybdenum silicide This has the effect of reducing the contact resistance between the film and the silicon substrate.
第１図は、本発明の半導体装置の一実施例を示す主要断
面図。
０１
０２
０３
０４
０５
０６
０７
０８
Ｎ形シリコン基板
シリコン酸化膜
ゲート酸化膜
Ｎ型多結晶シリコン膜
硅化チタニウム膜
硅化モリブデン膜
Ｐ膨拡散層
眉間絶縁膜
０９
アルミニウム配線月莫
以
上FIG. 1 is a main sectional view showing an embodiment of a semiconductor device of the present invention. 01 02 03 04 05 06 07 08 N-type silicon substrate Silicon oxide film Gate oxide film N-type polycrystalline silicon film Titanium silicide film Molybdenum silicide film P-swelled diffusion layer Insulating film between the eyebrows 09 Aluminum wiring Over the moon
Claims (3)
１の高融点金属化合物膜と、高融点金属あるいは第２の
高融点金属化合物膜の積層膜、あるいは、シリコンを主
成分とする膜と、高融点金属あるいは第２の高融点金属
化合物膜の積層膜からなり、ソース電極、あるいはドレ
イン電極の少なくとも一方の電極が、少なくとも埋め込
みコンタクト領域のみ、前記第１の高融点金属化合物膜
と、高融点金属あるいは第２の高融点金属化合物膜の積
層膜からなるＭＯＳ型電界効果トランジスタを含むこと
を特徴とする半導体装置。(1) The gate electrode is a laminated film of a film whose main component is silicon, a first high-melting point metal compound film, and a high-melting point metal or a second high-melting point metal compound film, or whose main component is silicon. and a high melting point metal or a second high melting point metal compound film, and at least one of the source electrode and the drain electrode is connected to the first high melting point metal compound film at least in the buried contact region. 1. A semiconductor device comprising a MOS field effect transistor made of a laminated film of a high melting point metal or a second high melting point metal compound film.
る多結晶シリコン膜であることを特徴とする請求項１記
載の半導体装置。(2) The semiconductor device according to claim 1, wherein the film containing silicon as a main component is a polycrystalline silicon film containing phosphorus.
シリコン基板との化合物である硅化高融点金属膜である
ことを特徴とする請求項１記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the first high-melting point metal compound film is a silicided high-melting point metal film that is a compound of a high-melting point metal and a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP418690A JPH03209773A (en) | 1990-01-11 | 1990-01-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP418690A JPH03209773A (en) | 1990-01-11 | 1990-01-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03209773A true JPH03209773A (en) | 1991-09-12 |
Family
ID=11577676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP418690A Pending JPH03209773A (en) | 1990-01-11 | 1990-01-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03209773A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230044292A (en) | 2020-08-13 | 2023-04-03 | 도쿄엘렉트론가부시키가이샤 | Electrode part of semiconductor device and manufacturing method thereof |
-
1990
- 1990-01-11 JP JP418690A patent/JPH03209773A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230044292A (en) | 2020-08-13 | 2023-04-03 | 도쿄엘렉트론가부시키가이샤 | Electrode part of semiconductor device and manufacturing method thereof |
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