JP3049255B2 - Method for manufacturing CMIS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a complementary MOS having a structure in which a same-polarity gate, that is, a PMOS has a p-type gate electrode and an NMOS has an n-type gate electrode.
(CMOS), generally, the manufacture of complementary insulated gate (CMIS) semiconductor devices.

[Summary of the Invention]

In the structure of the CMIS according to the present invention, for example, an oxide film serving as an n-type impurity source selectively converts polycrystalline Si to an n-type with respect to a polycrystalline Si film to be used as a gate electrode. Polycrystalline Si is selectively formed, and the electrical connection between the n-type and p-type polycrystals is made by using a refractory metal on the polycrystalline Si or a silicide film thereof.

[Conventional technology]

Conventionally, the gate electrode of CMIS has been mainly made of n-type polycrystalline Si for both PMOS and NMOS.However, in order to obtain CMIS with a low threshold voltage of, for example, 0.5 V or less, a unipolar gate structure is effective. Have been. In manufacturing the same polarity gate structure CMIS, connection of gate electrodes having different conductivity types becomes a problem. In the connection method using the conventional metal wiring, the integration density is sacrificed, and the use of the silicide technology has been technically unstable.

[Problems to be solved by the invention]

The present invention has been made to solve the above problems in an easy manner using existing established techniques.

[Means for solving the problem]

The method of manufacturing the same-polarity gate CMIS semiconductor device according to the present invention comprises:
Providing a gate oxide film on each of the surface of the p-type silicon substrate and the p-well and depositing a polycrystalline Si film, for example, an oxide film diffusion source selectively containing an n-type impurity on the polycrystalline film on the p-well Forming a polycrystalline film using the oxide film as a mask, selectively adding a p-type impurity to the polycrystalline film, removing the oxide film, and depositing a thin film of a refractory metal or a silicide thereof on the polycrystalline film. Process and the thin film and the polycrystalline film
It comprises a step of providing each gate electrode and wiring in a layered structure, and a step of forming a PMOS on an n-type substrate and an NMOS on a p-well.

[Action]

The p-type and n-type polycrystalline Si are automatically connected with a thin film of a refractory metal or a silicide on it, and the conventional CM
The same integration density as OS can be obtained. In addition, the same-polarity gate structure can be formed by adding a single mask process.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

(1) Example 1 (FIGS. 1 and 2) FIG. 1 is a schematic plan view of a CMOS according to the present invention, and FIGS. A-
It is A 'line sectional drawing. FIG. 2 (a) shows that an n-type Si substrate 10 is provided with a p-well 11, a separation field oxide film 5 is formed, and a gate oxide film 6 is formed in an n-type active region 1 and a p-well 11 in the same manner as in a normal CMOS manufacturing process. This is a cross-section in which a polycrystalline Si film 20 has been grown on the entire surface after being deposited thereon. In this case, the polycrystalline film 20 is undoped or has a low impurity density. FIG. 2 (b)
A diffusion source oxide film 7 to which an n-type impurity, for example, phosphorus is added, is deposited so as to entirely cover the polycrystalline film 20 on the p well 11, and is selectively left, and the other polycrystalline film 20 is masked using the oxide film 7 as a mask. Shows a state in which a p-type impurity such as boron is selectively added. As a result, an n-type polycrystalline film 23 and a p-type polycrystalline film 24 are selectively formed as the polycrystalline film 20. As the diffusion source oxide film 7, for example, SOG (Spin On Glass) or doped oxide containing phosphorus is used, and a CVD oxide film is provided thereon as necessary. For the selective addition of boron, ion implantation, pre-deposition, or the like is applied. For example, the density of phosphorus or boron
It is about 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ . FIG. 2C shows a state in which, for example, a silicide film 25 is deposited on the polycrystalline films 23 and 24 after removing an oxide film on the polycrystalline films 23 and 24 such as the diffusion source oxide film 7. Examples of the silicide film 25 include WSix and
A MoSix CVD film or a sputtered film is applied. Also, a high melting point metal such as W or Mo can be used instead of silicide. In FIG. 2D, for example, the silicide film 25 and the polycrystalline films 23 and 24 are collectively selectively etched in the shape of FIG. 1 to form a gate electrode 2 made of polycide (Silicide, poly Si2 layer structure).
1, 22 and wiring (composed of p, n polycrystalline films 124, 123 and silicide film 125) are provided. The p and n polycrystalline films 124 and 123 are connected by a silicide film 125. Thereafter, as shown in FIG. 2 (e), the n ⁺ source
Drain regions 111 and 112 and p ⁺ source / drain region 21
1,212 are provided, an interlayer insulating film 8 is deposited, contact holes are formed,
After forming each metal wiring 101, 102, 201, 202, 225, NMOS 100
And a CMOS consisting of PMOS 220 is completed.

〔The invention's effect〕

As described above, according to the present invention, it has a unipolar gate structure.
CMOS is realized without reducing the integration density by adding one mask process to the conventional manufacturing process. The present invention is not limited to the example shown in the embodiment, and the conductivity type of each region can be reversed.
It can also be applied to structures and LDD structures. The gate insulating film is not limited to an oxide film, but is generally applicable to CMIS. Further, since the present invention uses a silicide or a high melting point metal for a part of the wiring, the present invention is also excellent in high-speed operation.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a CMOS according to the present invention, and FIG.
1A to 1E show AA 'of FIG. 1 along the manufacturing process.
It is a line sectional view. 1,10 n-type region 6 gate oxide film 7 diffusion oxide film 11 p-well 20 polycrystalline Si 23 n-type polycrystalline 24 p-type polycrystalline 25,125 Silicide 100 …… NMOS 200 …… PMOS

Claims (2)

(57) [Claims] 1. A gate insulating film is provided on each of the surfaces of a first semiconductor region of one conductivity type and a second semiconductor region of a reverse conductivity type,
A first step of forming a field oxide film for separating the first semiconductor region and the second semiconductor region and then depositing a polycrystalline semiconductor film over the entire surface; and, following the first step, the first semiconductor region And an oxide film containing an impurity of the opposite conductivity type selectively on the polycrystalline semiconductor film in a part of the field insulating film continuously with the first semiconductor region; and CVD on the oxide film. A second step of forming a CVD oxide film by the following step; and, subsequent to the second step, selectively using the oxide film containing the opposite conductivity type impurity and the CVD oxide film as a mask to selectively form one conductivity type impurity in the polycrystalline semiconductor film. And removing the oxide film containing the opposite conductivity type impurity and the CVD oxide film, and depositing a thin film of a high melting point metal or a silicide thereof on the polycrystalline semiconductor film. And the fourth step A fifth step of selectively etching the thin film and the polycrystalline semiconductor film into a predetermined shape to provide each gate electrode and a wiring on the field oxide film, following the fourth step; Forming a reverse conductive channel transistor in the first semiconductor region and a single conductive channel transistor in the second semiconductor region. 2. The method of manufacturing a CMIS semiconductor device according to claim 1, wherein said impurity of the opposite conductivity type is phosphorus.