JP2971083B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a structure of a static RAM (SRAM) having a thin film transistor.

(Prior Art) An example of a circuit diagram of a conventional SRAM cell having a thin film transistor is shown in FIG. This SRAM cell has 4
N-channel MOSFETs Q1, Q2, Q3, and Q4 and two p-channel MOSFETs Q5 and Q6, and p-channel MOSFETs Q5 and Q6
Are constituted by thin film transistors.

An example of the pattern of the SRAM cell is shown in FIG. A solid line indicates an n-type diffusion layer, and a broken line indicates a thin film. Four n-channel MOSFETs are formed on a semiconductor substrate, and two p-channel MOSFETs are stacked thereon to form one SRAM cell. At this time, since the diffusion layer of the MOSFET on the semiconductor substrate is formed in a self-aligned manner using the polysilicon gate electrode as a mask, the diffusion layer (source, drain) of the n-channel MOSFET has a single concentration in the SRAM cell. . This situation will be described with reference to FIGS. 4th
The figures show cross-sectional views in respective steps along the line AA 'in FIG.

As shown in FIG. 4 (a), the n-type silicon substrate 1
An element isolation region 3 made of a silicon oxide film is formed in the p well region 2 formed in the step (a). A gate insulating film is formed on the exposed surface of the p-well region, and a gate electrode of an n-channel MOSFET is selectively formed on the gate insulating film. This gate electrode 5 is made of polysilicon. Gate electrode 5
Is used as a mask to perform ion implantation 6 of an n-type impurity, for example, As or P, to form an n-type impurity diffusion region 7 in a self-aligned manner as shown in FIG. 4 (b). next,
As shown in FIG. 4C, an insulating film 8 is formed on the entire surface, and a channel region 9 of a p-type thin-film MOS transistor is selectively formed on the diffusion region 7a. Further, a source / drain wiring layer 10 of a p-type thin film MOS transistor is formed on the element isolation region 3.

In such a conventional technique, the diffusion layer of the n-channel MOSFET is formed in a self-aligned manner using the polysilicon gate electrode 5 as a mask.
The source and drain of ET had the same concentration.

By the way, in the conventional SRAM cell, since the drain regions 7a of the n-channel MOSFETs Q1 and Q2 on the substrate serving as driver transistors are used as the gate electrodes of the stacked p-channel MOSFETs Q3 and Q4, the p-channel MOSFETs Q3 and Q4
In order to improve the performance, the gate insulating film 8 of the p-channel MOSFETs Q3 and Q4 had to be thinned.

However, the concentrations of the source and drain regions of the n-channel MOSFETs Q1 and Q2 have the same concentration as described above, and are usually about 1 × 10 ²⁰ cm ⁻³ in order to reduce the resistance of the source and drain regions. High concentrations had to be achieved. Therefore, there are problems that gate leakage of the p-channel MOSFETs Q3 and Q4 occurs and that the p-channel MOSFETs Q3 and Q4 cannot be set to a high withstand voltage.

(Problems to be Solved by the Invention) As described above, in the conventional SRAM cell having the p-channel MOSFET stacked on the n-channel MOSFET, gate leakage of the p-channel MOSFET occurs,
There was a problem that ET could not be made high withstand voltage. The problem of the gate withstand voltage described above is a problem that is particularly conspicuous when a conductive layer serving as a source, a drain, and a channel region of a thin film transistor is formed by depositing amorphous silicon.

SUMMARY OF THE INVENTION The present invention has been made to avoid the above-described problems, and has been made in an SRAM cell having an n-channel MOSFET stacked on an n-channel MOSFET.
It is an object of the present invention to provide a stacked p-channel MOSFET having high performance and high reliability without reducing the driving force and speed of the p-channel MOSFET.

[Means for Solving the Problems] A semiconductor device according to the present invention for solving the above problems includes a plurality of n-channel MOSFETs formed on a semiconductor substrate.
And one of the n-channel MOSFETs
In a static RAM memory cell, a drain diffusion layer is used as a gate electrode, and a source, a drain, and a p-channel MOSFET in which a channel region is formed on a conductive film stacked on the drain diffusion layer. The concentration of the drain diffusion layer of the one n-channel MOSFET is lower than that of the other n-channel MOSFET.

(Operation) Since the concentration of the drain diffusion layer is set lower than that of the source diffusion layer, the gate breakdown voltage of the pMOSFET is improved.

In addition, the problem of a decrease in the driving power of the driver transistor, which is a concern due to the low concentration of the drain diffusion layer of the driver transistor, is to reduce the concentration of only the drain diffusion layer, increase the concentration of the source diffusion layer, and reduce the current of the driver transistor. There is no problem because the operation is performed in the saturation region.

The asymmetry caused by the difference in resistance between the source diffusion layer and the drain diffusion layer causes no problem since the two driver transistors in the cell are used symmetrically.

Therefore, according to the present invention, a highly reliable SRAM cell can be obtained without deteriorating performance.

Embodiment An embodiment of an SRAM cell according to the present invention will be described with reference to FIG. FIG. 1 is a sectional view of the SRAM cell, and the circuit diagram and pattern of this SRAM cell are the same as those shown in FIGS. 2 and 3, respectively.

As shown in FIG. 1 (a), after a p-well region 2 and an element isolation region 3 are formed on the surface of a single-crystal n-type silicon substrate 1, a silicon oxide film 4 is formed by dilution oxidation using HCl.
To form a gate insulating film. Next, after opening the direct contact formation portion, a polycrystalline silicon film is selectively deposited by a low pressure CVD (LPCVD) method to about 400 nm, and POCl ₃ is deposited.
P (phosphorus) is introduced into the polycrystalline silicon film using a gas. Thereafter, the polycrystalline silicon film is patterned by using a resist to form an n-type gate electrode 5. When the gate electrode 5 is formed, the insulating film other than the gate insulating film 4 existing under the gate electrode 5 is removed. Therefore, after the gate electrode 5 is formed, the insulating film 4a is formed on the front surface.

Thereafter, an n-type impurity P (phosphorus) or As (arsenic) is introduced into the p-well region 2 by ion implantation 11 in a self-aligned manner with respect to the gate electrode 5 using the gate electrode 5 as a mask.

Thereafter, as shown in FIG. 1B, a selectively patterned resist 15 is formed, and a second n-type impurity p (phosphorus) or a p-type impurity is formed in a region to be a high-concentration n-type diffusion layer (source). As (arsenic) is introduced by ion implantation 12.

Thereafter, as shown in FIG. 1 (c), a thermal process, for example,
Annealing at 850 ° C. for 30 minutes in an N ₂ atmosphere forms diffusion layers 13 and 14 of n-channel MOSFETs having different concentrations.
The low concentration diffusion layer 13 functions as a drain, and the high concentration diffusion layer 14 functions as a source.

Thereafter, the thickness of the gate oxide film 8 of the p-channel MOSFET is made desired by oxidation in an O ₂ atmosphere. Next, after opening a contact hole with the first polycrystalline silicon film 5, a conductive layer film 9 serving as a channel, a source, and a drain of the thin film transistor is formed on the gate oxide film 8. The conductive film 9 is formed by depositing an amorphous silicon film in a SiH ₄ atmosphere at 550 ° C. and then locally monocrystallizing the amorphous silicon film by annealing in a N ₂ atmosphere at 600 ° C. for 2 hours. Is done.

Then, the conductive film 9 is patterned by resist patterning.
The channel portion of the n-type or p-type impurities, the source of the conductive film 9, the drain and the wiring portion 10 to 1 × 10 ¹⁵ cm ^-2
About a p-type impurity is ion-implanted. Then 800 ℃, 3
Annealing in an N ₂ atmosphere for about 0 minutes allows p-channel M
The diffusion layer (source, drain) of OSFET is formed.

Then, after depositing a SiO ₂ film by the CVD method, contacts are formed in desired regions for the gate, source, and drain of the n-channel MOSFET. Then, using an Ar target containing about 1% of Si, a first Al wiring layer is deposited by sputtering and patterned. After that, plasma CV
After depositing a SiO ₂ film by D, a contact portion for the first layer of Al wiring is opened, and the second layer of Al wiring is changed to the first layer of Al.
It is deposited and patterned in the same manner as the wiring layer. Then, after depositing a SiN film as a passivation film on the surface by plasma CVD, the passivation film in the pad portion is removed.

As described above, the SRAM cell of the present invention is formed.
In this SRAM cell, the impurity concentration of the drain diffusion layer 13 of the driver transistor is set lower than the impurity concentration of the source diffusion layer 14.

The present invention is not limited to the above embodiments. The gate electrode of the thin-film p-channel MOSFET is connected to two n-channel MOSFETs as driver transistors formed on a semiconductor substrate.
May be formed on the drain diffusion layer.

Further, the gate electrode of the p-channel MOSFET may be formed further above the conductive film serving as the source, drain and channel regions.

The conductive film forming the source, drain, and channel region of the p-channel MOSFET may be made of a polycrystalline silicon film.

Further, a low-concentration region having the same conductivity as the source and drain portions may be provided in a region on the gate electrode side of the source and the drain of the p-channel MOSFET.

Still further, the present invention has been described with respect to a single-port SRAM cell using six MOSFETs. However, the present invention is not limited to the number of MOSFETs, but includes a plurality of n-channel MOSFETs, of which at least one n-channel MOSFET is provided. p channel
The present invention can be applied to all cells in which MOSFETs are stacked as described above, for example, a dual-port SRAM cell.

[Effect of the Invention] According to the present invention, the impurity concentration of the drain diffusion layer of the n-channel MOSFET also serving as the gate electrode of the p-channel MOSFET is made lower than that of the other n-channel MOSFETs. The withstand voltage of a gate insulating film of a certain p-channel MOSFET is improved, and a highly reliable static RAM can be obtained.

[Brief description of the drawings]

1 (a) to 1 (c) are views for explaining the configuration of the SRAM cell of the present invention, and are cross-sectional views along the line AA 'in FIG. 3, and FIG. 2 uses thin film transistors. FIG. 3 is a circuit diagram of an SRAM cell, FIG. 3 is a pattern diagram of an SRAM cell using a thin film transistor, and FIG. 4 is a diagram for explaining a configuration of a conventional SRAM cell, and is taken along the line AA 'in FIG. FIG. 1... N-type silicon substrate, 2... P-well region, 3.
Element isolation region, 4, 8 gate insulating film, 5 gate electrode of n-channel MOSFET, 6 ion implantation of n-type impurity, 7 diffusion region of n-type impurity, 9 thin-film p-channel MOSFET Channel part of the thin film p-channel MOSFET
, Source and drain wiring portions, 11, 12,..., Ion implantation of n-type impurities, 13,..., Low-concentration n-type impurity diffusion layers, 14,.
High-concentration n-type impurity diffusion layer, 15 resist.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/092 H01L 27/11 H01L 21/8238 H01L 21/8244

Claims (1)

(57) [Claims] 1. A plurality of n-channels formed on a semiconductor substrate
A MOSFET and one of the n-channel MOSFETs
A memory cell of a static RAM in which a drain diffusion layer of a MOSFET is used as a gate electrode and a p-channel MOSFET in which a source, a drain, and a channel region are formed in a conductive film laminated on the drain diffusion layer is used. 2. The semiconductor device according to claim 1, wherein the concentration of the drain diffusion layer of the one n-channel MOSFET is lower than that of the other n-channel MOSFET.