JPH0330470A - Semiconductor device - Google Patents

Abstract

PURPOSE:To restrain the diffusion of impurity from a gate electrode and hot carriers from deteriorating so as to obtain a complementary FET device stable and excellent in electrical properties by a method wherein the thickness of the gate insulating film of a second conductivity type FET is all or partially formed of an insulating film which contains semiconductor and nitrogen. CONSTITUTION:A surface type first conductivity type FET and a second conductivity tape FET, which are provided with gate electrodes 8 and 13 formed on a semiconductor substrate 1 through the intermediary of gate insulating films 7 and 12 respectively, are formed on the same semiconductor substrate 1 to constitute a semiconductor device, where the gate insulating film 7 of the first conductivity type FET is formed of a semiconductor oxide film and the thickness of the insulating films 7 and 12 of the second conductivity type FET is wholly or partially formed of an insulating film 12 which contains semiconductor and nitrogen. For instance, a gate electrode 13 is formed on the channel region of a P channel FET through the intermediary of an insulating layer of a two-layered structure composed of a silicon oxide film 7 and a silicon nitride film 12 formed thereon, and the gate electrode 13 concerned is formed of P-type impurity highly concentrated poly-silicon.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention relates to
The present invention relates to a semiconductor device in which gate insulating films of a channel FET and a P-channel FET are formed with insulating films having different properties.

(Prior art) N-channel and P-channel MOS type FETs (
In a CMO8 semiconductor device using a 71i field effect transistor), its gate insulating film is usually formed of a polysilicon film doped with N-type impurities at a high concentration. For this reason, the P-channel FET is of a so-called buried type in which P-type impurity ions are implanted into the channel region from the viewpoint of one-week adjustment of the threshold value. This embedded FET
As the channel length decreases, the bunch-through breakdown voltage decreases, and it becomes difficult to control the concentration and thickness of the N-type layer formed on the surface layer of the substrate due to the increase in substrate concentration.

Therefore, in order to miniaturize the CMOS l conductor device, a CMOS structure in which both the N-channel and P-channel FETs are surface type is effective.

Such a structure uses an N-channel FE as a gate electrode.
This can be achieved by using polysilicon heavily doped with N-type impurities for T-channel FETs, and by using polysilicon heavily doped with P-type impurities for P-channel FETs.

In such a structure, when the gate insulating film is formed of a silicon oxide film, boron doped into the polysilicon forming the gate electrode of the P channel easily diffuses into the silicon oxide film.

This has caused instability in threshold control due to changes in impurity concentration in the channel region and depletion of the gate electrode.

Therefore, in order to suppress the diffusion of boron from the gate electrode of a P-channel FET, a silicon nitride film or a silicon oxynitride film ( It is effective to insert a silicon nitride oxide film).

This silicon nitride film or silicon oxynitride film has many electron traps in it. Therefore, when the above-mentioned insulating film is included in the gate insulating film, the N-channel FET has many hot electrons existing near the silicon/insulating film interface and hot electrons generated by collision ionization of these hot electrons. but,
Hot carriers are easily captured by traps in the insulating film and cause deterioration of hot carriers. Therefore, this hot carrier deterioration causes deterioration and instability of electrical characteristics such as a low channel current and a fluctuation in threshold value.

(Problems to be Solved by the Invention) As explained above, in the conventional surface type CMOS structure semiconductor device, the gate insulating film is common to both the N-channel FET and the P-channel FET. Therefore, when the gate insulating film is formed of a silicon oxide film, P
Boron, an impurity doped into the polysilicon forming the gate electrode of the channel FET, was easily diffused from the gate electrode through the silicon oxide film. This results in
This caused fluctuations and deterioration of electrical characteristics, leading to a decrease in reliability.

On the other hand, if part or all of the thickness of the gate insulating film is formed of silicon nitride film or silicon oxynitride III in order to suppress boron diffusion,
Hot carriers tend to cause deterioration in N-channel FETs. For this reason, even when the gate insulating film is formed using the above-mentioned insulating film, the electrical characteristics may fluctuate or deteriorate, resulting in lower reliability.

In this way, impurity diffusion from the gate electrode in P-channel FET and N-channel FET
It was not possible to suppress the deterioration of hot carriers.

Therefore, the present invention has been made in view of the above, and its purpose is to suppress the diffusion of impurities from the gate mi and the deterioration of hot carriers to obtain stable and good electrical characteristics. The object of the present invention is to provide a 16-conductor device consisting of complementary FETs that can be used.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, a surface-type first conductivity type semiconductor device having a gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween; In a semiconductor device in which a second conductivity type FET (field effect transistor) is formed on the same semiconductor substrate, the present invention provides that the gate insulating film of the first conductivity type FET is made of a semiconductor oxide film; Conductivity type F E
The gist of the T gate insulating film is that part or all of its thickness is made of an insulating film containing a conductor and nitrogen.

(Function) In the above structure, the present invention prevents diffusion of impurities from the gate electrode of the second conductivity type FET by using a gate insulating film containing a semiconductor and nitrogen in the second conductivity type FET. Further, the gate insulating film made of a semiconductor oxide film in the first conductivity type FET suppresses deterioration of hot carriers.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a sectional view showing the structure of a 1'-conductor device according to an embodiment of the present invention. An embodiment of the present invention shown in FIG.
In a structure in which an N-channel FET and an N-channel FET are formed to function complementary to each other, the gate insulating film of the N-channel FET is silicon oxidized. It is characterized in that the gate insulating film of the P channel F E 'r is formed of a two-layer insulating film consisting of a silicon oxide film and a silicon nitride film.

First, the structure of this embodiment will be explained with reference to FIG.

In FIG. 1, a P-well 2 serving as an N-channel FET formation region and an N-well 3 serving as a P-channel FET formation region are formed adjacent to each other in the surface layer of a P-type silicon substrate 1. . A field oxide film 4 serving as an element isolation region is formed around each well region.

In the P-well 2, a source region 5 and a drain region 6 of an N-channel FET are formed at a predetermined distance apart on the surface thereof. A gate electrode 8 of an N-channel FFE is formed on a channel region formed in the P well 2 sandwiched between these source regions 5 and drain regions 6 with a gate insulating film made of a silicon oxide film 7 interposed therebetween. There is. This gate electrode 8 is made of polysilicon doped with an N-type impurity or a high degree of 1 degree, and is surrounded by a silicon post-oxide film as a wave source.

In the N-well 3, a source region 10 and a drain region 1 of a P-channel FET are formed at a predetermined distance apart on the surface thereof.
1 is formed. On the channel region formed in the N well 3 sandwiched between the source region 10 and the drain region 11, there are two layers consisting of a silicon oxide film 7 and a silicon nitride film 12 laminated on this oxide +1!7. The gate electrode 13 of the P-channel FET is connected through the grooved gate insulating film.
or is formed. This gate electrode 13 is made of polysilicon heavily doped with P-type impurities, and its periphery is protected by a silicon post-oxide film 9.

In the N-channel FET and P-channel FET, electrode wiring 14 is formed in each source region 5.10,
An electrode wiring 14 is formed in each drain region 6.11 so as to connect the inner regions. Also, both FE
An interlayer insulating film 15 is formed on the surface of the T.

Next, a method for manufacturing a semiconductor device having the above-described structure will be described with reference to manufacturing process cross-sectional views shown in FIGS. 2(a) to 2(j).

First, we will go up to the level of normally used CMOS and P-well 2.
, an N well 3 is formed adjacent to the surface layer of the substrate 1.

Thereafter, a field oxide film 4 is formed to surround each well region using the LOGO5 technique to perform element isolation (FIG. 2(a)).

Next, the surfaces of the P well 2 and N well 3, which will be the regions where both FETs will be formed, are thermally oxidized to form the gate oxide film 5.
A silicon oxide film 7 having a thickness of about 0 to 100 Å is formed (FIG. 2(b)).

Next, a silicon nitride film 12 of 10 to 2O
It is deposited to a thickness of about A. Then P channel FE
The region where the T is to be formed is covered with a resist (not shown), and by using this resist as a mask, the silicon nitride film 12 remains only on the silicon oxide film 7 on the N-well 3, which is the region where the P-channel FET is to be formed. A portion of the silicon nitride film 12 is etched and removed as shown in FIG. Next, the resist is removed. Note that after this, the surface of the remaining silicon nitride film 12 may be slightly oxidized by post-oxidation. (Figure 2 (C)).

Next, a non-doped polysilicon film [6] is deposited on the entire surface by CVD.
The film is deposited to a thickness of about 2,000 to 4,000 Å using a method. Thereafter, the deposited polysilicon film 16 is patterned using a resist mask so as to become the gate electrodes 8 and 13 of both FETs (FIG. 2(d)).

Next, a silicon post-oxidation film 9 is formed on the exposed surface of the polysilicon film 16 by post-oxidation (FIG. 2(e)).

Next, the area where the P channel FET is to be formed is covered with a resist 17, and using this resist 17 as a mask, the P channel FET is formed.
Ion implantation of arsenic, which will become a mold impurity, is carried out at an implantation energy of about 30 KeV and a dose of about 2×10"'cm-2. As a result, the exposed polysilicon film 1
Arsenic is introduced into the P-well 2 on both sides of the polysilicon film 16 to form the source region 5 and drain I'+R region 6 of the N-channel FET so that the junction depth is relatively shallow. The gate electrode 8 of the N-channel FET is formed by doping at a high concentration (FIG. 2(f)). Next, after removing the first nodist 17 from the previous step, the N-channel FET
Cover the area where the ET is to be formed with a resist (not shown),
Using this resist as a mask, BF containing N-type impurities is
2 (boron fluoride) ion implantation is performed under the same conditions as arsenic ion implantation.

As a result, boron is introduced into the N-well 3 on both sides of the exposed polysilicon film 16, and a P-channel FET is formed.
The source region 10 and drain region 11 are formed so that the junction depth is relatively shallow, and polysilicon]4
A gate electrode 3 of the P-channel FET is formed by doping boron at a high concentration (FIG. 2(g)).

Next, after removing the resist I from the previous step I5, a silicon oxide film which will become the interlayer insulating film 15 is deposited over the entire surface by CVD (FIG. 2(h)).

Next, source regions 5. of both FETs. A contact hole] 9 is formed on the i, o and drain regions 6 and 11. Thereafter, the element region of the P-channel FET was covered with a resist (not shown), and arsenic was implanted at an implantation energy of 60 K e V I'd degree and a 1-Z dose of about 5 x 1.0"cm'. Perform ion implantation.Subsequently, P channel FET
Remove the resist covering the device region of the N-channel F
The ET element region is modulated with a resist (not shown), and BF2 ions are implanted under the same conditions as the arsenic ion implantation described above. This allows the source region 5.10 of both FETs to
A portion of the drain region 6.11 that contacts the electrode wiring 14 is formed deeply. This is source area 5
When the electrode wiring 14 is formed in the electrode wiring 10 and the drain region 6, 111, the source region 5, 10 and the drain region 611, which are formed relatively shallowly, are destroyed by the weight of the electrode wiring 14, so that contact failure does not occur. Source area 5.
This is a step for imparting strength to the drain regions 10 and drain regions 6 and 11 (FIG. 2(i)).

Finally, after depositing, for example, aluminum on the entire surface,
This aluminum is buttered and contact hole 1 is formed.
The electrode wiring 14 of the source region 510 of both FETs is formed in 9, and the electrode wiring 14 is formed so as to connect the drain regions 6.11 of both FETs, thereby completing the semiconductor device having the structure shown in FIG. Figure 2 (j)).

In the structure shown in FIG. 1 formed by such a manufacturing method, the gate insulating film of the N-channel FET is formed of silicon oxide film 7.

For this reason, carrier deterioration that occurs when part or all of the gate insulating film is formed with a nitrogen-containing insulating film such as a silicon nitride film or a silicon oxynitride film is caused by the N-channel FET. Does not occur.

Furthermore, the gate insulating film of the P-channel FET includes a silicon nitride film 12. Therefore, P channel FE
The diffusion of the P-type impurity boron introduced into the T gate electrode 13 is inhibited by the silicon nitride film 12.

On the other hand, in P-channel FETs, the carriers are 11-holes, and the impact ionization coefficient of holes is about two orders of magnitude smaller than that of electrons, so impact ionization occurs, resulting in hot electrons and holes. The occurrence of pairs is less than that of N-channel FETs. As a result, in a P-channel FET, the amount of hot electrons near the silicon-oxide film interface or the N-channel FET
It is extremely small compared to ET. Therefore, in P-channel FET, due to hot carrier deterioration or N-channel FE
It is significantly suppressed compared to T, and no decrease in channel current or fluctuation in threshold value occurs.

In this way, in the above-described structure, diffusion of impurities from the gate electrode and deterioration of hot carriers can be prevented, and fluctuations and deterioration of electrical characteristics can be suppressed.

Next, another embodiment of the invention will be described.

FIG. 3 is a sectional view showing the structure of a semiconductor device according to another embodiment of the invention. A feature of the embodiment shown in FIG. 3 is that a silicon oxynitride film is used as the gate insulating film of the P-channel FET. Even such a structure can be realized by a manufacturing process substantially similar to the manufacturing process described above, and will be described below with reference to the process cross-sectional diagram shown in FIG. 4.

First, after going through the same steps as shown in FIGS. 2(a) and 2(b), non-doped polysilicon 1!1116 is deposited on the entire surface, phosphorus is diffused, and then the gate of the N-channel FET is The polysilicon Ill 1.6 is patterned so that only the polysilicon film 16 that will become the electrode remains. Thereafter, the polysilicon film 16 is oxidized to form a silicon post-oxide film 9 on the exposed surface of the polysilicon film 16 (FIG. 4(a)).

Next, a silicon oxide film 2 that functions as a resist is applied to the entire surface.
1 by CVD method, P-channel FET
The silicon oxide film 21 on the region where the N-channel FET is to be formed is removed, and the region where the N-channel FET is to be formed is covered with the silicon oxide film 21 (FIG. 4(b)).

Next, a silicon oxide film (not shown) having a thickness of approximately 50 to 100 Å is formed on the surface of the N well 3 in the region where the P channel FET is to be formed. After that, the lamp annealing process was performed in an ammonia atmosphere at a temperature of about 950°C.
Annealing is performed for 0 seconds, and further annealing is performed for 60 seconds in a dry oxygen atmosphere at a temperature of about 1150°C. As a result, a silicon oxynitride film 20 is formed as the gate insulating film of the P-channel FET (see FIG. 4).
C)).

Next, after a non-doped polysilicon film 16 is deposited over the entire surface, this polysilicon film 16 is patterned to become a gate electrode of a P-channel FET. Subsequently, the surface of the patterned polysilicon film 16 is thermally oxidized to form a silicon post-oxide film 9 on the exposed surface of the polysilicon film 16 (FIG. 4(d)).

Next, in a process similar to that shown in FIG. 2(g), the source region IO and drain region 11 and gate electrode 13 of the P-channel FET are formed by ion implantation of arsenic and BF2 (FIG. 4(e)). ).

Next, after removing the silicon oxide film 21 that functions as a resist, a process similar to that shown in FIG. 2(f) is performed.
A source region 5, a drain region 6, and a gate electrode 8 of an N-channel FET are formed.

Next, through the steps shown in FIG. 2(h) and FIG. 2(i), the device having the structure shown in FIG. 3 is completed.

Even in such a structure, since only the gate insulating film of the P-channel FET is formed of an insulating film containing a silicon nitride film, the same effects as in the embodiments described above can be obtained.

Note that the present invention is not limited to the above-mentioned embodiments, and the gate insulating film of the P-channel FET may be made of only a silicon nitride film, or the surface of a two-layer film consisting of a silicon oxide film and a silicon nitride film laminated thereon. Oxidized three-layer insulating film,
Or an insulating film formed by nitriding a silicon oxide film,
Alternatively, the same effect can be obtained using an insulating film formed by nitriding a silicon thermal oxide film and then oxidizing it.

[Effects of the Invention] As explained above, according to the present invention, the first conductivity type FET and the second conductivity type FET are connected to function as complementary types.
Since the gate insulating films of conductive FETs are formed with insulating films of different film quality, instability and fluctuations in electrical characteristics are suppressed, stable and good device characteristics are obtained, and reliability is greatly improved. can be improved.

[Brief explanation of drawings]

FIG. 1 is a structural cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view showing one manufacturing method of the device shown in FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a cross-sectional view of the structure of the semiconductor device according to the present invention, and FIG. 4 is a process cross-sectional view showing one method of manufacturing the device shown in FIG. DESCRIPTION OF SYMBOLS 1... Silicon, 1 board, 2-P well, 3... N well, 5... Source region of N channel FET, 6... Drain region of N channel FET, 7... Silicon oxide film, 8...N-channel FET gate electrode, 10...
Source region of P-channel FET, 11... Drain region of P-channel FET, 12... Silicon nitride film, 13... Gate electrode of P-channel FET, 20...
Silicone oxynitride film.

Claims (2)

[Claims] (1) A semiconductor in which surface-type first conductivity type and second conductivity type FETs (field effect transistors) each having a gate electrode formed on the semiconductor substrate via a gate insulating film are formed on the same semiconductor substrate. In the device, the gate insulating film of the first conductivity type FET is made of a semiconductor oxide film, and the gate insulating film of the second conductivity type FET is partially or entirely made of an insulating film containing a semiconductor and nitrogen. A semiconductor device characterized by: (2) The insulating film is a silicon nitride film or a silicon
Claim 1 characterized in that it is an oxynitride film.
The semiconductor device described.