JPH05291573A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a high withstand voltage semiconductor device and a method for manufacturing the same which can deal with miniaturization of a semiconductor integrated circuit. CONSTITUTION:A drain diffused region 6 and a source diffused region 7 are so formed as to form a channel region on a main surface of a p-type semiconductor substrate 12, and a recess 9 having a predetermined depth is formed partly in the channel region. A gate electrode 5 is formed on the channel region 9 including the recess 9 through a gate insulating film 3a so set that its film thickness becomes relatively thick.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high breakdown voltage electric field capable of improving the breakdown voltage between a source and a drain by increasing the effective channel length of a field effect transistor. The present invention relates to a structure of an effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art The miniaturization of semiconductor integrated circuits is advancing without stopping, but a factor limiting the miniaturization is the breakdown voltage (BVsd) between the source and drain of a transistor (hereinafter simply referred to as "breakdown voltage"). Here, the determinants of the breakdown voltage of the MOS transistor will be briefly described. When a high voltage (a high positive voltage in the case of an N-channel type transistor) is applied to the drain region of the MOS transistor, the pn junction between the drain region and the substrate is reversely biased. As a result, the depletion layer expands,
The depletion layer finally reaches the source region and a current flows between the source / drain regions even though no voltage is applied to the gate electrode. Such a phenomenon is called a punch through phenomenon. The voltage at which such a punch-through phenomenon occurs is called the "breakdown voltage" in this case. The punch-through phenomenon remarkably occurs in a transistor having a short gate size. It is considered that this is because the channel length becomes shorter as the gate size becomes smaller. Then, the minimum gate size that does not cause such a punch-through phenomenon is the minimum usable gate size.

In miniaturization of semiconductor integrated circuits, it is required to reduce the above-mentioned minimum usable gate size. Then, in order to further reduce the minimum usable gate dimension, the expansion of the depletion layer in the channel direction is suppressed by taking measures such as thinning the gate oxide film and increasing the substrate impurity concentration. However, in this case, although the expansion of the depletion layer can be suppressed, the depletion layer is formed in a narrow region near the drain region and the gate electrode, so that a high electric field is eventually generated in that portion. Therefore, in order to further reduce the minimum usable gate size, it is necessary to reduce the absolute value of the breakdown voltage.

Here, a more specific description will be given with reference to FIGS. 38 and 39. FIG. 38 shows a conventional MO
It is sectional drawing which shows an example of an S transistor. As shown in FIG. 38, element isolation oxide film 110 is formed in the element isolation region on the main surface of p-type semiconductor substrate 112. In the element formation region on the main surface of p-type semiconductor substrate 112, n-type drain diffusion region 106 and source diffusion region 107 are formed at intervals so as to define a channel region. A gate electrode 105 is formed on the channel region via a gate insulating film 104. Further, the p + isolation layer 113 is formed at a predetermined depth position in the p-type semiconductor substrate 112.

In the MOS transistor having the above structure, a predetermined potential is applied to the drain diffusion region 106,
By applying a predetermined potential also to the gate electrode 105, a current will flow between the source / drain diffusion regions. 38, the above gate size means
The width W of the gate electrode 105 in FIG. The channel length means the length of the gate electrode 105 in the width direction. As described above, with the miniaturization of the semiconductor integrated circuit, the width W of the gate electrode 105 (hereinafter referred to as “gate size”) is also reduced. As a result, the channel length becomes short, and it can be said that the above punch-through phenomenon easily occurs.

FIG. 39 shows the absolute value (V) of the breakdown voltage and the gate dimension (μm) when the expansion of the depletion layer in the channel direction is suppressed (condition A) and when it is not suppressed (condition B).
It is a figure which shows the relationship with. In this case, the condition A is a case where the gate oxide film thickness is 180Å. The condition B is a case where the gate oxide film thickness is 280Å. As shown in FIG. 39, under the condition A, the absolute value of the breakdown voltage is about V, which is smaller than the absolute value 14V of the breakdown voltage under the condition B. However, the minimum usable gate size is smaller in the case of condition A than in the case of condition B. That is, as described above, it can be said that the breakdown voltage is forced to take a small value with the miniaturization of the gate dimension.

[0007]

Since the power supply voltage of an ordinary MOS LSI is 5 V or less, there is a sufficient margin even if the breakdown voltage is lowered to about 11 V as in the case of the above condition A. However, in devices such as EPROM and EEPROM that use a high voltage of 12 V or more during writing, it can be said that the decrease in absolute value of the breakdown voltage becomes a serious problem. Further, also in such a device, an increase in the degree of integration is required as in the case of other devices, and accordingly, miniaturization of a planar gate dimension is an essential requirement. In this case, since the MOS transistor having the conventional structure as described above has a small absolute value of withstand voltage, it is used as it is for a device such as EPROM or EEPROM which handles a high voltage of 12 V or more inside the circuit. There is a problem that you can not do it.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a high breakdown voltage field effect transistor which can cope with miniaturization and a manufacturing method thereof.

[0009]

In the semiconductor device according to the present invention, a recess for increasing the effective channel length is formed in the channel region of the first transistor in the first conductivity type semiconductor substrate. Then, on the main surface of the semiconductor substrate, the second conductivity type source / drain is formed so as to define the channel region at a position sandwiching the recess. Further, a gate insulating film is formed on the channel region including the recess, and a gate electrode is formed on the gate insulating film.

In another aspect of the semiconductor device according to the present invention, the field effect transistor further includes a second transistor formed on a flat main surface of a semiconductor substrate. The thickness of the gate insulating film is larger than the thickness of the gate insulating film of the second transistor.

In still another aspect, the semiconductor device according to the present invention has a first well, which is an impurity diffusion region of the first conductivity type, on the main surface of the semiconductor substrate, and a first well having an impurity concentration higher than that of the first well. A second well, which is an impurity diffusion region of one conductivity type, is formed, a first transistor is formed on the first well, and a second transistor is formed on the second well. Then, in such a semiconductor device, a recess for increasing the effective channel length is formed in a portion of the first well which becomes the channel region. The first transistor has a second conductivity type source / source formed on the main surface of the semiconductor substrate so as to define a channel region at a position sandwiching the recess.
It has a drain region. The first transistor is
A gate insulating film formed on the channel region including the above-mentioned recess and a gate electrode formed on the gate insulating film are provided.

According to the method of manufacturing a semiconductor device according to the present invention, first, a desired element formation region on the main surface of a semiconductor substrate is selectively thermally oxidized to form a local oxide film extending into the substrate. To do. Then, by removing this local oxide film, a recess is formed in a desired element formation region, and a gate electrode is formed on this recess via a gate insulating film. Then, the source / drain regions of the transistor are formed on the main surface of the semiconductor substrate at positions sandwiching the recess.

In another aspect of the method of manufacturing a semiconductor device according to the present invention, first, a recess having a desired depth is formed in a desired element forming region on the main surface of a semiconductor substrate by etching. Then, a gate electrode is formed on the recess via a gate insulating film, and source / drain regions of the transistor are formed at positions on the main surface of the semiconductor substrate that sandwich the recess.

[0014]

According to the semiconductor device of the present invention, in one aspect, the recess is formed in the portion which will be the channel region of the first transistor. Thereby, the effective channel length of the first transistor can be increased. That is, when a voltage is applied to the drain region of the transistor, the depletion layer expands, but the distance until the depletion layer expands and reaches the source region can be substantially lengthened. As a result, the breakdown voltage of this transistor can be improved.

In another aspect, the semiconductor device according to the present invention is premised on that a second transistor is further provided on the flat main surface of the semiconductor substrate. In this case, the thickness of the gate insulating film of the first transistor is set to be larger than the thickness of the gate insulating film of the second transistor. Thereby, in the first transistor, the spread of the depletion layer is relatively difficult to be suppressed, and the possibility of generating a high electric field due to electric field concentration in the vicinity of the gate electrode and the drain region can be reduced.
That is, this first transistor can allow the application of a high voltage. Here, the first transistor has a long effective channel length because the recess is formed in the channel region as described above. As a result, the range in which the expansion of the depletion layer can be allowed increases. That is, the breakdown voltage of the transistor is improved.

In still another aspect of the semiconductor device according to the present invention, the impurity concentration of the first well in which the first transistor is formed is set relatively low. As a result, the first transistor can allow the application of a high voltage. Here, the first transistor has a long effective channel length because the concave portion is formed in the channel region thereof. As a result, the allowable amount of expansion of the depletion layer of the first transistor when a high voltage is applied increases. That is, the breakdown voltage of the first transistor can be increased.

According to the method of manufacturing a semiconductor device according to the present invention, in one aspect, a local oxide film expanded into the substrate by selectively thermally oxidizing a desired element formation region on the main surface of the semiconductor substrate. And then removing this local oxide film makes it possible to form a recess in a desired element formation region. Then, source / drain regions are formed at positions sandwiching the recess. This makes it possible to increase the effective channel length of the field effect transistor. As a result, the breakdown voltage of this field effect transistor can be improved.

According to another aspect of the method of manufacturing a semiconductor device of the present invention, a recess having a desired depth is formed in a desired element formation region on the main surface of a semiconductor substrate by etching. Then, the source / drain regions of the transistor are formed at positions sandwiching this recess. As a result, the effective channel length of this field effect transistor can be lengthened and the breakdown voltage of this transistor can be improved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following is a diagram showing a case where the present invention is applied to an N-channel type MOS transistor in which two types of transistors, a high voltage transistor and a low voltage transistor, are formed on the same semiconductor substrate. It will be explained using.

FIG. 1 is a sectional view of a semiconductor device including a high voltage MOS transistor according to an embodiment of the present invention. Referring to FIG. 1, in this figure, a high breakdown voltage MO
The case where the S transistor formation region 1 and the normal MOS transistor formation region 2 are adjacent to each other is shown. Then, in the high breakdown voltage MOS transistor formation region 1, a recess 9 is formed in a portion which becomes a channel region of the transistor. The depth of the recess 9 is preferably 0.2 μm, and the width of the recess 9 in the channel length direction is preferably
It is 0.4 μm. Further, the shape of the concave portion 9 is preferably a smooth shape having no protrusion that causes electric field concentration. Then, on the main surface of the p-type semiconductor substrate 12,
A source diffusion region 7 and a drain diffusion region 6 are formed at a position so as to sandwich the recess 9 with a space therebetween. Then, 2 is formed on the channel region of this MOS transistor.
The gate electrode 5 is formed via the gate insulating film 3a having a thickness of about 50Å. The thickness of the gate insulating film 3a is preferably 200 to 300Å.

On the other hand, the structure of the MOS transistor formed adjacent to the above high breakdown voltage MOS transistor is as follows.
Similar to the conventional example, the source diffusion region 7 and the drain diffusion region 6 are formed at predetermined positions on the main surface of the p-type semiconductor substrate 12 at intervals so as to define the channel region. Then, on the channel region, 180
The gate electrode 5 is formed via the gate insulating film 4 having a film thickness of about Å. Further, a p + isolation layer is formed at a predetermined depth position of the p-type semiconductor substrate 12. Further, in the element isolation region on the main surface of the p-type semiconductor substrate 12, the element isolation oxide film 10 is spaced apart.
Are formed.

In the high breakdown voltage MOS transistor having the above structure, by increasing the thickness of the gate insulating film 3a to about 250 Å, the voltage that can be applied to the high breakdown voltage MOS transistor can be increased to 14V. And
In order to cope with the decrease in punch-through breakdown voltage due to the thickening of the gate insulating film 3a as described above, a recess 9 having a predetermined depth is formed in the p-type semiconductor substrate 12, and a channel is formed at the position where the recess 9 is formed. Forming a region. Thereby, the effective channel length can be increased. as a result,
The allowance for the expansion of the depletion layer is increased, and the punch-through breakdown voltage is improved. Further, in this case, the planar gate dimension of the gate electrode 5 can be adjusted by the shape, depth, width, etc. of the recess 9. Therefore, it can be said that it is possible to flexibly deal with the planar reduction of the gate dimension due to the miniaturization.

Next, a method of manufacturing a semiconductor device including a high voltage MOS transistor having the above structure will be described with reference to FIG.
~ It demonstrates using FIG. 2 to 10 are cross-sectional views showing first to ninth steps in the manufacturing process of the semiconductor device including the high breakdown voltage MOS transistor according to the present invention.

Referring to FIG. 2, a well-known selective oxidation method (LO) is formed in the element isolation region on the main surface of p-type semiconductor substrate 12.
COS method) is used to selectively perform thermal oxidation to form a thick element isolation oxide film 10 of about 5000 Å. At the same time when the element isolation oxide film 10 is formed,
A thick oxide film 10a is formed in a part of the high breakdown voltage MOS transistor formation region. In this case, the thickness of the thick oxide film 10a is approximately the same as the thickness of the element isolation oxide film 10 described above. Further, in this embodiment, the thick oxide film 10a is replaced by the element isolation oxide film 10
Although formed at the same time, the thick oxide film 10a may be formed in a step different from the element isolation oxide film 10 forming step. In this case, the thickness of the thick oxide film 10a can be adjusted variously.

Next, as shown in FIG. 3, a resist pattern 21 is formed by a photolithography technique so as to cover the high breakdown voltage MOS transistor forming region, and the resist pattern 21 is used as a mask to perform the element implantation by an ion implantation method. Boron (B) for increasing the isolation withstand voltage of 3 × 10 ¹³ c
Implantation is performed under the conditions of m ⁻² and accelerating voltage of 200 KeV. Thereby, the p + isolation layer 13 is formed under the element isolation oxide film 10.

Next, referring to FIG. 4, after removing the resist pattern 21 described above, a resist pattern 22 having an opening in the high breakdown voltage MOS transistor forming region is formed by photolithography, and hydrofluoric acid (HF) is used. The thick oxide film 10a is etched using an aqueous solution such as). Thereby,
Recesses 9 are formed in a part of the high breakdown voltage MOS transistor formation region on the main surface of p type semiconductor substrate 12. After that, as shown in FIG. 5, ion implantation is performed using the resist pattern 22 as a mask, so that a necessary amount of boron (B) ions for determining the threshold voltage (Vth) of the high breakdown voltage MOS transistor is obtained. inject.

The element isolation oxide film 1 in the present embodiment.
Since the 0 formation step and the channel doping step are indispensable steps for forming a normal MOS transistor, a photolithography step is newly added to obtain the structure of the MOS transistor according to the present invention. It can be said that there is no need to do it.

Next, as shown in FIGS. 5 and 6, after the resist pattern 22 is removed, the underlying oxide film 10b formed when the element isolation oxide film 10 is formed is hydrofluoric acid (H).
It is removed by etching using an aqueous solution such as F). And
By performing the thermal oxidation process, the gate insulating film 3 having a film thickness of about 180 Å is formed. After that, as shown in FIG. 7, a resist pattern 23 is formed so as to cover the high breakdown voltage MOS transistor formation region by using a photoengraving technique, and the resist pattern 23 is used as a mask to remove an aqueous solution of hydrofluoric acid (HF) or the like. Then, the gate insulating film 3 formed in the element forming region other than the high breakdown voltage MOS transistor forming region is removed by etching.

After that, as shown in FIG. 8, after removing the resist pattern 23, a thermal oxidation process is performed to have a film thickness of about 180 Å in the element forming regions other than the high breakdown voltage MOS transistor forming region. The gate insulating film 4 is formed. At this time, since the gate insulating film 3 is formed in advance in the high breakdown voltage MOS transistor formation region, the gate insulating films are stacked by the thermal oxidation process in this step, and as a result, the high breakdown voltage MOS transistor is formed.
In the transistor formation region, the gate insulating film 3a having a film thickness of about 250Å is formed.

Next, referring to FIG. 9, a polysilicon film 5 having a film thickness of about 3000 Å is formed on the element forming region by the CVD method, and phosphorus (P) or the like is formed on the polysilicon film 5. Are introduced by thermal diffusion to reduce the electric resistance value of the polysilicon film 5. Then, a resist pattern 24 patterned into a desired shape is formed on the polysilicon film 5 by a photoengraving technique, and the polysilicon film 5 is formed by plasma etching using CF ₄ plasma or the like with the resist pattern 24 as a mask. To etch.

Thereafter, as shown in FIG. 10, arsenic (As) ions are accelerated by an ion implantation method at an acceleration voltage of 40 Ke.
The drain diffusion region 6 and the source diffusion region 7 are formed by implanting under the condition of V, 4 × 10 ¹⁵ cm ⁻² . At this time, in order to activate the arsenic (As) injection layer injected for forming the drain diffusion region 6 and the source diffusion region 7, after performing a heat treatment at a temperature of about 900 ° C. for about 15 minutes in a nitrogen atmosphere, Reoxidation is performed by performing heat treatment at a temperature of about 900 ° C. for about 40 minutes in an oxygen atmosphere. Then, an interlayer insulating film by a known method,
A MOS transistor is formed by forming a contact hole and an aluminum wiring layer.

Next, another embodiment based on the present invention will be described with reference to FIGS. FIG. 11 is a sectional view of a semiconductor device including a high voltage MOS transistor according to another embodiment of the present invention. Referring to FIG. 11, the p-type semiconductor substrate 32 has the same structure as in the above embodiment.
A high breakdown voltage MOS transistor formation region 1 and a normal MOS transistor formation region 2 are provided adjacent to each other. In the high breakdown voltage MOS transistor formation region 1, a drain diffusion region 26 and a source diffusion region 27 are formed at a predetermined interval on the main surface of the p-type semiconductor substrate 32 so as to define a channel region. Then, a trench 34 having a predetermined depth is formed in the channel region. The depth of this trench 34 is preferably 2000Å-40
The size of the trench 34 is about 00Å, and the width of the trench 34 in the channel direction is preferably within the range of about 0.2 μm to 0.4 μm. A gate electrode 25 is formed on the channel region via a gate insulating film 23a having a film thickness of about 250Å. Further, the element isolation oxide film 30 is formed in the element isolation region of the p-type semiconductor substrate 32.
Under the element isolation oxide film 30, a p + isolation layer 33 for improving the isolation voltage between elements is formed.

On the other hand, in the normal MOS transistor formation region 2, a drain diffusion region 26 and a source diffusion region 27 are formed at a predetermined interval on the main surface of the p-type semiconductor substrate 32 so as to define a channel region. ing. And
A gate electrode 25 is formed on the channel region via a gate insulating film 24 having a film thickness of about 180Å.

In the MOS transistor formed in the high breakdown voltage MOS transistor formation region, since the trench 34 having a predetermined depth is formed in the channel region,
The effective channel length is long. This makes it possible to improve the breakdown voltage between the source / drain diffusion regions of this MOS transistor for the same reason as in the above-described embodiment.

Next, with reference to FIGS. 12 to 19, a method of manufacturing a semiconductor device including a high voltage MOS transistor according to this embodiment will be described. 12 to 19 are cross-sectional views showing first to eighth steps of the manufacturing process of the semiconductor device.

Referring to FIG. 12, a predetermined amount of p-type impurity such as boron (B) is injected into the element isolation region on the main surface of p-type semiconductor substrate 32, and then a known selective oxidation method (LOC) is performed.
By selectively performing thermal oxidation treatment using the OS method), the element isolation oxide film 30 having a film thickness of about 5000 Å is formed in the element isolation region. At this time, a p + isolation layer 33 for improving the isolation breakdown voltage between elements is formed under the element isolation oxide film 30.

Next, referring to FIG. 13, after etching away 30b formed at the time of forming element isolation oxide film 30 described above, a region which becomes a channel region of a high breakdown voltage MOS transistor is formed by using photolithography. A resist pattern 45 is formed by opening a part of it. Then, the resist pattern 45 is used as a mask to perform dry etching using CF ₄ plasma or the like to etch the p-type silicon substrate 32 by a predetermined amount, so-called trench 3
4 is formed.

Next, referring to FIG. 14, after removing the resist pattern 45 described above, a resist pattern 46 having an opening in a region which will be a channel region of the high breakdown voltage MOS transistor is formed by using a photolithography technique. .. Then, using the resist pattern 46 as a mask, oblique rotation ion implantation is performed to perform boron (B) ion implantation for adjusting the threshold voltage (Vth) of the high breakdown voltage MOS transistor.

Next, referring to FIG. 15, after removing the resist pattern 46, a thermal oxidation process is performed to form a gate with a film thickness of about 180Å on the surface of the p-type semiconductor substrate 32 in the element forming region. The insulating film 23 is formed. Then, as shown in FIG. 16, a resist pattern 47 is formed so as to cover the high breakdown voltage MOS transistor formation region by using the photoengraving technique.
Using 7 as a mask, using an aqueous solution of hydrofluoric acid (HF),
The gate insulating film 23 formed in the element forming region other than the high breakdown voltage MOS transistor forming region is removed by etching.

Next, referring to FIG. 17, after removing the resist pattern 47, thermal oxidation is performed again to form a film thickness of about 180 Å in the element forming regions other than the high breakdown voltage MOS transistor forming region. A gate insulating film 24 having is formed. At this time, since the high-voltage MOS transistor formation region is also subjected to the thermal oxidation treatment, the film thickness of the gate insulating film 23a formed on the high-voltage MOS transistor formation region is about 250Å. ..

Then, referring to FIG. 18, a polysilicon film 2 having a film thickness of about 3000 Å is formed on the element forming region on the main surface of p type semiconductor substrate 32 by the CVD method.
After forming 5, the polysilicon film 25 is subjected to a thermal diffusion process to introduce impurities such as phosphorus (P) to reduce the electric resistance value of the polysilicon film 25. afterwards,
A resist pattern 48 patterned into a desired shape is formed on the polysilicon film 25 by using a photolithography technique. Then, the polysilicon film 25 is etched by performing plasma etching using CF ₄ plasma or the like using the resist pattern 48 as a mask. Thereby, the gate electrode 25 is formed.

Next, referring to FIG. 19, the p-type semiconductor substrate 3 is formed by ion implantation using arsenic (As) ions under the conditions of an acceleration voltage of about 40 KeV and about 4 × 10 ¹⁵ cm ^-2.
Then, the drain diffusion region 26 and the source diffusion region 27 are formed. At this time, in order to activate the arsenic (As) injection layer injected to form the drain diffusion region 26 and the source diffusion region 27, a heat treatment is performed at about 900 ° C. for about 15 minutes in a nitrogen atmosphere. After that, reoxidation is performed by performing heat treatment at about 900 ° C. for about 40 minutes in an oxygen atmosphere. Thereafter, a MOS transistor is formed by forming an interlayer insulating film, a contact hole and an aluminum wiring layer by a known method.

Next, still another embodiment based on the present invention
This will be described with reference to FIGS. 20 to 29. Figure 20
Includes a high voltage MOS transistor in this embodiment.
FIG. 3 is a cross-sectional view showing a semiconductor device. Referring to FIG. 20,
High breakdown voltage MOS transistor in p-type semiconductor substrate 62
The formation region 1 has an impurity concentration of 1 × 10¹⁶cm^-3To a degree
The adjusted first p-type well 65 is formed. Well
In addition, a normal MOS transistor in the p-type semiconductor substrate 62
In the star formation region 2, the impurity concentration is 3 × 10.¹⁶cm ^-3Degree
The second p-type well 66 adjusted every time is formed.
In this way, the high breakdown voltage MOS transistor formation region 1 is formed.
The impurity concentration of the formed first p-type well 65 is relatively
By making it low, M formed in this region
It is possible to increase the voltage applied to the OS transistor.
Become.

In the high breakdown voltage MOS transistor formation region 1, a drain diffusion region 56 and a source diffusion region 57 are formed at a predetermined distance on the main surface of the p-type semiconductor substrate 62 so as to define a channel region. ing.
A recess 59 is formed in this channel region, and an MO formed in this region by this recess 59.
The effective channel length of the S transistor is long. The depth of the recess 59 is preferably 0.2 μm to
The width of the recess 59 in the channel length direction is preferably about 0.3 μm to 0.5 μm. In addition, the shape of the recess 59 is preferably a smooth shape having no protrusion that causes electric field concentration. As a result, the allowable amount for the expansion of the depletion layer is increased and the breakdown voltage between the source / drain diffusion regions is improved.

On the other hand, in the normal MOS transistor formation region 2, a MOS transistor having the same structure as the MOS transistor shown in the conventional example is formed. That is, the drain diffusion region 56 and the source diffusion region 57 are formed at a prescribed interval on the main surface of the p-type semiconductor substrate 62 in the normal MOS transistor formation region 2, and the gate insulation is formed on the channel region. A gate electrode 55 is formed via the film 53. An element isolation oxide film 60 is formed in the element isolation region on the main surface of the p-type semiconductor substrate 62. The element isolation oxide film 60 is formed.
A p + isolation layer 63 is formed below.

Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIGS.
21 to 29 are cross-sectional views showing the first to ninth steps in the manufacturing process of the semiconductor device having the above structure.

Referring to FIG. 21, a resist pattern 67 having an opening in high breakdown voltage MOS transistor formation region 1 in p-type semiconductor substrate 62 is formed using a photolithography technique. Then, using this resist pattern 67 as a mask, phosphorus (P) ions are implanted with an implantation amount of about 4 × 10 ¹² cm ⁻² . After that, as shown in FIG. 22, a resist pattern 68 having an opening in the normal MOS transistor formation region 2 is formed by using the photolithography technique. Then, using this resist pattern 68 as a mask, phosphorus (P) ions are ion-implanted with an implantation amount of about 1 × 10 ¹³ cm ^-2 . Then, in order to diffuse the phosphorus (P) ions to a desired depth, heat treatment is performed at 1180 ° C. for 6 hours.

Then, referring to FIG. 23, a thermal oxidation process is selectively performed using a known selective oxidation method (LOCOS method) to form a film of about 5000 Å in the element isolation region of p-type semiconductor substrate 62. An element isolation oxide film 60 having a thickness is formed. At this time, at the same time, a thick oxide film 60a is formed in a portion which will be a channel region in the high breakdown voltage MOS transistor formation region. This thick oxide film 60
Regarding the formation of a, the process for forming the thick oxide film 60a may be separated from the process for forming the element isolation oxide film 60, as in the above-described embodiment. The effect obtained thereby is similar to that of the above-described embodiment.

Next, as shown in FIG. 24, a resist pattern 69 is formed so as to cover the high withstand voltage MOS transistor forming region by using the photoengraving technique. Using this resist pattern 69 as a mask, boron (B) is 3 ×. 10 ¹³ c
Ion implantation is performed under the conditions of m ⁻² and an acceleration voltage of about 200 KeV. As a result, the p + isolation layer 63 is formed under the element isolation oxide film 60. Then, after removing the resist pattern 69, as shown in FIG. 25, the high breakdown voltage MOS transistor formation region 1 is formed by using the photolithography technique.
A resist pattern 70 having openings is formed. And
Using this resist pattern 70 as a mask, hydrofluoric acid (HF)
The thick oxide film 60a is removed using an aqueous solution such as the above. Thereby, the high breakdown voltage MOS transistor formation region 1
A recess 59 is formed in the main surface of p-type semiconductor substrate 62 in FIG.

Next, as shown in FIG. 26, by using the resist pattern 70 as a mask, boron (B) ions are ion-implanted in a necessary amount, so that a high breakdown voltage MOS is formed.
Channel doping is performed to determine the threshold voltage (Vth) of the transistor.

The above-mentioned step of forming the element isolation oxide film 60 and the step of channel doping are originally indispensable steps for forming a MOS transistor, and are taken in order to obtain a structure of a MOS transistor according to the present invention. It does not add a new plate-making process.

Referring to FIG. 27, after removing the resist pattern 70, underlying oxide film 60b patterned when forming element isolation oxide film 60 is removed by etching. After that, by applying a thermal oxidation treatment, p
A gate insulating film 53 having a film thickness of about 180 Å is formed on the surface of the element forming region on the main surface of the type semiconductor substrate 62. Then, as shown in FIG. 28, the gate insulating film 5
A polysilicon film 55 having a film thickness of about 3000 Å is formed on the surface 3 by a CVD method, and a resist pattern 71 patterned into a desired shape is formed on the polysilicon film 55 by photolithography. .. Then, the polysilicon film 55 is etched by performing plasma etching using CF ₄ plasma or the like using the resist pattern 71 as a mask. Thereby, the gate electrode 55 is formed.

Next, as shown in FIG. 29, arsenic (As)
The drain diffusion region 56 and the source diffusion region 57 of the transistor are formed by implanting ions with an accelerating voltage of about 40 KeV and about 4 × 10 ¹⁵ cm ^-2 .
In order to form the drain diffusion region 56 and the source diffusion region 57, heat treatment is performed at about 900 ° C. for about 15 minutes in a nitrogen atmosphere in order to activate the implantation layer of the implanted arsenic (As). And then 9 in an oxygen atmosphere
Reoxidation is performed by performing heat treatment at 00 ° C. for about 40 minutes. Thereafter, a MOS transistor is formed by forming an interlayer insulating film, a contact hole and an aluminum wiring layer by a known method.

Next, still another embodiment based on the present invention will be described with reference to FIGS. Figure 30
FIG. 9 is a sectional view showing a semiconductor device including a high voltage MOS transistor according to still another embodiment of the present invention. Referring to FIG. 30, in the p-type semiconductor substrate 92, the impurity concentration in the high breakdown voltage MOS transistor formation region 1 is 1 ×.
The first p-type well 95 adjusted to about 10 ¹⁶ cm ^-3 is formed, and in the normal MOS transistor formation region 2, the second p-type well adjusted to have an impurity concentration of about 3 × 10 ¹⁶ cm ^-3. 96 are formed. Then, on the main surface of the p-type semiconductor substrate 92 in the first p-type well 95,
A drain diffusion region 86 and a source diffusion region 87 are formed at a predetermined interval so as to define the channel region. Then, a trench 94 having a predetermined depth is formed in this channel region. In this case, the depth of the trench 94 is preferably about 2000Å to 4000Å, and the width of the trench 94 in the channel direction is preferably about 0.2 μm to 0.4 μm. The gate electrode 85 is formed on the channel region with the gate insulating film 83 interposed therebetween. Also in this case, as in the above-described embodiment, by providing the trench 94 in the channel portion, it is possible to increase the effective channel length. Thereby, the breakdown voltage between the source / drain diffusion regions of this MOS transistor having the trench 94 in the channel portion is improved for the same reason as in the above-described embodiment.

On the other hand, on the main surface of the p-type semiconductor substrate 92 in the above-mentioned second p-type well 96 region, a drain diffusion region 86 and a source diffusion region 87 are formed at a predetermined interval so as to define a channel region. ing. A gate electrode 85 is formed on the channel region with a gate insulating film 83 interposed therebetween. An element isolation oxide film 90 is formed in the element isolation region on the main surface of the p-type semiconductor substrate 92. A p + isolation layer 93 is formed under the element isolation oxide film 90.

Next, a method of manufacturing the semiconductor device having the above structure will be described with reference to FIGS. 31 to 37 are cross-sectional views showing first to seventh steps in the manufacturing process of this semiconductor device. Referring to FIG. 31,
On the surface of the p-type semiconductor substrate 92, using the photoengraving technique,
A resist pattern 97 having an opening in the high breakdown voltage MOS transistor formation region 1 is formed. Then, using this resist pattern 97 as a mask, phosphorus (P) ions are added at 5 × 10 ^12.
The first p-type well 95 is formed by implanting ions of about cm ⁻² . Next, as shown in FIG. 32, a resist pattern 98 having an opening in the normal MOS transistor formation region 2 is formed, and phosphorus (P) ions are ion-implanted at about 1 × 10 ¹³ cm ^{-2 using} this resist pattern 98 as a mask. By doing so, the second p-type well 96 is formed. At this time, phosphorus (P) ions are added to the p-type semiconductor substrate 9 to form the first p-type well 95 and the second p-type well 96.
1180 ° C. to diffuse to the desired depth of 2,
Heat treatment is performed for 6 hours.

Referring to FIG. 33, a p-type impurity such as boron (B) is introduced into the element isolation region on the main surface of p-type semiconductor substrate 92, and then a known selective oxidation method (LOC) is performed.
The element isolation oxide film 90 and the p + isolation layer 93 having a film thickness of about 5000 Å are formed by selectively performing thermal oxidation treatment by the OS method). After that, a resist pattern 9 in which a part of a region to be a channel region of the high breakdown voltage MOS transistor is opened is formed by using a photoengraving technique.
9 is formed, and the p-type silicon substrate 92 is etched by performing dry etching using CF ₄ plasma or the like using the resist pattern 99 as a mask. Thereby, the trench 94 having a predetermined depth is formed.

Next, referring to FIG. 34, after removing resist pattern 99, resist pattern 100 is formed in which high breakdown voltage transistor formation region 1 is opened. And
Boron (B) ions are introduced into the p-type semiconductor substrate 92 by the oblique rotation ion implantation method using the resist pattern 100 as a mask to adjust the threshold voltage (Vth) of the high breakdown voltage MOS transistor. Then, as shown in FIG. 35, after removing the resist pattern 100, a thermal oxidation process is performed to form a gate insulating film 83 having a film thickness of about 180 Å. Next, as shown in FIG. 36, 300 is formed on the p-type semiconductor substrate 92 by using the CVD method.
A polysilicon film 85 having a film thickness of about 0 Å is formed, and impurities such as phosphorus (P) are introduced into the polysilicon film 85 by a thermal diffusion method or the like to reduce the electric resistance value of the polysilicon film 85. After that, a resist pattern 101 patterned into a desired shape is formed on the polysilicon film 85 by using a photoengraving technique. Then, using the resist pattern 101 as a mask, the polysilicon film 85 is etched by plasma etching using CF ₄ plasma or the like. Thereby, the gate electrode 8
5 will be formed.

Next, referring to FIG. 37, arsenic (As) ions are accelerated on the main surface of p-type semiconductor substrate 92 at an acceleration voltage of 40K.
The drain diffusion region 86 and the source diffusion region 87 are formed by ion implantation under the conditions of about eV and about 4 × 10 ¹⁵ cm ⁻² . At this time, in order to activate the arsenic (As) injection layer injected for forming the drain diffusion region 86 and the source diffusion region 87, a heat treatment is performed at about 900 ° C. for about 15 minutes in a nitrogen atmosphere. After that, reoxidation is performed by further performing heat treatment at about 900 ° C. for about 40 minutes in an oxygen atmosphere. After that, an interlayer insulating film, a contact hole, and an aluminum wiring layer are formed by a known method to form a MOS.
A transistor will be formed.

[0060]

As described above, according to the present invention, since the recess is formed in the channel region of the field effect transistor, it is possible to increase the effective channel length. This makes it possible to improve the breakdown voltage between the source / drain regions. At this time, the voltage that can be applied to the field effect transistor is increased by adjusting the thickness of the gate insulating film of the field effect transistor that should have a high breakdown voltage or adjusting the well concentration to be thin. However, this results in a relatively large depletion layer spread.
In this case, the presence of the above-mentioned recess makes it possible to allow the depletion layer to spread. This makes it possible to improve the breakdown voltage between the source / drain regions. Further, according to the present invention, it is possible to deal with the case where the planar gate size is reduced. That is, it is possible to cope with the miniaturization of the semiconductor integrated circuit.

According to the manufacturing method of the present invention, a high breakdown voltage field effect transistor can be manufactured with the same number of masks as the conventional field effect transistor. Therefore, it can be said that a higher performance field effect transistor can be manufactured at substantially the same manufacturing cost. Also, since the channel length can be adjusted by the depth of the recesses, the degree of freedom in setting the conditions of the field effect transistor during manufacturing can be increased.

[Brief description of drawings]

FIG. 1 is a high breakdown voltage MO in one embodiment according to the present invention.
It is sectional drawing of the semiconductor device containing an S transistor.

FIG. 2 is a cross-sectional view showing a first step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view showing a second step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 4 is a cross-sectional view showing a third step in the method of manufacturing the semiconductor device shown in FIG.

5 is a cross-sectional view showing a fourth step in the method of manufacturing the semiconductor device shown in FIG.

6 is a cross-sectional view showing a fifth step in the method of manufacturing the semiconductor device shown in FIG.

7 is a cross-sectional view showing a sixth step in the method of manufacturing the semiconductor device shown in FIG.

8 is a cross-sectional view showing a seventh step in the method of manufacturing the semiconductor device shown in FIG.

9 is a cross-sectional view showing an eighth step in the method of manufacturing the semiconductor device shown in FIG.

10 is a cross-sectional view showing a ninth step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 11 is a sectional view showing a semiconductor device including a high voltage MOS transistor according to another embodiment of the invention.

12 is a cross-sectional view showing a first step in the method of manufacturing the semiconductor device shown in FIG.

13 is a cross-sectional view showing a second step in the method of manufacturing the semiconductor device shown in FIG.

14 is a cross-sectional view showing a third step in the method of manufacturing the semiconductor device shown in FIG.

15 is a cross-sectional view showing a fourth step in the method of manufacturing the semiconductor device shown in FIG.

16 is a cross-sectional view showing a fifth step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 17 is a cross-sectional view showing a sixth step in the method of manufacturing the semiconductor device shown in FIG. 11.

FIG. 18 is a cross-sectional view showing a seventh step in the method of manufacturing the semiconductor device shown in FIG. 11.

19 is a cross-sectional view showing an eighth step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 20 is a sectional view showing a semiconductor device including a high voltage MOS transistor according to still another embodiment of the present invention.

21 is a cross-sectional view showing a first step in the method for manufacturing the semiconductor device shown in FIG.

22 is a cross-sectional view showing a second step in the method of manufacturing the semiconductor device shown in FIG.

23 is a cross-sectional view showing a third step in the method of manufacturing the semiconductor device shown in FIG.

24 is a cross-sectional view showing a fourth step in the method of manufacturing the semiconductor device shown in FIG.

25 is a cross-sectional view showing a fifth step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 26 is a cross-sectional view showing a sixth step in the method of manufacturing the semiconductor device shown in FIG. 20.

27 is a sectional view showing a seventh step of the method for manufacturing the semiconductor device shown in FIG. 20. FIG.

28 is a cross-sectional view showing an eighth step in the method of manufacturing the semiconductor device shown in FIG.

29 is a cross-sectional view showing a ninth step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 30 is a sectional view showing a semiconductor device including a high voltage MOS transistor according to still another embodiment of the present invention.

31 is a cross-sectional view showing a first step in the method of manufacturing the semiconductor device shown in FIG. 30. FIG.

32 is a cross-sectional view showing a second step in the method of manufacturing the semiconductor device shown in FIG.

FIG. 33 is a cross-sectional view showing a third step in the method of manufacturing the semiconductor device shown in FIG. 30.

34 is a cross-sectional view showing a fourth step in the method of manufacturing the semiconductor device shown in FIG.

35 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device shown in FIG. 30. FIG.

36 is a cross-sectional view showing a sixth step in the method for manufacturing the semiconductor device shown in FIG. 20. FIG.

FIG. 37 is a cross-sectional view showing a seventh step in the method of manufacturing the semiconductor device shown in FIG. 30.

FIG. 38 is a sectional view showing the structure of a conventional MOS transistor.

FIG. 39 is an M in which a treatment for suppressing the expansion of the depletion layer has been performed.
FIG. 6 is a diagram showing a relationship between an absolute value of a source / drain breakdown voltage and a gate dimension in an OS transistor (condition A) and a MOS transistor (condition B) which is not subjected to a treatment for suppressing the spread of a depletion layer.

[Explanation of symbols]

1 High voltage MOS transistor formation region 2 Normal MOS transistor formation region 3, 3a, 4, 23, 24, 53, 83 Gate insulating film 5, 25, 55, 85 Gate electrode 6, 26, 56, 86 Drain diffusion region 7 , 27, 57, 87 Source diffusion region 9, 59 Recessed portion 10, 30, 60, 90, 110 Element isolation oxide film 12, 32, 62, 92, 112 p-type semiconductor substrate 13, 33, 63, 93, 113 p + iso Layers 21, 22, 23, 45, 46, 47, 48, 67, 6
8,69,70,71,97,98,99,100,1
01 Resist pattern 10a, 60a Thick oxide film 10b, 30b, 60b Underlay oxide film 34,94 Trench 65,95 First p-type well 66,96 Second p-type well

Claims (5)

[Claims] 1. A first-conductivity-type semiconductor substrate having a recess in a portion to be a channel region of a first transistor, and a channel region formed on a main surface of the semiconductor substrate at a position sandwiching the recess. A second conductive type source / drain region, a gate insulating film formed on the channel region including the recess, and a gate electrode formed on the gate insulating film. 2. The semiconductor device further comprises a second transistor formed on a flat main surface of the semiconductor substrate, wherein a thickness of a gate insulating film of the first transistor is equal to a gate insulating film of the second transistor. The semiconductor device according to claim 1, wherein the semiconductor device has a thickness greater than the thickness of. 3. A semiconductor substrate having a main surface, a first well that is a first conductivity type impurity diffusion region formed in the main surface of the semiconductor substrate, and a first well formed in the main surface of the semiconductor substrate. A second well which is a first conductivity type impurity diffusion region having an impurity concentration higher than that of one well; a first transistor formed on the first well; and a second transistor formed on the second well. A semiconductor device including: a channel region of the first well, wherein the first transistor has a recess in a portion that becomes a channel region, and the first transistor has a channel region on a main surface of the semiconductor substrate at a position sandwiching the recess. Second-conductivity-type source / drain regions formed so as to define, a gate insulating film formed on the channel region including the recess, and a gate formed on the gate insulating film. Wherein a; and a pole. 4. A step of forming a local oxide film extended into the substrate by selectively thermally oxidizing a desired element formation region on the main surface of a semiconductor substrate, and removing the local oxide film to form the local oxide film. Forming a recess in a desired element formation region; forming a gate electrode on the recess via a gate insulating film; and forming a source / drain region of a transistor on the main surface of the semiconductor substrate at a position sandwiching the recess. And a method of manufacturing a semiconductor device, comprising: 5. A step of forming a recess having a desired depth by etching in a desired element formation region on the main surface of a semiconductor substrate, and a gate electrode is formed on the recess via a gate insulating film. A method of manufacturing a semiconductor device, comprising: a step of forming a source / drain region of a transistor on a main surface of the semiconductor substrate at a position sandwiching the recess.