JPH04246862A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a MOS type transistor which hardly deteriorates in breakdown strength between a drain and a source in a non-punch through region even if a gate oxide film is formed thin. CONSTITUTION:A thin gate oxide film 11 is formed on a P-type silicon substrate 10, a gate electrode 12 is provided onto the gate oxide film 11, and the gate oxide film 11 is isotropically etched using a resist which is formed so as to expose only a part of the gate electrode 12 on a drain side as a mask, whereby the gate oxide film near the drain 13 is slightly etched and oxidized again, and in result a comparatively thick so-called gate bird's beak is formed near the drain 13, and a gate oxide film is selectively formed thick.

Description

[0001] The present invention relates to a semiconductor integrated circuit and a method for manufacturing a semiconductor integrated circuit, particularly to improving the performance of a MOS transistor. The present invention relates to a MOS transistor and a method for manufacturing the MOS transistor that prevents reduction in source-drain breakdown voltage in a through region. 2. Description of the Related Art The trend toward miniaturization of semiconductor integrated circuits is progressing without stopping, and along with the reduction in planar dimensions, the vertical dimensions are also being reduced. For example, if we take the gate oxide film as an example, a film thickness of about 500A was selected for a 3-micron rule device, but a film thickness of about 200A was selected for a 1-micron rule device after planar reduction. ing. This is in accordance with the so-called proportional reduction law, and the device parameters are optimized by determining the element dimensions of the device. but,
There are also negative effects associated with this, and an example of these is shown below. That is, FIG. 9 shows the correlation between the source-drain breakdown voltage (BVsd), which is one of the important parameters of a MOS transistor, and the gate dimensions, using the gate oxide film thickness as a parameter. here,
The determining factors of the source-drain breakdown voltage of a MOS transistor will be briefly explained. Determining factors for the source-drain breakdown voltage include punch-through and drain-substrate junction breakdown voltage. (1) Punch-through The gate dimension is a factor that determines the source-drain breakdown voltage in a short region. In a MOS transistor, when the drain voltage is increased (in the + direction in the case of an N-channel transistor), the PN junction between the drain and the substrate is biased in the opposite direction, so the depletion layer expands. , and finally reaches the source, and current flows between the source and drain even though no voltage is applied to the gate. This phenomenon naturally occurs significantly in transistors with short gate dimensions, and the minimum gate dimension that does not cause punch-through is the minimum usable gate dimension of a MOS transistor. Regarding this phenomenon, the thinner the gate oxide film is, the higher the withstand voltage is because the extension of the depletion layer along the interface between the gate oxide film and the silicon substrate is suppressed. (2) Drain/substrate junction breakdown voltage source/
This is a source-drain breakdown voltage factor in the non-punch-through region, which is a region where the drain-to-drain breakdown voltage does not depend on gate dimensions. The drain-substrate junction breakdown voltage is the reverse breakdown voltage of the PN junction between the drain and the substrate described above, but it is not determined simply by the difference in PN concentration. As mentioned in (1) above, if the gate oxide film is thin, the extension of the depletion layer along the interface between the gate oxide film and the silicon substrate can be suppressed. The potential gradient becomes steeper. Therefore, a high electric field is generated, and the reverse breakdown voltage of the PN junction between the drain and the substrate is determined at that portion. Therefore, when the gate oxide film is made thinner, the source-drain breakdown voltage in the non-punch-through region, where the source-drain breakdown voltage of the MOS transistor is determined by the drain-substrate junction breakdown voltage, becomes lower. For the reasons mentioned above, as the gate oxide film becomes thinner, the minimum usable gate size of a MOS transistor becomes shorter, meeting the trend toward miniaturization.
The absolute value of the drain-to-drain breakdown voltage becomes lower. Specifically, in the example of the correlation between source-drain breakdown voltage (BVsd) and gate dimensions shown in FIG.
By thinning A to 180A, 14V to 13
It has dropped to V. In other words, with the gate oxide film thickness of 180 A, even if a transistor with a large gate size is used, a source-drain breakdown voltage of 13 V or more cannot be obtained. [0007] The power supply voltage used in a typical MOS transistor is about 5 V, and the decrease in the source-drain breakdown voltage to the extent described here is not a problem at all. However, in devices such as EPROM and EEPROM that use a high voltage of 12 V or more during writing, a decrease in maximum source-drain breakdown voltage becomes a serious problem. [0008] As explained above, in conventional MOS transistors, as the gate oxide film becomes thinner, the breakdown voltage between the source and drain in the non-punch-through region becomes lower, and There is a problem that such MOS type transistors cannot be used in devices such as those in which a high voltage of 12 V or more is handled inside the circuit during writing. The present invention has been made to solve the above-mentioned problems, and is to obtain a MOS transistor in which the source-drain breakdown voltage in the non-punch-through region does not decrease even if the gate oxide film is thinned. The purpose of this invention is to provide a manufacturing method for the same. Means for Solving the Problems In order to achieve the above object, a semiconductor integrated circuit according to a first aspect of the present invention is provided with M
By selectively thickening the gate oxide film near the drain of an OS type transistor (making the gate bird's beak on the drain side thicker than the gate bird's beak on the source side), the potential gradient near the drain and gate due to drain voltage application can be reduced. is made looser to increase the breakdown voltage between the source and drain in the non-punch-through region. A method for manufacturing a semiconductor integrated circuit according to a second aspect of the present invention is a manufacturing method for manufacturing a semiconductor integrated circuit according to the first aspect of the invention, in which a thin gate oxide is formed on the surface of a semiconductor wafer. After forming a film and forming a gate electrode on the gate oxide film, the area near the drain is etched using the resist formed as a mask to expose only the drain side of the gate electrode. After slightly etching the gate oxide film, reoxidation is performed to selectively thicken the gate oxide film by forming a relatively thick so-called gate bird's beak only in the vicinity of the drain. Further, a method for manufacturing a semiconductor integrated circuit according to a third aspect of the present invention is a manufacturing method for manufacturing a semiconductor integrated circuit according to the first aspect of the invention, in which a thin gate oxide film is formed on the surface of a semiconductor wafer. After forming a gate electrode on the gate oxide film, a nitride film for preventing oxidation is formed on the entire surface, and then a resist formed to expose only the drain side of the gate electrode is used as a mask. After etching the nitride film, reoxidation is performed to selectively thicken the gate oxide film by forming a relatively thick so-called gate bird's beak only in the vicinity of the drain. [Operation] Therefore, according to the semiconductor integrated circuit and semiconductor integrated circuit manufacturing method of the present invention, gate oxidation is selectively performed by forming a relatively thick so-called gate bird's beak only in the vicinity of the drain of the MOS transistor. The film can be made thicker, and as a result, even if the gate oxide film is made thinner, the source-drain breakdown voltage in the non-punch-through region can be increased. [Embodiment] An embodiment of the present invention will be explained below with reference to the drawings. FIG. 1 is a cross-sectional view of a MOS transistor which is an embodiment of a semiconductor integrated circuit according to the first aspect of the present invention. In FIG. 1, the MOS transistor of the present invention includes a P-type silicon substrate (10), a gate oxide film (11), a gate electrode (12), a drain diffusion layer (13), and a source diffusion layer (14). , thermal oxide film (15), and thermal oxide film (
A thick gate bird's beak (16) on the drain side formed when forming the thermal oxide film (15) and a thin gate bird's beak (16) on the source side formed when forming the thermal oxide film (15).
17). As is clear from FIG. 1, in the MOS transistor according to the first aspect of the present invention, the gate bird's beak on the drain side is thick. By thickening the gate bird's beak on the drain side in this way, the potential gradient in the vicinity of the drain and gate due to the application of a drain voltage becomes gentler, and the reverse breakdown voltage of the PN junction between the drain and the substrate can be increased. In addition, since the thickness of the gate oxide film other than the area near the drain is made thinner, the above-mentioned merits of thinning the gate oxide film are taken advantage of, and the minimum usable gate size is thin, and MOS type transistors with high withstand voltage between the source and drain can be used. It becomes. In other words, the MOS transistor according to the first aspect of the present invention improves the reverse junction breakdown voltage between the drain and the substrate due to the thinning of the gate oxide film. It is possible to enjoy the benefits of improved breakdown voltage and improved breakdown voltage between the source and drain in the punch-through region due to the thinning of the gate oxide film. Next, a semiconductor integrated circuit manufacturing method according to the second invention, which is related to the method for manufacturing a MOS transistor according to the first invention, will be explained using FIGS. 2 to 6. 2 to 6 are MOSs according to the semiconductor integrated circuit manufacturing method of the second invention.
MOS at each step showing the generation process of type transistor
FIG. 2 is a cross-sectional view of a type transistor. In the process of producing the MOS transistor shown in FIG. 1, first, a gate oxide film (11) is formed by thermally oxidizing a P-type silicon substrate (10). A cross-sectional view of the MOS transistor in this state is shown in FIG. Next, a polysilicon gate electrode (12) with a film thickness of about 3000A is formed by CVD, and a resist (18) is formed into a desired shape by photolithography.
Using this as a mask, the polysilicon gate electrode (12) is etched using a plasma etching technique using CF4 plasma or the like. Next, resist pattern (18
) or polysilicon gate electrode (12) as a mask, the gate oxide film (11) is etched. A cross-sectional view of the MOS transistor in this state is shown in FIG. Next, after removing the resist pattern (18), using ion implantation technology, As ions are injected 4× at an acceleration voltage of about 40 KeV.
An N+ source diffusion layer (14) and an N+ drain diffusion layer (13) are formed by implanting approximately 1015 (cm-1). A cross-sectional view of the MOS transistor in this state is shown in FIG. Next, the gate oxide film on the drain side is slightly etched by isotropically etching the oxide film using the resist pattern (19) exposing only the drain portion as a mask using photolithography. It digs into the source direction by about 5 to 10% of the distance between the source and drain. A cross-sectional view of the MOS transistor in this state is shown in FIG. After that, the N+ source diffusion layer (14) and the N+ source diffusion layer (14)
+ In order to activate the As ion-implanted layer implanted to form the drain diffusion layer (13), heat treatment was performed in a nitrogen atmosphere at a temperature of about 900° C. for about 15 minutes, and then 90° C.
Reoxidation is performed by heat treatment at a temperature of about 0° C. in an oxygen atmosphere for about 40 minutes. Then, after oxidation, the polysilicon gate electrode (12) and P-type silicon substrate (10) will be exposed to the oxidizing atmosphere because the gate oxide film has slightly bit into the drain side. , a thick gate bird's beak (16) is formed. On the other hand, a thin gate bird's beak (17) is formed in the unexposed portion exposed to the oxidizing atmosphere. A cross-sectional view of the MOS transistor in this state is shown in FIG. As explained above, by the above-described manufacturing method, it is possible to realize a MOS type transistor in which the gate oxide film is formed thick only on the drain side as shown in FIG. 1. Next, a method for manufacturing a semiconductor integrated circuit according to a third invention of the present invention, which is related to a method for manufacturing a MOS transistor according to the first invention, will be explained using FIGS. 7 and 8. 7 and 8 are cross-sectional views of a MOS transistor at each step showing the process of producing a MOS transistor according to the semiconductor integrated circuit manufacturing method of the third invention. In the semiconductor integrated circuit manufacturing method of the third invention, the steps up to the steps shown in FIG. 4 are the same as those shown in the embodiment of the second invention. For the MOS transistor shown in FIG. 4, the N+ source diffusion layer (14) and the N+
After completing the As ion implantation to form the drain diffusion layer (13), an anti-oxidation nitride film (20) of about 20 nm is formed on the entire surface of the semiconductor wafer by low pressure CVD. Next, a resist pattern (19) exposing only the drain portion is formed by photolithography, and using this as a mask, the anti-oxidation nitride film (20) is etched by dry etching using CF4 plasma. A cross-sectional view of the MOS transistor in this state is shown in FIG. After that, the N+ source diffusion layer (14)
In order to activate the As ion-implanted layer implanted to form the N+ drain diffusion layer (13), heat treatment was performed at a temperature of about 900° C. for about 15 minutes in a nitrogen atmosphere.
Reoxidation is performed by heat treatment at a temperature of about 00° C. in an oxygen atmosphere for about 40 minutes. After oxidation, parts other than the drain part were covered with the anti-oxidation nitride film (20), so they were not oxidized, and only the gate oxide film in the vicinity of the drain was oxidized, forming a thick gate bird's beak (16). A cross-sectional view of the MOS transistor in this state is shown in FIG. In the above embodiment, only an N-channel transistor was explained, but it goes without saying that similar effects can be obtained even if the present invention is applied to a P-channel transistor. As explained above, according to the semiconductor integrated circuit according to the first aspect of the present invention, the gate oxide film in the vicinity of the drain of the MOS transistor is formed to be selectively thick. Therefore, the reverse breakdown voltage between the drain and the substrate can be increased by making the potential gradient generated between the drain and the gate due to drain voltage application gentle, without sacrificing the benefits of making the gate oxide film thinner. This has the effect of increasing the source-drain breakdown voltage of the non-punch-through region. Further, according to the method for manufacturing a semiconductor integrated circuit according to the second aspect of the present invention, after forming a thin gate oxide film on the surface of a semiconductor wafer and forming a gate electrode on the gate oxide film, , by performing isotropic oxide film etching using a resist formed to expose only the drain side of the gate electrode as a mask, the gate oxide film near the drain is slightly etched, and then reoxidation is performed. Since the gate oxide film is selectively thickened by forming a relatively thick so-called gate bird's beak only in the vicinity of the drain, the MO of the first invention
By adding a simple process to the structure of an S-type transistor,
This has the effect of being able to form with high precision. Furthermore, according to the method for manufacturing a semiconductor integrated circuit according to the third aspect of the present invention, after forming a thin gate oxide film on the surface of the semiconductor wafer and forming a gate electrode on the gate oxide film, After forming a nitride film on the entire surface to prevent oxidation, etching the nitride film using a resist mask that exposed only the drain side of the gate electrode, and then reoxidizing the area near the drain. Since the gate oxide film is selectively thickened by forming a relatively thick so-called gate bird's beak, the structure of the MOS transistor of the first invention can be formed with high precision by adding a simple process. The effect is that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a MOS transistor which is an embodiment of a semiconductor integrated circuit according to a first aspect of the present invention.

[Fig. 2] M according to the semiconductor integrated circuit manufacturing method of the second invention
FIG. 2 is a cross-sectional view of a MOS transistor showing the process of producing an OS transistor.

FIG. 3 is a cross-sectional view of a MOS transistor with a polysilicon gate electrode (12) and a gate oxide film (11) etched.

FIG. 4 is a cross-sectional view of a MOS transistor in which an N+ source diffusion layer (14) and an N+ drain diffusion layer (13) are formed.

FIG. 5 is a cross-sectional view of a MOS transistor in which a gate oxide film is formed so as to dig into the source direction.

FIG. 6 is a cross-sectional view of a MOS transistor in which a thick gate bird's beak (16) is formed after reoxidation by heat treatment.

[Fig. 7] M according to the semiconductor integrated circuit manufacturing method of the third invention
FIG. 2 is a cross-sectional view of a MOS transistor showing the process of producing an OS transistor.

FIG. 8 is a cross-sectional view of a MOS transistor in which a thick gate bird's beak (16) is formed after reoxidation by heat treatment.

FIG. 9 is a diagram illustrating the correlation between the source-drain breakdown voltage (BVsd) and gate dimensions of a MOS transistor using the gate oxide film thickness as a parameter.

[Explanation of symbols]

(10) P-type silicon substrate (11) Gate oxide film (12) Polysilicon gate electrode (13) Drain diffusion layer (14) Source diffusion layer (15) Thermal oxide film (16) Thick gate bird's beak (17) Thin gate Bird's beak (18), (19) Resist pattern (20)
Antioxidant nitride film

Claims (3)

[Claims] 1. A MOS type semiconductor integrated circuit, wherein a gate bird's beak near the drain is thicker than a gate bird's beak near the source. 2. A manufacturing method for manufacturing a semiconductor integrated circuit according to claim 1, comprising an oxide thin film generation step of generating a thin oxide film to become a gate oxide film on the surface of a semiconductor wafer by a thermal oxidation method or the like. , a gate electrode generation step in which an electrode material such as a polycrystalline silicon thin film, which will become a gate electrode, is produced on the oxide thin film, and the electrode material is dry-etched using a photoresist formed into a desired shape by photolithography as a mask. An etching process to etch;
a diffusion layer forming step of introducing an impurity of a conductivity type opposite to that of the semiconductor substrate by ion implantation or the like using the electrode material formed in a desired shape as a mask to form a source diffusion layer and a drain diffusion layer; and photolithography. By isotropically etching the oxide film using a photoresist as a mask, which has been formed using a technique such that only the drain diffusion layer is exposed, the drain side end of the gate oxide film is etched in the direction of the source by 50% of the length between the source and drain. It includes at least an adjustment step of cutting in the length by about 10%, and a heat treatment step of thickening the gate bird's beak at the drain side end by exposing the entire semiconductor wafer obtained by the above steps to a thermal oxidation atmosphere. A method for manufacturing a semiconductor integrated circuit, characterized by: 3. A manufacturing method for manufacturing a semiconductor integrated circuit according to claim 1, comprising an oxide thin film generation step of generating a thin oxide film to become a gate oxide film on the surface of a semiconductor wafer by a thermal oxidation method or the like. , a gate electrode generation step in which an electrode material such as a polycrystalline silicon thin film, which will become a gate electrode, is produced on the oxide thin film, and the electrode material is dry-etched using a photoresist formed into a desired shape by photolithography as a mask. An etching process to etch;
a diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer by introducing impurities of a conductivity type opposite to that of the semiconductor substrate by ion implantation or the like using the electrode material formed in a desired shape as a mask; An oxidation prevention film generation step in which a thin film such as a nitride film having an oxidation prevention effect is generated on the entire surface of the semiconductor wafer obtained by the process, and a photoresist formed by photolithography so that only the drain diffusion layer is exposed is masked. an oxidation-preventing thin film etching step for etching the thin film having an oxidation-preventing effect; and a heat treatment step for thickening the gate bird's beak at the drain side end by exposing the entire semiconductor wafer obtained through each of the above steps to a thermal oxidation atmosphere. A method for manufacturing a semiconductor integrated circuit, comprising at least the following.