JP2004158806A - Method for manufacturing insulated gate field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem, wherein in an extension impurity region which has been already formed, a surface part thereof is dug by unintentional etching in the middle of a process, to reduce the characteristics. <P>SOLUTION: A method for manufacturing insulated gate field-effect transistors includes steps of: forming a laminate of a gate insulating film 2 and a gate electrode 3 on a semiconductor 1 on which a channel is formed; covering at least a surface region of the semiconductor 1 with an oxide preventing film 4 for preventing the surface region of the semiconductor 1 exposed to the periphery of the gate electrode 3 from oxidizing; ion-implanting impurities on the surface region of the semiconductor 1 with the oxide preventive film 4 remaining thereon to form the extension impurity region (distributed region 3a) of a source or drain; and forming a source/drain impurity region in the semiconductor 1 separate from an edge of the gate electrode 3 by a predetermined distance. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing an insulated gate field effect transistor in which a source / drain impurity region includes a so-called extension impurity region.
[0002]
[Prior art]
An insulated gate field effect transistor represented by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely used as an active device of a semiconductor integrated circuit (IC). High integration of ICs is mainly supported by miniaturization of MOSFETs.
In a CMOS (complementary mental-oxide semiconductor) logic IC or the like, a P-type channel MOS (hereinafter, PMOS) and an N-type channel MOS are mixed. For transistors with different types and profiles of these impurities, in order to suppress a short channel effect accompanying miniaturization, a shallow junction ion implantation technique called an extension, and a channel depending on a gate length Lg. To control the impurity profile, an ion implantation technique called a pocket or a halo is known.
Of these, the extension impurity region requires a very shallow junction depth with the recent progress in miniaturization. In addition, the impurity concentration tends to be set higher than before to suppress source resistance and the like.
[0003]
On the other hand, a logic IC usually has a low withstand voltage logic transistor that operates at a power supply voltage Vdd, and a logic transistor that protects an internal circuit from a high voltage that may be applied from the outside to its input / output unit. A transistor with a higher breakdown voltage is used.
In order to improve the breakdown voltage without incurring the area penalty, the impurity concentration profile of the source or the drain is usually made different from that of the logic transistor. In such a case, it is necessary to repeatedly form extension impurity regions at different locations in the same wafer under different ion implantation conditions.
[0004]
FIGS. 4A to 4C show that a transistor (for example, an N-type logic transistor of a CMOS logic IC) in which an extension impurity region has been formed is inevitably formed in a process of forming an extension impurity region of another transistor. FIG. 2 is a cross-sectional view showing a typical process.
In FIG. 4A, a gate insulating film 101 is formed over a semiconductor in which a channel is formed, for example, a P well 100, and a gate electrode 102 is formed over the gate insulating film 101. N-type impurities are shallowly introduced into the well surface portions on both sides of the gate electrode 102 in the channel direction by ion implantation with relatively low acceleration energy. Reference numeral 103 in the drawing indicates the distribution region of this N-type impurity.
[0005]
Thereafter, another transistor in the same wafer as the N-type logic transistor shown in FIG. 4A in which the impurity distribution region 103 is formed, for example, a P-type logic transistor, an N-type or a P-type input / output transistor, A resist layer 104 is formed in order to perform ion implantation under conditions different from 103. In FIG. 4A, the N-type logic transistor that has been subjected to ion implantation first is covered with a resist layer 104.
[0006]
When ion implantation for forming an extension region is completed for another transistor (not shown), the used resist layer 104 is removed. In the peeling, as shown in FIG. 4B, the organic resist is burned in O ₂ plasma to be ashed and removed. Although not shown, a thin native oxide film is formed on the silicon surface of the well 100 at this time.
[0007]
In FIG. 4C, post-processing cleaning is performed. After that, the steps of FIGS. 4A to 4C are repeated as many times as necessary to form sidewall spacers and source / drain impurity regions. To complete the CMOS logic IC.
[0008]
[Problems to be solved by the invention]
However, in the conventional method of manufacturing a semiconductor device including an insulated gate field effect transistor, a cleaning solution containing hydrofluoric acid is used to remove organic substances in a post-processing step of FIG. For this reason, the natural oxide film is removed by etching, and as a result, the silicon surface after the removal of the natural oxide film is more or less dug than the state before the post-processing. Silicon having a high impurity concentration is easily oxidized, and in the present extension impurity region having a high concentration and a thin layer, a silicon surface layer of, for example, about 0.5 nm to 1.0 nm can be dug by a single resist stripping and post-processing cleaning. Will be.
[0009]
FIG. 5 is an enlarged cross-sectional view of the MOSFET after a plurality of, for example, four times of resist stripping and post-processing cleaning.
After the fourth post-processing cleaning, the digging amount Δd of the silicon surface is almost the same as the recent thin film thickness tox of the gate insulating film 101 or the projection range Rp of impurity ions in extension ion implantation (for example, 2 nm to 3 nm). ).
[0010]
FIG. 6A shows an impurity concentration profile in the depth direction of the substrate immediately after ion implantation when an N-type impurity is ion-implanted through a through oxide film (through oxide). FIG. 6B shows an impurity concentration profile when the silicon surface of this sample is dug by 0.5 nm and when the silicon surface is dug by 1.0 nm in comparison with a case where the silicon surface is not dug. The impurity concentration profile shown in FIG. 6B is a final impurity concentration profile after a CMOS process in which various heat treatments are performed.
As shown in FIG. 6B, it can be seen that the impurity concentration is reduced by 20% when the silicon surface is dug by 0.5 nm, and is reduced by 40% when the silicon surface is dug by 1.0 nm.
[0011]
FIG. 7 is a graph comparing Vg-Id characteristics of transistors having a dug amount of 0.5 nm and 1.0 nm with a transistor without dug amount. When the substrate is dug and the resistance of the extension region increases, the drain current Id when the same gate voltage Vg is applied decreases. This decrease in the drain current Id is as large as close to 40% as shown in FIG. At this time, the threshold voltage Vth has changed by 100 mV.
The reason why the transistor characteristics are changed is that the lateral expansion dimension of the impurity region becomes shorter due to the decrease in the amount of impurities due to the digging of the silicon surface, and the effective channel length becomes relatively longer. Further, the sheet resistance of the extension impurity region becomes extremely high, and the driving capability of the transistor decreases due to an increase in the parasitic resistance.
[0012]
An object of the present invention is to provide a method of manufacturing an insulated gate field-effect transistor that effectively prevents unintended etching during the process of an extension impurity region that has already been formed, and prevents deterioration in characteristics.
[0013]
[Means for Solving the Problems]
A method for manufacturing an insulated gate field effect transistor according to the present invention is intended to achieve the above object, and a step of forming a stacked body of a gate insulating film and a gate electrode on a semiconductor on which a channel is formed, A step of covering at least the surface area of the semiconductor with an oxidation-preventing film for preventing the surface area of the semiconductor exposed around the gate electrode from being oxidized; and Forming a source or drain extension impurity region by ion-implanting an impurity; and forming a source / drain impurity region in the semiconductor at a predetermined distance from an edge of the gate electrode.
[0014]
In this method of manufacturing an insulated gate field effect transistor, the surface of the semiconductor around the gate electrode is covered with an oxidation prevention film before performing ion implantation for forming the extension impurity region. Due to the presence of the oxidation prevention film, the surface portion of the extension impurity region having a high concentration and a high oxidation rate is not oxidized thereafter. Therefore, the surface portion of the extension impurity region is not consumed by oxidation. Even after going through various steps until the insulated gate field effect transistor is completed, even if the impurity concentration profile changes due to the diffusion of the impurity in the extension impurity region into the semiconductor, the impurity concentration profile greatly increases due to the surface region dug. No undesired change or unintended decrease in impurity concentration occurs.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a method of manufacturing an insulated gate field effect transistor (MISFET) according to the present invention will be described with reference to a logic transistor having a low withstand voltage and an input / output transistor having a relatively high withstand voltage. The following describes an example of a CMOS logic IC having a CMOS structure of a P-type and a P-type with reference to the drawings. Here, a cross section of the NMOS logic transistor will be described.
[0016]
FIGS. 1A to 3C are cross-sectional views of a semiconductor device (IC) according to an embodiment of the present invention in the process of manufacturing an NMOS logic transistor portion.
[0017]
In FIG. 1A, reference numeral 1 denotes a well formed on a semiconductor substrate such as a P-type silicon wafer, or a semiconductor supported on the substrate such as an SOI layer. In the present invention, a semiconductor in which a channel is formed refers to a semiconductor substrate, a well, an SOI layer, or the like. Hereinafter, a well will be described as an example of a semiconductor.
The NMOS logic transistor is formed in a dedicated P-type well 1. Other PMOS logics (not shown) are formed in dedicated N wells, and similarly, input / output transistors are formed in dedicated wells.
A part of the surface portion of the well 1 is insulated by a method such as a partial thermal oxidation method or a STI (Shallow Trench Isolation) method performed by masking a region where the transistor is formed, and the well 1 is not illustrated in a predetermined manner. An element isolation insulating layer having a pattern is formed.
[0018]
The gate insulating film 2 is formed on the surface of the well 1 where the element isolation insulating layer is not formed. The gate insulating film 2 is made of, for example, silicon oxide or silicon oxynitride formed by a thermal oxidation method.
Next, a gate electrode film made of, for example, polycrystalline silicon (doped polysilicon) or amorphous silicon (doped amorphous silicon), which is doped with impurities and has increased conductivity, is deposited on the gate insulating film 2. I do. The gate electrode film is deposited to a thickness of about 150 nm by, for example, a CVD (Chemical Vapor Deposition) method, and is doped with impurities during or after the ion implantation.
The gate electrode film and the gate insulating film are patterned to form a laminate of the gate electrode 3 and the gate insulating film 2.
[0019]
In this embodiment, an oxidation prevention film 4 that covers at least the surface of the semiconductor exposed around the gate electrode is formed. In FIG. 1B, an oxidation preventing film 4 is necessarily formed also on the surface of the gate electrode 3. The material of the oxidation prevention film 4 is preferably, for example, silicon nitride. As a method for forming the oxidation preventing film 4, a CVD method, a thermal nitriding treatment (for example, RTN (Rapid Thermal Nitridation)) or a thermal oxynitriding treatment can be adopted. The film thickness is set to a lower limit film thickness at which uniformity of the film thickness is sufficiently ensured at least over the entire wafer. In particular, in the case of CVD, since the film growth starts from nucleation in the first stage, it is necessary to perform CVD until the film thickness becomes uniform to some extent. Although there is no upper limit to the film thickness, it is desirable not to make the thickness too large in view of the uniformity of the ion implantation since the oxidation prevention film also functions as a through film for extension ion implantation. For the reasons described above, for example, the thickness of the oxidation prevention film 4 is set to 0. It is selected from the range of several nm to 3 nm.
[0020]
In FIG. 1C, a resist layer (not shown) that opens a formation region of the NMOS logic transistor is formed. Using the resist layer as a mask, N-type impurity ions are implanted to form extension impurity regions of the source / drain regions S / D. For example, arsenic ions As ⁺ as ion species are implanted at an acceleration energy of 2.5 keV, a dose of 1.0 × 10 ¹⁵ ions / cm ² , and an implantation angle of 0 °. At this time, the gate electrode 4 (and the element isolation insulating film) functions as a self-aligned mask, and the oxidation preventing film 4 is a protective film for preventing contamination of the surface of the well 1 or a through film for reducing defects introduced at the time of implantation. Functions as a membrane. As a result, N-type extension impurity distribution regions 5a are formed in the well surface portions on both sides of the gate electrode 3.
Thereafter, the resist layer is peeled off, and post-processing cleaning is performed. The resist stripping and post-processing cleaning will be described later.
[0021]
For other types of transistors (PMOS logic transistors, P-type and N-type input / output transistors), extension impurity regions shown in FIG. 1C are formed in individual steps. FIGS. 2A to 2C illustrate processing that is necessarily performed on the NMOS logic transistor during a series of steps for forming the extension impurity region.
[0022]
FIG. 2A shows a resist layer 6 formed as an ion implantation mask. The resist layer 6 is opened at another location, and the location where the NMOS logic transistor is to be formed is not an ion implantation target. Covered.
[0023]
FIG. 2B illustrates a resist stripping step. In the resist stripping step, ashing is performed by introducing oxygen gas into a plasma ashing apparatus. Normally, the wafer is exposed to oxygen plasma at this time, but the oxidation preventing film 4 does not oxidize the silicon on the well surface.
[0024]
In FIG. 2C, post-processing cleaning is performed. This is usually performed by RCA cleaning, but since it is an alkaline chemical solution for removing the resist, the oxide film surface is slightly etched.
The series of steps illustrated in FIGS. 2A to 2C is performed three times in this example on the extension impurity distribution region 5a of the NMOS logic transistor that has already been formed.
[0025]
After that, for example, a silicon oxide film is CVD-processed, and the entire surface is anisotropically etched (etched back). As a result, as shown in FIG. 3A, sidewall spacers 7 are formed on the side surfaces of the gate electrode 3, respectively.
[0026]
In FIG. 3B, ion implantation for forming source / drain regions is performed. This ion implantation is also selectively performed for each type of transistor. That is, similarly to FIG. 2A, an opening resist layer is formed at a transistor portion to be ion-implanted, ions are implanted under conditions suitable for each transistor, and then, as shown in FIGS. 2B and 2C. Similarly, the resist layer is peeled off, and post-processing cleaning is performed.
As an example of ion implantation conditions, in ion implantation for an NMOS logic transistor, for example, arsenic ions As ⁺ as an ion species are introduced at an acceleration energy of 40 keV, a dose of 2.0 × 10 ¹⁵ ions / cm ² , and an implantation angle of 0 °. Ions are implanted. At this time, the sidewall spacer 7 and the gate electrode 3 (and the element isolation insulating film) function as a self-alignment mask, and the oxidation prevention film 4 is a protective film for preventing contamination of the well surface, or a defect introduced at the time of implantation. Function as a through film to reduce As a result, an N-type source / drain impurity distribution region 8a is formed at a position in the well defined by the outer edge of the sidewall spacer 7 with respect to the center of the channel.
[0027]
After that, heat treatment (annealing) for activating the implanted impurities is performed. RTA (Rapid Thermal Annealing) can be used for annealing. At this time, RTA is performed on the substrate held at, for example, about 1000 ° C. in a nitrogen N ₂ atmosphere for about 10 seconds. As a result, the impurity is diffused, and as shown in FIG. 3C, the source / drain region S including the source / drain impurity region 8 and the extension impurity region 5 extending from the source / drain impurity region 8 toward the center of the channel. / D is formed.
[0028]
Thereafter, if necessary, the deposition of the interlayer insulating film, the formation of the contacts, and the formation of the wiring are repeated as many times as necessary to complete the CMOS logic IC.
[0029]
In the manufacturing method according to the present embodiment, the surface of the semiconductor is protected by the oxidation preventing film 4 before the ion implantation for forming the extension impurity region having a high concentration and a small thickness. Therefore, at the time of removing the resist used as a mask for ion implantation, oxidation of the semiconductor by oxygen plasma is effectively prevented. Also, the semiconductor surface is not exposed during the post-processing cleaning, so that it is not attacked by the cleaning liquid. If the thickness of the oxidation prevention film 4 is made sufficiently thin within a uniform range, there is almost no effect on ion implantation.
As described above, unintentional excavation of the extension impurity region can be effectively prevented. As a result, it is possible to prevent a reduction in resistance due to a reduction in impurity concentration, a reduction in current driving capability, a change in threshold voltage, a reduction in operation speed, and a circuit malfunction due to these.
[0030]
In the present embodiment, since the oxidation prevention film 4 is inevitably formed on the side surface of the gate electrode 3, it also functions as a sidewall spacer at the time of ion implantation. That is, at the time of the ion implantation of FIG. 1C, the edge of the extension impurity distribution region 5a is located outside the gate electrode by a distance corresponding to the thickness of the oxidation prevention film 4. Accordingly, after the impurities in the extension impurity distribution region 5a are diffused by the heat treatment, the overlapping area between the extension impurity region and the gate electrode can be reduced. This is advantageous in meeting the demand for a high-speed transistor that wants to reduce the parasitic capacitance between the gate and the source or the drain.
[0031]
【The invention's effect】
According to the method of manufacturing an insulated gate field effect transistor according to the present invention, unintended etching (digging) during the process of the extension impurity region already formed can be effectively prevented.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views of a portion of an NMOS logic transistor showing up to an ion implantation step for forming an extension impurity region in a semiconductor device (IC) according to an embodiment of the present invention; is there.
2 (A) to 2 (C) are cross-sectional views of an NMOS logic transistor portion, up to a post-treatment cleaning step of resist removal in another type of transistor following FIG. 1 (C).
3 (A) to 3 (C) are cross-sectional views of an NMOS logic transistor portion up to a step of forming source / drain regions subsequent to FIG. 2 (C).
FIGS. 4A to 4C are cross-sectional views showing a series of steps necessary for ion implantation using a resist layer as a mask, which are used for explaining the problems of the prior art.
FIG. 5 is an enlarged cross-sectional view of the MOSFET after a plurality of, for example, four times of resist stripping and post-processing cleaning.
FIG. 6 is a graph showing a concentration profile of an N-type impurity in a depth direction of a silicon substrate. (A) shows a profile immediately after ion implantation. (B) shows impurity concentration profiles when the silicon surface is dug by 0.5 nm and when the silicon surface is dug by 1.0 nm, as compared with the case where the silicon surface is not dug.
FIG. 7 is a graph showing Vg-Id characteristics of transistors having a dug amount of 0.5 nm and 1.0 nm compared with transistors without dug.
FIG. 8 is a graph showing a relationship between a dug amount, a threshold voltage, and a drain current.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor in which a channel is formed, 2 ... Gate insulating film, 3 ... Gate electrode, 4 ... Oxidation prevention film, 5a ... Extension impurity distribution region, 5 ... Extension impurity region, 6 ... Resist layer, 7 ... Third wall spacer , 8a: source / drain impurity distribution region, 8: source / drain impurity region

Claims (4)

Forming a stacked body of a gate insulating film and a gate electrode over a semiconductor on which a channel is formed;
A step of covering at least the surface region of the semiconductor with an oxidation prevention film that prevents the surface region of the semiconductor exposed around the gate electrode from being oxidized;
A step of ion-implanting impurities into the surface region of the semiconductor with the oxidation blocking film attached, forming a source or drain extension impurity region;
Forming a source / drain impurity region in the semiconductor separated by a predetermined distance from an edge of the gate electrode;
A method for manufacturing an insulated gate field effect transistor, comprising: The oxidation preventing film is a nitride film,
2. The method according to claim 1, wherein, in the step of forming the oxidation prevention film, the nitride film is formed to have a thickness not less than a minimum necessary for stabilizing the film thickness over the entire substrate on which the insulated gate field effect transistor is formed. 3. A method for manufacturing the insulated gate field effect transistor according to the above. In the case where the surface layer of the semiconductor is consumed in the heat treatment process as a part of the material of the oxidation prevention film in the step of forming the oxidation prevention film, the material and thickness of the oxidation prevention film are formed in the next formation of the extension impurity region. 2. The method of manufacturing an insulated gate field effect transistor according to claim 1, wherein a projection range of the ion implantation is determined in advance in consideration of the thickness of the surface layer of the semiconductor to be consumed. Forming the extension impurity region,
Forming a resist layer;
A step of selectively implanting impurity ions into semiconductor portions according to the pattern of the resist layer,
Removing the resist layer,
Cleaning the surface of the semiconductor,
2. The method according to claim 1, wherein when forming a plurality of types of insulated gate field effect transistors having different impurity profiles on the same substrate, the step of forming the extension impurity region is continuously performed a plurality of times by the number of the types of the transistors. A method for manufacturing the insulated gate field effect transistor according to the above.

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