JP2009277816A - Semiconductor device and method for manufacturing thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing thereof, which is equipped with a protective insulating film which is little in substrate oxidation, and does not cause the drive power reduction of a PMOS. <P>SOLUTION: A CMOS includes an NMISFET having a first protective insulating film 5 covering the surface of an N-type source-drain region and the periphery of a first gate electrode, and a PMISFET having a second protective insulating film 6 covering a P-type source-drain region 8 formed in both sides of a second gate electrode and the periphery of the second gate electrode, wherein the first protective insulating film 5 consists of one layer or more, the one layer is a silicon nitride film or an silicon oxynitride film, a portion contacting a semiconductor substrate among the second protective insulating film 6 is an silicon oxide film, and wherein the distance from the silicon substrate under the second protective insulating film 6 to the silicon nitride film or the silicon oxynitride film is longer than the distance from the silicon substrate under the first protective insulating film 5 to the silicon nitride film or the silicon oxynitride film. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device effective for a MISFET having a shallow source / drain junction and a manufacturing method thereof.

  Semiconductor devices are being miniaturized in accordance with scaling rules. Miniaturization of semiconductor devices is being promoted in transistors by reducing the gate electrode length, reducing the thickness of the gate insulating film, and reducing the extension region shallowly. As a result, miniaturization of transistors has progressed, and higher integration and higher drive of semiconductor devices have been promoted.

  Conventionally, with the miniaturization of transistors, the formation of source / drain regions has been realized by forming a steep impurity profile by reducing the energy of ion implantation. FIG. 9A is a cross-sectional view of the CMOS transistor after forming the gate oxide film and the gate electrode. After processing the gate electrode, an offset spacer made of a silicon oxide film or a silicon nitride film is formed as necessary. Thereafter, as shown in FIG. 9B, the surface of the PMOS region is covered with a resist material 11, and Halo implantation and source / drain region implantation are performed to form NMOS and PMOS source / drain regions 7 and 8.

  Here, in order to remove the resist used at the time of ion implantation, for example, a chemical solution using SPM (sulfuric acid hydrogen peroxide), APM (ammonia hydrogen peroxide) or DHF (dilute hydrofluoric acid), ashing using oxygen plasma, or a combination thereof. Do by. These treatments etch the silicon substrate surface at least. For example, APM has a function of directly etching a silicon surface. Alternatively, a silicon oxide film (chemical oxide film) having a low film density formed by SPM or ashing is easily etched by DHF. As a result of this repetition, the silicon surface is etched, as shown in FIG.

  Thereafter, as shown in FIG. 9D, the surface of the NMOS region is covered with a resist material 12, and Halo implantation and source / drain region implantation are performed to form a PMOS source / drain region 8. Then, as a result of peeling the resist, FIG. 9E is obtained. Thereafter, the side wall spacer 9 and the deep diffusion layer are formed, so that FIG. 9F is obtained.

  The etching of the surface of the source / drain region in this manner deteriorates the relationship between the junction depth (xj) of the source / drain region and the parasitic resistance. In particular, this effect becomes more prominent when transistors are miniaturized. For example, a transistor with a gate length of 30 nm requires xj to be 5 nm, but if the silicon surface is etched by 2 nm, the parasitic resistance will increase by 67%.

  In order to solve the above problem, in Patent Documents 1 and 2, a silicon nitride film is formed on the transistor surface after processing the gate electrode in order to prevent oxidation of the source / drain region that occurs in the semiconductor manufacturing process, and the semiconductor manufacturing process A method for preventing the etching of the extension region that occurs in the above is disclosed.

  However, the semiconductor devices disclosed in Patent Documents 1 and 2 have several problems. According to the authors' experiment, since silicon nitride inhibits the activation of boron in the vicinity of the silicon surface in contact, the source / drain region of the PMOS where Xj is short becomes extremely high resistance, leading to a decrease in the driving force of the PMOS. I found out. FIG. 1 shows a potential distribution of PMOS when silicon nitride is brought into contact with a silicon substrate. The + side is P-type and the-side is N-type. According to this, in the vicinity of the surface of the source / drain region, the potential of the portion to be P-type (the circled portion in FIG. 1) is lowered by the implanted boron.

Although this phenomenon can be prevented by using a silicon oxide film as the antioxidant film, the silicon oxide film cannot prevent the oxidation of the substrate in the n-type region. According to Non-Patent Document 1, a phosphorus-doped oxide film, which is a typical n-type impurity, has a much higher etching rate and weak protection resistance than a boron-doped oxide film, which is a typical p-type impurity. When phosphorus is implanted into the source / drain regions of the NMOS, phosphorus is physically mixed into the surface protective film, and therefore, if the protective film is a silicon oxide film, there is a concern that all will be etched later.
JP 2004-158806 A JP 2004-014875 A Journal of the Korean Physical Society, Vol. 33, No. , November 1998, pp. S99-S103 (FIG. 5)

  SUMMARY OF THE INVENTION Accordingly, it is a main object of the present invention to provide a semiconductor device including a protective insulating film and a method for manufacturing the semiconductor device, in which the substrate oxidation is small and the driving force of the PMOS does not decrease.

(Characteristics of the invention)
The semiconductor device of the present invention includes a semiconductor substrate, a first gate insulating film formed on the substrate, a first gate electrode formed on the first gate insulating film, and the first gate electrode. NMISFET having N-type source / drain regions formed in the semiconductor substrate on both sides of the semiconductor substrate, and a first protective insulating film covering at least the periphery of the first gate electrode on the surface of the N-type source / drain region A second gate insulating film formed on the substrate, a second gate electrode formed on the second gate insulating film, and in the semiconductor substrate on both sides of the second gate electrode. A PMISFET having a P-type source / drain region formed and a second protective insulating film covering at least the periphery of the second gate electrode on the surface of the P-type source / drain region, Protection The film is composed of one or more layers, at least one layer is an insulating film that is a silicon nitride film or a silicon oxynitride film, and a portion of the second protective insulating film that is in contact with the semiconductor substrate is a silicon oxide film, The distance from the silicon substrate under the second protective insulating film to the silicon nitride film or silicon oxynitride film is longer than the distance from the silicon substrate under one protective insulating film to the silicon nitride film or silicon oxynitride film It is characterized by that.

  In addition, the N-type source / drain region is formed outside the sidewall of the gate electrode, and the N-type deep source / drain region is shallower than the deep source / drain region. It consists of an N-type source / drain extension region extending toward the channel region below the electrode.

  The first protective insulating film covers at least the surface of the N-type source / drain extension region.

  In addition, the P-type source / drain region is formed outside the sidewall of the gate electrode, and the P-type deep source / drain region is shallower than the deep source / drain region. It consists of a P-type source / drain extension region extending toward the channel region below the electrode.

  The second protective insulating film covers at least the surface of the P-type source / drain extension region.

  Preferably, the first protective insulating film and the second protective insulating film have a thickness of 0.5 nm to 3 nm.

  According to a method of manufacturing a semiconductor device of the present invention, a first insulating film in which a portion in contact with a semiconductor substrate is a silicon oxide film is formed on the semiconductor substrate on which the first and second gate insulating films and the gate electrode are formed. After the step of depositing and depositing the first insulating film, the region including the p-type source / drain region is covered with a mask such as a resist, and the first insulating film in the region including the n-type source / drain region is covered. After the step of removing and the step of removing the first insulating film, the portion in contact with the semiconductor substrate is composed of one or more layers, and at least one layer is a silicon nitride film or a silicon oxynitride film. A step of depositing and covering a region including the n-type gate electrode / source / drain region with a mask such as a resist, and doping with p-type impurities including molecules of boron or a plurality of boron is performed. A step of forming a p-type source / drain region in the semiconductor substrate, and after depositing the second insulating film, a region including the p-type gate electrode / source / drain region is covered with a mask such as a resist; and a step of forming an n-type source / drain region in the semiconductor substrate by doping with an n-type impurity.

  In addition, an impurity containing fluorine is formed on the semiconductor substrate in which the first and second gate insulating films and the gate electrode are formed and the region including the n-type gate electrode / source / drain region is covered with a mask such as a resist. A step of implanting and stripping the resist, a step of forming a silicon oxide film, a step of depositing a silicon nitride film or performing a nitrogen atmosphere treatment, and a p-type gate electrode / source / drain region thereafter. A region including an n-type gate electrode / source / drain region, and a step of forming an n-type source / drain region in the semiconductor substrate by covering the region including the resist with a mask such as a resist and doping an n-type impurity. Is covered with a mask such as a resist, and doped with a p-type impurity containing a molecule of boron or a plurality of boron, and a p-type impurity is formed in the semiconductor substrate. Forming a over scan and drain regions can also be obtained by the method for manufacturing a semiconductor device, which comprises a.

  In addition, an impurity containing nitrogen is formed on the semiconductor substrate in which the first and second gate insulating films and the gate electrode are formed and the region including the p-type gate electrode / source / drain region is covered with a mask such as a resist. Implanting and stripping the resist, then forming a silicon oxide film, and then covering the region including the p-type gate electrode / source / drain region with a mask such as a resist, and doping with n-type impurities And forming an n-type source / drain region in the semiconductor substrate, covering the region including the n-type gate electrode / source / drain region with a mask such as a resist, and forming a molecule composed of boron or a plurality of boron. And a step of forming a p-type source / drain region in the semiconductor substrate. It can also be obtained by the manufacturing method of the device.

(Function)
When the protective insulating film of the nMOS is composed of one or more layers, and at least one layer is a silicon nitride film or a silicon oxynitride film, etching resistance can be improved and oxidation of the diffusion layer in the nMOS region can be suppressed.

  In addition, by making the pMOS protective insulating film in contact with the semiconductor substrate a silicon oxide film, it is possible to suppress inactivation of boron, which is a P-type impurity, which occurs when the pMOS protective insulating film is in contact with the silicon nitride film. it can.

  According to the present invention, boron used for forming the source / drain of the PMOS is not deactivated, and the source / drain impurity implantation region can suppress etching during the manufacturing process while maintaining the driving power of the PMOS. As a result, an increase in resistance in the diffusion layer region can be suppressed, and as a result, a highly driven transistor can be provided.

(Construction)
Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 2 is a sectional view of the semiconductor device according to the first embodiment of the present invention.

  A protective insulating film 5 is formed on part of the N-type source / drain region 7. This protective insulating film 5 is a silicon nitride film. A protective insulating film 6 is formed on part of the P-type source / drain region 8 formed by implanting an impurity containing boron. This protective insulating film 6 consists of two layers, and the layer in contact with the semiconductor substrate is a silicon oxide film. Accordingly, the etching resistance of the protective insulating film of the nMOS is high, and oxidation of the diffusion layer in the nMOS region can be suppressed.

  In addition, inactivation of boron, which is a P-type impurity, can be suppressed. The protective insulating film 5 may have a two-layer structure in which a silicon oxide film is formed on a silicon nitride film, and the protective insulating film 6 may have a silicon oxide film single-layer structure.

  The protective insulating film 5 has a two-layer structure in which a silicon nitride film is formed on a silicon oxide film, and the protective insulating film 6 also has a two-layer structure in which a silicon nitride film is formed on a silicon oxide film. The distance from the silicon nitride film in the protective insulating film 6 to the silicon substrate 1 may be longer than the distance from the silicon nitride film in the protective insulating film 5 to the silicon substrate 1.

  Further, the protective insulating films 5 and 6 do not have a layer structure, and may be in a state where the nitrogen concentration gradually changes.

  Further, the silicon nitride film of the protective insulating films 5 and 6 may be a silicon oxynitride film.

  FIG. 3 is a sectional view of a semiconductor device according to the second embodiment of the present invention.

  The N-type source / drain region 7 and the P-type source / drain region 8 are an N-type deep source / drain region formed outside the side wall 10 of the gate electrode 4 and a shallower and deeper source than the deep source / drain region. An N-type source / drain extension region extending from the drain region toward the channel region below the gate electrode 4. A protective insulating film 5 is formed on the source / drain extension region of the N-type source / drain region 7. This protective insulating film 5 is a silicon nitride film.

  A protective insulating film 6 is formed on the source / drain extension region of the P-type source / drain region 8 formed by implanting an impurity containing boron. This protective insulating film 6 consists of two layers, and the layer in contact with the semiconductor substrate is a silicon oxide film. Accordingly, the etching resistance of the protective insulating film of the nMOS is high, and oxidation of the diffusion layer in the nMOS region can be suppressed. In addition, inactivation of boron, which is a P-type impurity, can be suppressed.

(Manufacturing method)
FIG. 4 shows a semiconductor device and a method for manufacturing the semiconductor device according to the first embodiment of the present invention. First, as shown in FIG. 4A, after forming the element isolation oxide film 2 on the semiconductor substrate 1, Nwell and Pwell are formed. Thereafter, after a 1.2 nm silicon oxynitride film is formed as the gate insulating film 3, a polysilicon film is formed to 100 nm, and patterning is performed by a photolithography technique to form the gate electrode 4.

  Next, as shown in FIG. 4B, a silicon thermal oxide film 6 having a thickness of 2 nm is formed as a protective oxide film for preventing oxidation. The thickness of the protective oxide film is in the range of 0.5 nm to 3 nm.

  Here, the reason will be described with reference to FIG. The solid line in the figure shows the relationship between the parasitic resistance and the junction depth in an ideal state when the source / drain surface is not etched. On the other hand, the dotted line shows the relationship when the surface of the source / drain is etched by 1.5 nm. It can be seen that when the substrate surface is etched, the effect of increasing the parasitic resistance becomes significant when the junction depth is approximately 15 nm or less.

  On the other hand, specifications of parasitic resistance and junction depth required for MOSFETs are disclosed in ITRS (International Technology Roadmap for Semiconductors). The window (margin) of specifications required for MOSFETs in recent years is extremely strict, and the desired performance cannot be satisfied unless these requirements are satisfied. In FIG. 5, the specifications of the 32 nm node generation shown in ITRS 2005 are entered with diagonal lines. According to this, it is understood that the etching of the surface of the source / drain must be suppressed to 1.5 nm or less in order to satisfy this requirement.

  On the other hand, when a silicon oxide film is formed by thermal oxidation, a silicon surface having a film thickness half that of the oxide film is consumed. That is, thermal oxidation itself has the same effect as etching. Therefore, it is necessary to suppress the thermal oxide film thickness to 1.5 nm × 2 = 3.0 nm or less. However, if it is too thin, the surface protection effect is reduced. Even in the case of a thermal oxide film, when it is 0.5 nm or less, it is immediately removed even by a short DHF treatment. There is also a problem that it is difficult to control the thickness of the thermal oxide film of 0.5 nm or less.

  The reason why the thermal oxide film is used is that since the resistance to WET etching is high, even if the protective insulating film is thin, the protective insulating film can be prevented from being lost during the manufacturing process. FIG. 6 shows the etching rate of the silicon oxide film formed by each method to various chemical solutions. According to this, compared with a silicon oxide film formed by CVD, a silicon oxide film formed by thermal oxidation has the slowest etching rate and is most suitable as a substrate protective film. Plasma oxidation may be used as a method for obtaining a silicon oxide film close to a thermal oxide film.

  Next, the PMOS region of the formed protective oxide film is covered with a resist 10 as shown in FIG. 4C, and the protective oxide film in the NMOS region is removed by etching. Thereafter, processing is performed in a nitrogen plasma atmosphere to form a silicon oxynitride film 5 as shown in FIG. Thereby, a silicon nitride film is formed in the NMOS region, and the WET etching resistance of the protective insulating film in the PMOS region is also improved. As a result, the protective insulating film in the PMOS region has a low nitrogen concentration on the silicon substrate side and a high nitrogen concentration on the surface side. As described above, even when the protective insulating film in the PMOS region contains nitrogen, the inactivation of boron in the pMOS region can be suppressed by keeping the nitrogen-containing region away from the silicon substrate.

  Next, as shown in FIG. 4E, a resist mask 11 is formed in the PMOS region, and source / drain implantation with Halo and n-type impurities is performed in the NMOS region to form an n-type source / drain region 7. . Next, the resist mask 11 is removed by sulfuric acid / hydrogen peroxide cleaning. Further, as a resist removal method, it is possible to use both ashing treatment in a plasma oxidizing atmosphere and sulfuric acid / hydrogen peroxide cleaning. Since the surface of the protective insulating film is modified to a silicon oxynitride film, or because it is a silicon nitride film, the progress of substrate oxidation due to the ashing process is suppressed, and since a thermal oxide film is used, sulfuric acid-hydrogen peroxide Reduction in film thickness due to cleaning can be suppressed, and there is no need to feed back to ion implantation conditions. Next, as shown in FIG. 4 (f), a resist mask 12 is formed in the NMOS region, and source / drain implantation is performed in the PMOS region by Halo and boron ions to form the p-type source / drain region 8 in the same manner. . Thereafter, the resist mask is removed.

  Next, a 20 nm silicon oxide film is formed. Then, dry etching (RIE: Reactive Ion Etching) is performed to form sidewall spacers 9.

  Thereafter, a part of the protective insulating film is removed, and source / drain electrodes are formed by a known method.

(Another embodiment of the invention)
In the above embodiment, the gate insulating film 3 includes a single layer of a high dielectric constant insulating film having a relative dielectric constant of 5 or more, a silicon oxide film / a high dielectric constant insulating film stack having a relative dielectric constant of 5 or more, a silicon oxynitride film / a dielectric constant. A high dielectric constant insulating film stack having a rate of 5 or more can be substituted. The film thickness of the gate insulating film 3 is desirably 0.5 nm or more and 10 nm or less.

  As the gate electrode 4, a metal electrode containing one or more metals made of Ni, Co-containing electrodes, W, Ta, Ru, Mo, and Ti can be substituted. In addition, a temporary gate electrode to be removed later is included. The gate electrode film thickness is desirably in the range of 20 nm to 200 nm.

  For the formation of the silicon oxide film 6, an HDP film, an LPCVD film, or the like may be used. Since the wet etching resistance is enhanced by nitriding, the protective effect of the substrate is obtained although it is inferior to the thermal oxide film.

  The silicon nitride film 5 may be formed by CVD (Chemical Vapor Deposition), sputtering, or ALD (Atomic Layer Deposition) instead of nitrogen plasma atmosphere treatment.

  A silicon nitride film can be used for forming the sidewall spacer 9 instead of the 20 nm silicon oxide film. Further, the film structure includes the silicon oxide film single layer, the silicon nitride film single layer, the silicon oxide film / silicon nitride film stack, the silicon nitride film stack / silicon oxide film, and the silicon oxide film / silicon nitride film / silicon oxide film. A laminated structure can be substituted. The film thickness is preferably 5 nm or more and 80 nm or less in the case of a single layer. The total film thickness range is preferably 5 nm to 80 nm.

  Alternatively, the sidewall spacer 9 may be removed after the source / drain implantation, and the sidewall spacer may be attached again.

  Further, after the sidewall spacer 9 is formed, a resist mask is formed again in the PMOS region, and source / drain implantation with n-type impurities is performed in the NMOS region, so that the n-type source / drain region deeper than the already formed source / drain regions is formed. A drain region may be formed. Similarly, a resist mask is formed in the NMOS region, source / drain implantation with p-type impurities is performed in the PMOS region, and p-type source / drain regions deeper than the already formed source / drain regions are similarly formed. May be.

  In forming the p-type source / drain region 8, another p-type impurity may be implanted together with boron. Further, cluster ions or carboranes composed of a plurality of boron may be implanted.

  FIG. 7 shows a semiconductor device and a method for manufacturing the semiconductor device according to the second embodiment of the present invention.

  First, as shown in FIG. 7A, after forming the element isolation oxide film 2 on the semiconductor substrate 1, Nwell and Pwell are formed. Thereafter, after a 1.2 nm silicon oxynitride film is formed as the gate insulating film 3, a polysilicon film is formed to 100 nm, and patterning is performed by a photolithography technique to form the gate electrode 4. The gate insulating film 3 is a single layer of a high dielectric constant insulating film having a relative dielectric constant of 5 or higher, a silicon oxide film / a high dielectric constant insulating film stack having a relative dielectric constant of 5 or higher, or a silicon oxynitride film / a high dielectric constant having a relative dielectric constant of 5 or higher. It is possible to substitute a rate insulating film stack. The film thickness of the gate insulating film 3 is not less than 0.5 nm and not more than 10 nm. As the gate electrode 4, a Ni-containing electrode, or a metal electrode containing one or more metals made of W, Ta, Ru, Mo, Ti can be substituted. The thickness of the gate electrode ranges from 20 nm to 200 nm.

  Next, as shown in FIG. 7B, the PWell portion is covered with a resist mask 13, and fluorine is implanted into the NWell portion. Thereafter, the resist mask 14 is removed, and a silicon thermal oxide film 6 is formed as a protective insulating film as shown in FIG. At this time, due to the effect of fluorine implanted earlier, the silicon oxide film 15 in the PMOS region becomes thicker than the NMOS region. Note that the timing of fluorine implantation may be any time before the protective insulating film is formed. The thickness of the protective insulating film is in the range of 0.5 nm to 3 nm.

  Here, in order to further improve the WET etching resistance of the protective insulating films 6 and 14, the surface silicon oxide film modification treatment is performed. As shown in FIG. 7D, the surface of the silicon thermal oxide film 6 that is a protective insulating film is treated in a nitrogen plasma atmosphere to form a silicon nitride film 5. Instead of the nitrogen plasma atmosphere treatment, a silicon nitride film may be formed by a CVD (Chemical Vapor Deposition) method, a sputtering method, or an ALD (Atomic Layer Deposition) method. As a result, the protective insulating film has a low nitrogen concentration on the silicon substrate side and a high nitrogen concentration on the surface side. Since the thickness of the silicon oxide film before forming the silicon nitride film is large in the PMOS region, the nitrogen concentration on the silicon substrate side is lower in the PMOS region.

  After that, the process after 1st Embodiment FIG.4 (e) is implemented.

  As described above, even when the protective insulating film in the PMOS region contains nitrogen, the inactivation of boron in the pMOS region can be suppressed while increasing the etching resistance of the nMOS region by keeping the nitrogen-containing region away from the silicon substrate. it can.

  FIG. 8 shows a semiconductor device and a method for manufacturing the semiconductor device according to the third embodiment of the present invention.

  First, as shown in FIG. 8A, after forming the element isolation oxide film 2 on the semiconductor substrate 1, NWell and PWell are formed. Thereafter, after a 1.2 nm silicon oxynitride film is formed as the gate insulating film 3, a polysilicon film is formed to 100 nm, and patterning is performed by a photolithography technique to form the gate electrode 4. The gate insulating film 3 is a single layer of a high dielectric constant insulating film having a relative dielectric constant of 5 or higher, a silicon oxide film / a high dielectric constant insulating film stack having a relative dielectric constant of 5 or higher, or a silicon oxynitride film / a high dielectric constant having a relative dielectric constant of 5 or higher. It is possible to substitute a rate insulating film stack. The film thickness of the gate insulating film 3 is not less than 0.5 nm and not more than 10 nm. As the gate electrode 4, a Ni-containing electrode, or a metal electrode containing one or more metals made of W, Ta, Ru, Mo, Ti can be substituted. The thickness of the gate electrode ranges from 20 nm to 200 nm.

  Next, as shown in FIG. 8B, nitrogen is implanted into the PWell portion where the NWell portion is more than the resist mask 14. Thereafter, the resist mask 13 is removed, and a silicon thermal oxide film 6 is formed as a protective insulating film as shown in FIG. At this time, the oxide film in the NMOS region becomes the silicon oxynitride film 15 due to the effect of the nitrogen implanted earlier. Note that the timing of nitrogen implantation may be anywhere as long as it is before the formation of the protective insulating film. Thereby, a silicon oxide film on the PMOS side and a silicon oxynitride film on the NMOS side can be formed. The thickness of the protective insulating film is in the range of 0.5 nm to 3 nm.

  In order to further improve the wet etching resistance of the protective insulating films 6 and 15, surface oxide film modification treatment may be performed. For example, as shown in FIG. 8D, the surface of the silicon thermal oxide film as the protective insulating film is treated in a nitrogen plasma atmosphere to form the silicon oxynitride film 5. Instead of the nitrogen plasma atmosphere treatment, a silicon nitride film may be formed by a CVD (Chemical Vapor Deposition) method, a sputtering method, or an ALD (Atomic Layer Deposition) method. As a result, the protective insulating film in the PMOS region has a low nitrogen concentration on the silicon substrate side and a high nitrogen concentration on the surface side.

  After that, the process after 1st Embodiment FIG.4 (e) is implemented.

  As described above, even when the protective insulating film in the PMOS region contains nitrogen, the inactivation of boron in the pMOS region can be suppressed while increasing the etching resistance of the nMOS region by keeping the nitrogen-containing region away from the silicon substrate. it can.

PMOS potential distribution when silicon nitride film is in contact with silicon substrate Sectional drawing which shows 1st Embodiment of the semiconductor device of this invention Sectional drawing which shows 2nd Embodiment of the semiconductor device of this invention Process drawing which shows the manufacturing method of the semiconductor device of the 1st Embodiment of this invention Diagram showing the relationship between junction depth and parasitic resistance The figure which shows the etching rate to various chemicals of the silicon oxide film formed by each method Process drawing which shows the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention Process drawing which shows the manufacturing method of the semiconductor device of the 3rd Embodiment of this invention Sectional drawing which shows each manufacturing process of the semiconductor device concerning embodiment of the conventional method

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Oxide isolation film 3 Gate insulating film 4 Gate electrode 5 Protective insulating film (silicon nitride film)
6 Protective insulating film (silicon oxide film)
7 n-type source / drain region 8 p-type source / drain region 9 side wall spacer 10 resist 11 resist 12 resist 13 resist 14 silicon oxide film 15 which has grown faster and thickered by the effect of fluorine 15 silicon oxynitride film

Claims (6)

A semiconductor substrate;
A first gate insulating film formed on the substrate;
A first gate electrode formed on the first gate insulating film;
N-type source / drain regions formed in the semiconductor substrate on both sides of the first gate electrode;
A first protective insulating film covering at least the periphery of the first gate electrode on the surface of the N-type source / drain region;
NMISFET having
A second gate insulating film formed on the substrate;
A second gate electrode formed on the second gate insulating film;
P-type source / drain regions formed in the semiconductor substrate on both sides of the second gate electrode;
A second protective insulating film covering at least the periphery of the second gate electrode on the surface of the P-type source / drain region;
A PMISFET having
The first protective insulating film comprises one or more layers;
At least one layer is an insulating film which is a silicon nitride film or a silicon oxynitride film,
A portion of the second protective insulating film that is in contact with the semiconductor substrate is a silicon oxide film,
The distance from the silicon substrate under the second protective insulating film to the silicon nitride film or the silicon oxynitride film rather than the distance from the silicon substrate under the first protective insulating film to the silicon nitride film or silicon oxynitride film A semiconductor device characterized by having a long length. The N-type source / drain regions are
N-type deep source / drain regions formed outside the side wall of the gate electrode;
An N-type source / drain extension region extending from the deep source / drain region to the channel region below the gate electrode and shallower than the deep source / drain region;
An NMISFET in which the first protective insulating film covers at least the surface of the N-type source / drain extension region;
The P-type source / drain regions are
A P-type deep source / drain region formed outside the sidewall of the gate electrode;
A P-type source / drain extension region extending from the deep source / drain region to the channel region below the gate electrode, which is shallower than the deep source / drain region;
A PMISFET in which the second protective insulating film covers at least the surface of the P-type source / drain extension region;
The semiconductor device according to claim 1, comprising:   3. The semiconductor device according to claim 1, wherein thicknesses of the first protective insulating film and the second protective insulating film are 0.5 nm or more and 3 nm or less. On the semiconductor substrate on which the first and second gate insulating films and the gate electrode are formed,
Depositing a first protective insulating film whose portion in contact with the semiconductor substrate is a silicon oxide film;
After depositing the first protective insulating film, a step including covering a region including the p-type source / drain region with a mask such as a resist and removing the first protective insulating film in the region including the n-type source / drain region. When,
After the step of removing the first protective insulating film, a step of depositing a second protective insulating film consisting of one or more layers, at least one layer being a silicon nitride film or a silicon oxynitride film;
covering a region including a p-type gate electrode / source / drain region with a mask such as a resist, doping with an n-type impurity, and forming an n-type source / drain region in the semiconductor substrate;
After the second protective insulating film is deposited, the region including the n-type gate electrode / source / drain region is covered with a mask such as a resist, and doping with p-type impurities including molecules of boron or a plurality of boron is performed. Forming a p-type source / drain region in the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: On the semiconductor substrate in which the first and second gate insulating films and the gate electrode are formed, and the region including the n-type gate electrode / source / drain region is covered with a mask such as a resist,
Implanting impurities containing fluorine and stripping the resist;
Thereafter, a step of forming a silicon oxide film,
Subsequently, a step of depositing a silicon nitride film or performing a nitrogen atmosphere treatment,
A step of covering a region including the p-type gate electrode / source / drain region with a mask such as a resist, doping with an n-type impurity, and forming an n-type source / drain region in the semiconductor substrate;
The region including the n-type gate electrode / source / drain region is covered with a mask such as a resist, and doped with p-type impurities including a molecule composed of boron or a plurality of boron. Forming a drain region;
A method for manufacturing a semiconductor device, comprising: On the semiconductor substrate in which the first and second gate insulating films and the gate electrode are formed, and the region including the p-type gate electrode / source / drain region is covered with a mask such as a resist,
Implanting impurities containing nitrogen and stripping the resist;
Thereafter, a step of forming a silicon oxide film,
A step of covering a region including the p-type gate electrode / source / drain region with a mask such as a resist, doping with an n-type impurity, and forming an n-type source / drain region in the semiconductor substrate;
The region including the n-type gate electrode / source / drain region is covered with a mask such as a resist, and doped with p-type impurities including a molecule composed of boron or a plurality of boron. Forming a drain region;
A method for manufacturing a semiconductor device, comprising: