WO2013105550A1

WO2013105550A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2013105550A1
Application number: PCT/JP2013/050116
Authority: WO
Inventors: 穣小田; 寿史入沢; 手塚　勉
Original assignee: 独立行政法人産業技術総合研究所
Priority date: 2012-01-13
Filing date: 2013-01-08
Publication date: 2013-07-18
Also published as: TW201340184A; JP2013145800A

Abstract

A method for manufacturing a semiconductor device, wherein a gate structure part (100) including a gate insulating film (11) and a gate electrode (12) is formed on a semiconductor layer (10), and a gate sidewall film (16) that is an insulating film including a metallic material is formed on the sidewall of the gate structure part (100).

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a field effect semiconductor device and a method for manufacturing the same.

In order to reduce power consumption in CMOS devices, reduction of parasitic resistance in the source / drain region (SD region) of MOSEFET has become an important elemental technology. In recent years, with the aim of further reducing parasitic resistance, metal SD is formed in which an extension region is formed by a self-alignment process using a metal silicide such as NiSi (for example, non-patent literature). 1). Even when such a metal SD structure is used or an SD structure using a normal p / n junction, it is necessary to make the gate sidewall as thin as possible in order to sufficiently reduce the parasitic resistance.

Moreover, in the metal SD structure, there remains a problem in suppressing the leakage current as compared with the case where the p / n junction is used. In order to realize the metal SD structure in which the short channel effect is suppressed and the leakage current is suppressed, a method of forming a p / n junction region under the metal SD region excluding the extension portion in contact with the channel is effective (for example, non Patent Document 2). For this purpose, a semiconductor device using a double sidewall structure is proposed in which a very thin first gate sidewall film for reducing parasitic resistance is formed on the sidewall of the gate, and a second gate sidewall film is formed on the outside thereof. (For example, refer to Patent Document 1). However, also in this case, it is desirable to form the gate side wall (first gate side wall film) as thin as possible.

As described above, any of formation of an SD region using a normal p / n junction, formation of an SD region using a metal SD, and formation of an SD region combining a metal SD using a double sidewall and a p / n junction. Even in this case, it is desirable to make the side wall in contact with the gate as thin as possible while maintaining insulation. For this reason, it is considered that a process for forming the gate sidewall film with good control is essential.

Conventionally, it has been common to use an insulating film such as SiN or SiO ₂ as the gate sidewall film. However, in order to form a thin sidewall film using these films, there is a problem of substrate digging in the RIE process. That is, when a film type such as SiO ₂ or SiN is formed as the gate sidewall film, there is a possibility that the gate insulating film and the substrate are etched during RIE for forming the sidewall. This is due to the small selection ratio of gases such as CHF ₃ and CF ₄ used for RIE for sidewall formation with respect to the gate insulating film and the substrate. It is considered that this small selection ratio narrows the process margin, resulting in substrate digging. When such a substrate digging in the SD region, particularly in the extension region, is expected, the parasitic resistance of the MOSFET is greatly increased, the resistance variation for each device is increased, and the short channel effect is deteriorated. These are factors that cause deterioration and variations in element characteristics.

JP 2005-217245 A

An object of the present invention is to provide a semiconductor device that can form a thin insulating film on a gate side wall with good controllability without causing substrate digging and the like, and can improve element characteristics and reduce variations, and a method for manufacturing the same. There is.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming a gate structure portion including a gate insulating film and a gate electrode over a semiconductor layer, and an insulating film including a metal material on a sidewall of the gate structure portion. Forming a gate sidewall film.

More specifically, since it is essential to form a sidewall film with good controllability without causing digging of the substrate by RIE when forming the gate sidewall film, in order to realize this, the following is performed. Then, a sidewall film is formed after the gate is formed.

That is, the sidewall film is formed of a metal material such as TaN or TiN that can be easily oxidized and etched by RIE using a gas such as Cl ₂ having a high selectivity between the metal film and the oxide film (gate insulating film). Film and further RIE process. Thereafter, only the metal film is oxidized by irradiating plasma with oxygen supply, and this is used as a gate side wall film.

Also, an easily oxidized electrode material such as TaN or TiN is used for the gate electrode. Then, the electrode surface is oxidized in a state where the electrode surface after the gate structure is exposed, and this is used as an extremely thin sidewall film.

According to the present invention, by forming a gate sidewall film, which is an insulating film containing a metal material, on the sidewall of the gate structure portion, a thin insulating film can be formed on the gate sidewall with good controllability without causing substrate digging or the like. Can do. For this reason, it is possible to improve element characteristics and reduce variations.

More specifically, the following points are advantageous as compared with the case of using SiN, SiO ₂ of the prior art for the side wall. During the RIE process for forming the sidewall, the RIE selection ratio between the metal film and the oxide film (gate insulating film) is as high as 20 or more for Cl ₂ , for example, thereby suppressing the etching of the gate insulating film and substrate digging due to overetching. And the process margin is widened. As a result, an extension structure is obtained in which the parasitic resistance is small and the short channel effect can be suppressed. Therefore, it is possible to realize a MOS transistor that can obtain a high current with a lower gate overdrive.

It is sectional drawing which shows the first half of the manufacturing process of the semiconductor device concerning 1st Embodiment. FIG. 6 is a cross-sectional view showing the second half of the manufacturing process of the semiconductor device according to the first embodiment. It is process sectional drawing which shows the modification of 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning 3rd Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning 4th Embodiment. It is process sectional drawing which shows the modification of 4th Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device concerning 5th Embodiment.

Hereinafter, the details of the present invention will be described with reference to the illustrated embodiments.

(First embodiment)
1 and 2 are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment.

First, as shown in FIG. 1A, a gate insulating film 11 having a thickness of, for example, 5 nm, a gate electrode 12 having a thickness of, for example, 30 nm, and a gate hard mask 13 are formed in this order on the semiconductor substrate 10. Subsequently, the gate hard mask 13 and the gate electrode 12 are etched by photolithography and RIE (reactive ion etching) processes. As a result, the gate structure 100 is formed.

Here, the semiconductor substrate 10 may be a semiconductor including a high mobility material such as Si, Ge, SiGe, GaAs, GaSb, InP, InGaAs, and InAs. As the gate insulating film 11, an oxide or nitride of a substance contained in the semiconductor material can be used. Further, as the gate insulating film 11, Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , ZrO ₂ , LaLuO ₃ , LaAlOx, HfAlO, SiO ₂ , LaAlSiOx, a formed by ALD, CVD, PVD (sputtering) or the like. It may be a high-k insulating film such as -Si, c-Si, Y ₂ O ₃ or a mixture thereof. The gate electrode 12 is made of TaN, TiN, a-Si, poly-Si, a-Ge, poly-Ge, W, Al, Pd, Ti, Cr, Pt, Ni, Au, NiSi, NiGe, NiSiGe, or the like. It may be included. Further, the gate hard mask 13 may be SiN, SiO ₂ , a-Si, or the like.

Next, as shown in FIG. 1B, a metal film 14 that is easily oxidized by plasma irradiation in an oxygen atmosphere and RIE using Cl ₂ , BCl ₃ , CCl ₄ , or SiCl ₄ gas is formed into a desired film. A film is formed by a thickness (for example, 3 nm). The metal film 14 is formed by a method such as sputtering or CVD. Examples of the material of the metal film 14 include TaN, TiN, AlN, Ta, Ti, Al, Ni, Hf, W, a-Si, poly-Si, a-Ge, and poly-Ge.

Next, RIE is performed with a gas such as Cl ₂ , BCl ₃ , CCl ₄ , SiCl _4, etc., so that the metal film 14 is left only on the gate sidewall as shown in FIG. Here, in the RIE using a gas such as Cl ₂ , the selectivity between the metal film and the oxide film is as high as 20 or more. For this reason, the gate insulating film 11 is hardly etched, and therefore the semiconductor substrate 10 under the gate insulating film 11 is not etched.

The gate structure portion 100 including the metal film 14 on the gate side wall formed as described above is oxidized by exposure to oxygen gas, oxygen plasma, atomic oxygen, or the like. Then, as shown in FIG. 1D, the metal film 14 such as TaN becomes an insulating oxide film such as TaNOx or TaOx. As a result, a gate structure 200 in which a very thin (for example, 5 nm) gate sidewall film 16 is formed is obtained.

Next, as shown in FIG. 2A, the exposed gate insulating film 11 other than the gate structure 200 is removed. Subsequently, as shown in FIG. 2B, a metal film 17 is deposited to a thickness of 5 nm, for example, in order to form a metal-semiconductor alloy layer to be a metal extension region. Here, the metal film 17 may include, for example, Ni, Co, Ti, Pt, Pd, W, AuGe, Au, or the like.

Next, annealing for forming an alloy layer is performed to cause the surface of the substrate 10 to react with the metal film 17 to form a metal-semiconductor alloy layer 18 (for example, a metal silicide) as shown in FIG. Form. Subsequently, as shown in FIG. 2D, the unreacted metal film 17 is removed by wet processing. Thereby, the metal SD structure 18 by the self-alignment process is obtained.

Thereafter, as in a normal MOSFET manufacturing method, SiO ₂ or the like is deposited as an interlayer insulating film, and contact holes are formed by lithography, RIE, and wet processing. Further, contact formation that provides electrical contact with the SD region is performed, and wiring formation is performed to complete the MOS device.

As described above, according to the present embodiment, the gate sidewall film 16 formed on the sidewall of the gate structure portion 100 is formed of an insulating film containing a metal material, so that a thin insulating film is formed on the gate sidewall without causing substrate digging or the like. Can be formed with good controllability. For this reason, it is possible to improve element characteristics and reduce variations.

(Modification of the first embodiment)
As a modification of the first embodiment, an example of forming an SD region using a p / n junction instead of a metal SD structure is shown.

As shown in FIG. 3A, the process until the gate structure 200 is obtained is the same as that of the first embodiment (FIG. 1D). However, when impurities are introduced using ion implantation as described below, it is necessary to prevent unintentional doping into the channel directly under the gate due to the penetration of the impurity into the gate. For this reason, the gate electrode 12 needs to be thicker than the first embodiment (for example, 50 nm or more) in accordance with the ion implantation energy.

Next, as shown in FIG. 3B, an impurity region is doped into the semiconductor substrate 10 by an ion implantation method using the gate structure 200 as a mask, thereby forming an SD region 19 composed of a p / n junction. Subsequently, activation annealing is performed. Here, for an n-MOSFET, an n-type impurity (for example, P or As for a Si or Ge substrate, or Si for a III-V group compound substrate such as InGaAs) may be doped. Further, for a p-MOSFET, a p-type impurity (for example, B for a Si or Ge substrate or Be for a III-V group compound substrate such as InGaAs) may be doped. Further, ion implantation into the extension region or ion implantation for forming Halo may be performed.

Finally, as shown in FIG. 3C, a metal film containing Ni, Co, Ti, Pt, Pd, W, AuGe, Au, or the like is formed and salicide is performed. Thereby, the metal silicide layer 68 is formed, and the contact resistance of the wiring layer can be reduced and the resistance of the deep region of the SD region can be reduced. In FIG. 3C, an extension region 69 by ion implantation is also shown.

Thereafter, SiO ₂ or the like is deposited as an interlayer insulating film and contact formation is performed. However, the subsequent steps are the same as those in the first embodiment, and are omitted here.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 4A, the first embodiment (FIG. 1) is performed until the gate structure 300 having the gate insulating film 11, the gate electrode 22, and the gate hard mask 13 is formed on the semiconductor substrate 10. This is substantially the same as (a)). However, in the present embodiment, the material of the gate electrode 22 is oxygen such as TaN, TiN, AlN, a-Si, poly-Si, a-Ge, poly-Ge, Pd, Ti, W, Al, Ni, and Hf. It is desirable that the surface is composed of only a metal that easily oxidizes due to plasma treatment or the like.

After the gate structure 22 is formed using the easily oxidized metal such as TaN or TiN as the gate electrode 22, the side surface of the gate electrode 22 is oxidized by exposure to oxygen gas, oxygen plasma, atomic oxygen, or the like. . Then, as shown in FIG. 4B, for example, an oxide film 26 having a thickness of 5 nm is formed. As a result, the gate structure 400 in which the insulating gate sidewall film 26 is formed is obtained.

After forming the gate structure 400, the metal SD structure 18 can be formed in the same manner as in the first embodiment. Further, the subsequent steps are the same as those in the first embodiment, and are omitted here.

As described above, in this embodiment, the gate electrode 22 is oxidized to form the gate sidewall film 26, so that the substrate digging does not occur when the gate sidewall film 26 is formed. Therefore, the same effect as in the first embodiment can be obtained. In addition, the present embodiment has an advantage that the manufacturing process can be simplified because the formation of the metal film 14 and the RIE are not necessary as compared with the first embodiment.

(Modification of the second embodiment)
As a modification of the second embodiment, an example of forming an SD region using a p / n junction instead of a metal SD structure is shown.

The process until the gate structure 400 is obtained is the same as in the second embodiment. However, when the p / n junction is formed by ion implantation, it is necessary to increase the thickness of the gate electrode as described in the modification of the first embodiment.

Next, in the case of an n-MOSFET by ion implantation or the like, an n-type impurity (for example, P or As for a Si or Ge substrate, Si for an III-V group compound substrate such as InGaAs) is doped. . Further, for a p-MOSFET, a p-type impurity (for example, B for a Si or Ge substrate or Be for a III-V group compound substrate such as InGaAs) is doped. Further, ion implantation into the extension region or ion implantation for forming Halo may be performed. Subsequently, activation annealing is performed.

Next, SiO ₂ or the like is deposited as an interlayer insulating film, and contact formation or the like is performed. However, the subsequent steps are the same as those in the first embodiment, and are omitted here.

(Third embodiment)
FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the third embodiment. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

The process is the same as that of the first embodiment until a gate structure including a gate sidewall which is an insulating film is formed. That is, it is considered that the gate structure 200 in the first embodiment is formed. Here again, as in the modification of the first embodiment, the ion implantation process is performed later, so that the gate height needs to be as high as in the modification of the first embodiment.

Next, as shown in FIG. 5A, the gate sidewall film 36 (second gate structure) is formed on the gate structure portion (the above-described gate structure portion 200) on which the gate sidewall film 16 (first gate sidewall film) is formed. A gate structure 500 having a gate sidewall film is formed. Here, the gate sidewall film 36 may be an insulating film such as SiO ₂ or SiN. The gate sidewall film 36 may be formed by using a so-called sidewall leaving technique in which an insulating film is deposited on the entire surface and then etched back by RIE. The thickness of the gate sidewall film 36 may be about the thickness of the impurity diffusion length in the lateral direction by ion implantation and activation after the sidewall formation, for example, 20 nm.

Next, as shown in FIG. 5B, for an n-MOSFET, an n-type impurity (for example, P or As for a Si or Ge substrate, or Si group for an IIII-V group compound substrate such as InGaAs) is used. In the case of a p-MOSFET, a p-type impurity (for example, B for a Si or Ge substrate or Be for a III-V group compound substrate such as InGaAs) is implanted. Then, an SD region 19 is formed by performing activation annealing.

Next, as shown in FIG. 5C, the gate sidewall film 36 is removed by wet processing such as HF. Subsequently, the gate insulating film 11 formed on the SD region 19 is removed by wet processing or the like.

Next, as shown in FIG. 5D, a metal SD structure 18 is formed by forming a metal material and performing an annealing process, as in the first embodiment. Here, the metal material for forming the metal-semiconductor alloy layer may be a metal including Ni, Co, Ti, PT, Pd, W, AuGe, and Au. Thus, the metal-semiconductor alloy layer 18 is formed by self-alignment. Subsequently, if there is an unreacted metal, it is removed by wet treatment or the like.

Through the above steps, the extension is converted into metal SD, and the SD region is formed in which the p / n junction is formed in the deep region and low parasitic resistance and low leakage current are realized.

Thus, according to the present embodiment, the etching selectivity between the first gate sidewall film 16 made of TaNOx or the like and the second gate sidewall film 36 made of SiO ₂ or the like can be increased. For this reason, when the gate sidewall film 36 is removed by etching, the gate sidewall film 16 remains almost unetched. Therefore, even in the structure in which the metal SD using the double sidewall and the p / n junction are combined, the same effect as in the first embodiment can be obtained.

(Modification of the third embodiment)
As a modification of the third embodiment, an example is shown in which a side surface of a metal gate similar to that of the second embodiment is oxidized to form a gate structure including gate sidewalls that are insulating films.

First, the process is the same as in the second embodiment (FIG. 4B) until the side surface of the metal gate is oxidized to form the side wall made of the oxide film 26. That is, it is considered that the gate structure 400 in the second embodiment is formed. Hereinafter, since the second gate sidewall film 36 is formed and the metal SD region is formed in the same manner as in the third embodiment, the details thereof are omitted.

(Another modification of the third embodiment)
As a further modification of the metal SD structure obtained in the third embodiment and the modification of the third embodiment, an example of SD region formation using a p / n junction will be shown.

This is the same until the deep region is ion-implanted and the second gate sidewall film 36 is removed in the third embodiment and the modification of the third embodiment (FIG. 5C). Next, in the state where the first gate sidewall film 16 remains, the extension region is ion-implanted and activation annealing is performed. Thereafter, contact formation and wiring formation are performed by performing post-processes in the same manner as in the first embodiment. Thereby, a MOS device can be obtained.

(Fourth embodiment)
FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

Until the gate structure in which the side wall is not oxidized is formed, it is omitted here because it is the same as in the first embodiment (FIG. 1C). As a result, as shown in FIG. 6A, it is assumed that the gate structure 600 in which the metal film 14 (first gate sidewall film) is formed on the gate sidewall is formed.

Next, as shown in FIG. 6B, a gate structure 700 in which the gate sidewall film 36 (second gate sidewall film) is formed is formed. Here, the gate sidewall film 36 may be an insulating film such as SiO ₂ or SiN.

Next, as shown in FIG. 6C, a source / drain region 19 is formed in the structure in which the gate structure 700 is formed. That is, an n-type impurity for an n-MOSFET (eg, P or As for a Si or Ge substrate, Si for an III-V group compound substrate such as InGaAs), or a p-type for a p-MOSFET. Impurities (for example, B for Si or Ge substrates, Be for III-V group compound substrates such as InGaAs) are implanted. Then, activation annealing is performed.

Next, as shown in FIG. 6D, the gate sidewall film 36 is removed by wet processing such as HF. Here, since the metal film 14 which is the gate sidewall film is exposed, the metal film 14 formed on the gate sidewall is oxidized by exposure to oxygen gas, oxygen plasma, atomic oxygen, or the like. As described above, the gate structure portion in which the gate sidewall film 16 (third gate sidewall film) which is an insulating film is formed is obtained.

Since the subsequent metal SD region formation process is the same as that of the third embodiment, it is omitted here. Furthermore, contact formation and wiring formation are performed by performing a post-process in the same manner as in the first embodiment. Thereby, a MOS device can be obtained.

As described above, according to this embodiment, in the state where the metal film 14 as the first gate sidewall film is formed on the sidewall of the gate structure 100, the formation of the second gate sidewall film 36, ion implantation, Removal is performed and finally the metal film 14 is oxidized to form a third gate sidewall film 16. Thereby, the thin insulating film 16 can be formed on the gate side wall with good controllability without causing substrate digging or the like. For this reason, even in the structure in which the metal SD using the double sidewall and the p / n junction are combined, the same effect as in the first embodiment can be obtained.

(Modification of the fourth embodiment)
As shown in FIG. 7A, the process is the same as in the second embodiment (FIG. 4A) until the gate structure 300 is formed. That is, as the material of the gate electrode 22, only those containing metals that are easily oxidized by oxygen plasma treatment, such as TaN, TiN, AlN, a-Si, poly-Si, a-Ge, W, Al, Ni, and Hf. It shall consist of

Next, as shown in FIG. 7B, a gate structure portion 800 in which the gate sidewall film 36 (first gate sidewall film) is formed is formed. Here, the gate sidewall film 36 may be an insulating film such as SiO ₂ or SiN. In contrast to the structure in which the gate structure 800 is formed, an n-type impurity is used for an n-MOSFET (eg, P or As for a Si or Ge substrate, or a III-V group compound substrate such as InGaAs or the like). Si) and p-type MOSFETs are implanted with p-type impurities (for example, B for Si and Ge substrates, Be for III-V group compound substrates such as InGaAs). Then, activation annealing is performed. As a result, an SD region 19 composed of a p / n junction is formed.

Next, as shown in FIG. 7C, the gate sidewall film 36 is removed by wet processing such as HF. Since the side surface of the gate electrode 22 is exposed in this state, the side surface of the gate electrode 22 is oxidized by performing oxidation by oxygen plasma treatment or the like. Thereby, as shown in FIG. 7D, a gate structure having an insulating gate sidewall film 46 (second gate sidewall film) on the sidewall of the gate electrode 22 can be formed. At this time, the thickness of the gate sidewall film 46 can be made extremely thin by controlling the oxidation time or the like.

The subsequent metal SD region formation process is the same as that in the third embodiment, and is omitted here. Furthermore, contact formation and wiring formation are performed by performing a post-process in the same manner as in the first embodiment. Thereby, a MOS device can be obtained.

(Another modification of the fourth embodiment)
As a modification to the fourth embodiment and its modification, an example of forming an SD region using a p / n junction instead of a metal SD structure is shown. 7D is performed until the second gate sidewall film 46 is formed (oxidized) after the deep region ion implantation is performed and the first gate sidewall film 36 is removed.

Next, ion implantation is performed on the extension region, and activation annealing is performed. Thereafter, contact formation and wiring formation are performed by performing post-processes in the same manner as in the first embodiment. Thereby, a MOS device can be obtained.

(Fifth embodiment)
FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment. In addition, the same code | symbol is attached | subjected to FIG. 5 and an identical part, and the detailed description is abbreviate | omitted.

This embodiment is a combination of the sidewall formation process shown in the first to fourth embodiments and the replacement gate process that is promising for improving the gate interface characteristics when using a Ge or III-V group substrate. A device fabrication example will be described.

As in the first to fourth embodiments and their modifications, a gate structure, a gate sidewall film, and an SD region are formed. Here, as an example, the process up to the step shown in FIG. 5D of the third embodiment is performed, and the gate insulating film 11, the gate electrode 12, and the gate hard mask 13 are used as a dummy gate structure.

Next, as shown in FIG. 8A, an insulating film 50 such as SiO ₂ that sufficiently embeds the dummy gate structure is formed using PECVD or the like.

Next, as shown in FIG. 8B, the CMP process is performed so that the head of the gate electrode 12 or the gate hard mask 13 is exposed or the gate electrode 12 and the gate hard mask 13 are reduced by about several nm.

Next, as shown in FIG. 8C, the gate hard mask 13, the gate electrode 12, and the gate insulating film 11 are removed by wet processing or RIE. Here, in the removal process of the gate hard mask 13 and the gate electrode 12, it is necessary to select a material that can have a sufficient removal selection ratio with respect to the buried insulating film 50. For example, if the buried insulating film 50 is SiO ₂ , it is desirable to use SiN for the gate hard mask 13 and a-Si for the gate electrode 12. This is because these materials can be selectively removed without etching SiO ₂ by using H ₃ PO _{4 for} SiN and TMAH for a-Si.

As for the gate insulating film 11, it is not desirable that the substrate 10 is damaged when the gate insulating film 11 is removed. For this reason, it is desirable to use an etchant that can be removed only by wet treatment and that can be removed by an etchant that does not etch the substrate, such as HF. Examples of such a film include SiO ₂ and Al ₂ O ₃ .

After removing all the dummy gate structures, a gate insulating film 51 is formed again by ALD or CVD as shown in FIG. Further, a gate electrode 52 is formed thereon by sputtering or CVD. Subsequently, as shown in FIG. 8E, the gate is formed by removing the gate electrode 52 on the insulating film 50 by CMP. Thereafter, by forming an interlayer insulating film and wiring, it is possible to realize a MOSFET having good interface characteristics, low parasitic resistance and low leakage current.

As described above, according to the present embodiment, by using a metal oxide film such as TaNOx as the sidewall film 16 of the dummy gate structure, the sidewall film 16 is hardly etched when the dummy gate structure is removed. become. For this reason, as shown in the first to fourth embodiments, it is possible to form a thin sidewall without digging the substrate. Furthermore, the substrate digging can be suppressed by removing the gate insulating film 11 having the dummy gate structure by wet processing. Therefore, by combining the sidewall formation process shown in the first to fourth embodiments and the replacement gate process, it is possible to further improve the element characteristics and reduce variations.

(Modification)
The present invention is not limited to the above-described embodiments.

The metal material for forming the gate sidewall film in the first embodiment is not limited to that described in the embodiment, and may be any material having a sufficient etching selectivity with respect to the gate insulating film and the substrate.

In the first embodiment, the insulating gate sidewall film is formed by oxidizing the metal film only on the gate sidewall, but the present invention is not limited to this. For example, after the metal film formed on the entire surface is oxidized to form an insulating film, the insulating film may be etched back to leave the insulating film only on the gate sidewall. In this case, the material of the gate sidewall film made of an insulating film may be any material having a sufficient etching selectivity with respect to the gate insulating film or the substrate.

Also, the semiconductor substrate is not necessarily limited to a bulk substrate, and for example, a semiconductor layer formed on an insulating layer on the substrate may be used.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope of the present invention and the gist thereof, and are also included in the invention described in the scope of claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ...

Semiconductor substrate

11, 51 ...

Gate insulating film

12, 22, 52 ... Gate electrode 13 ... Gate hard mask 14 ...

Metal film

16, 26, 46 ... Thin gate side wall film 17 ... Metal film 18 ... Metal-semiconductor Alloy layer (Metal SD structure)
19: Source / drain region (SD region)
36: thick gate sidewall film 50: buried insulating

film

100, 200, 300, 400, 50, 600, 700, 800 ... gate structure

Claims

Forming a gate structure including a gate insulating film and a gate electrode on the semiconductor layer;
Forming a gate sidewall film that is an insulating film containing a metal material on the sidewall of the gate structure;
A method for manufacturing a semiconductor device.
The gate sidewall film is formed by forming an insulating gate sidewall film by forming a metal film on the sidewall of the gate structure and then oxidizing the metal film. A method for manufacturing a semiconductor device.
The gate sidewall film is formed by forming the gate electrode from metal and oxidizing the side surface of the metal gate electrode to form an insulating gate sidewall film. A method for manufacturing a semiconductor device.
Forming a gate structure including a gate insulating film and a gate electrode on the semiconductor layer;
Forming a first gate sidewall film, which is an insulating film containing a metal material, on the sidewall of the gate structure;
A second gate sidewall film having a thickness different from that of the first gate sidewall film is formed on the outside of the first gate sidewall film.
Source / drain regions are formed by doping impurities into the semiconductor layer using the gate structure portion and the first and second gate sidewall films as a mask,
Removing the second gate sidewall film after forming the source / drain regions;
A method for manufacturing a semiconductor device.
Forming a gate structure including a gate insulating film and a gate electrode on the semiconductor layer;
Forming a first gate sidewall film made of a metal material on the sidewall of the gate structure;
A second gate sidewall film having a thickness different from that of the first gate sidewall film is formed on the outside of the first gate sidewall film.
Source / drain regions are formed by doping impurities into the semiconductor layer using the gate structure portion and the first and second gate sidewall films as a mask,
After the formation of the source / drain regions, the second gate sidewall film is removed,
After the removal of the second gate sidewall film, an insulating third gate sidewall film is formed by oxidizing the first gate sidewall film.
A method for manufacturing a semiconductor device.
A gate structure including a gate insulating film and a gate electrode made of a metal material is formed on the semiconductor layer,
Forming a first gate sidewall film on the sidewall of the gate electrode;
Source / drain regions are formed by doping impurities into the semiconductor layer using the gate structure portion and the first gate sidewall film as a mask,
After the formation of the source / drain regions, the first gate sidewall film is removed,
After the removal of the first gate sidewall film, the side surface of the gate electrode is oxidized to form an insulating second gate sidewall film having a thickness smaller than that of the first gate sidewall film.
A method for manufacturing a semiconductor device.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate includes Si, Ge, or a III-V group compound semiconductor.
7. The metal material for forming the gate sidewall film is at least one selected from TaN, TiN, AlN, Ta, Ti, Al, Ni, Hf, and W. A method for manufacturing the semiconductor device according to claim 1.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the side surface of the gate electrode is oxidized using oxygen gas, oxygen plasma, or atomic oxygen.
A gate structure formed on the semiconductor layer and including a gate insulating film and a gate electrode;
A gate sidewall film, which is an insulating film containing a metal material, formed on the sidewall of the gate structure;
Source / drain regions formed on the surface of the semiconductor layer with the gate structure interposed therebetween;
A semiconductor device comprising: