JP2009164218A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve carrier mobility in a channel region, without causing film cracking on a stress liner film or the like. <P>SOLUTION: In a semiconductor device, a sidewall 107 is provided beside the side face of a gate electrode 103 of an NMOS transistor. The height of the sidewall 107 is 1/3 or lower the height of the gate electrode 103, and the width at the upper surface of a semiconductor substrate 100 is equal to or less than the gap between the gate electrode 103 and an n-type source region or n-type drain region 108. A stress liner film 111 having a tensile stress of 1.7 GPa or larger is so provided on the upper surface of the semiconductor substrate as to cover the gate electrode 103 and the sidewall 107. The thickness of the film is 25 nm or larger. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a liner SiN film (stress liner film) and a manufacturing method thereof.

  In recent years, the capacity of semiconductor devices has increased significantly, and miniaturization of MOS (mental-oxide semiconductor) transistors has progressed to the point where the width of the gate electrode is 40 nm or less. In response to the high-speed processing of the semiconductor device, a distortion technique has been already put into practical use in which the driving force of the semiconductor device is increased by applying stress to the channel region of the transistor.

  When strain is introduced into the channel region of a transistor, the band structure of the channel region changes, resulting in a change in the effective mass of carriers in the channel region, resulting in a change in band occupancy, etc., and a change in carrier mobility in the channel region. .

  In order to apply strain to the channel region, stress may be applied to the channel region. The stress applied to the channel region is different between the case where stress is applied to the channel region of a negative channel mental-oxide semiconductor (NMOS) transistor and the case where stress is applied to the channel region of a PMOS (positive channel mental-oxide semiconductor) transistor. In contrast, it is known that a tensile stress may be applied to a channel region in an NMOS transistor and a compressive stress may be applied to a channel region in a PMOS transistor.

The simplest strain technique for increasing the carrier mobility in the channel region of a transistor is to use a SiN film having a film stress as a contact liner film (see Patent Document 1). In this case, as the contact liner film, a SiN film having a tensile stress is used for the NMOS transistor, and a SiN film having a compressive stress is used for the PMOS transistor. Further, in order to further increase the carrier mobility in the channel region, it is only necessary to increase the stress applied to the channel region. For that purpose, the contact liner SiN film may be thickened.
Japanese Patent Laid-Open No. 2003-60076

  However, as the miniaturization of MOS transistors progresses, the distance between MOS transistors is becoming increasingly narrow, and it is difficult to increase the thickness of the liner SiN film. As a solution to this problem, for example, as disclosed in the literature X. Chen et.al., VLSI p74, 2006, a method of increasing the thickness of the liner SiN film by eliminating the sidewall portion from the transistor is proposed. Has been.

  However, it has been found that when the liner SiN film is made thicker by removing the sidewall portion from the transistor, the following two problems occur.

  The first problem is that the carrier mobility in the channel region cannot be increased even if the stress liner film thickness of the NMOS transistor is increased to 25 nm or more. As a method of providing a liner SiN film in an NMOS transistor, a method of generating a tensile stress by causing film contraction to the SiN film after forming the SiN film is used. However, when the liner SiN film is made thick, cracks occur in the liner SiN film beside the gate electrode in the process of shrinking the film. The reason is that when the liner SiN film becomes thicker, the contraction length when shrinking the liner SiN film becomes longer, so the tensile force upward and laterally increases on the side of the gate electrode, and as a result, the gate electrode This is probably because the liner SiN film is cracked at the boundary between it and the liner SiN film. When cracking occurs in the liner SiN film, stress cannot be effectively applied to the channel region, and carrier mobility in the channel region cannot be improved.

  The second problem is that when the liner SiN film is made thick, not only the stress applied to the channel region of the transistor is increased, but also the stress applied to the offset sidewall provided on the side surface of the gate electrode is increased. This means that peeling occurs at the interface between the gate electrode and the offset sidewall. If the offset sidewall is peeled off from the side surface of the gate electrode, the stress from the liner SiN film is not effectively applied to the channel region, and the carrier mobility in the channel region cannot be improved.

  The present invention has been made in view of this point, and an object of the present invention is to improve carrier mobility in a channel region without causing a crack in a stress liner film or the like.

  In the semiconductor device of the present invention, an offset sidewall is provided on the side surface of the gate electrode of the NMOS transistor, and a sidewall is provided beside the offset sidewall. The height of the sidewall is not more than 1/3 of the height of the gate electrode, and the width on the upper surface of the semiconductor substrate is not more than the distance between the gate electrode and the n-type source region or n-type drain region. In addition, a stress liner film having a tensile stress of 1.7 GPa or more is provided on the upper surface of the semiconductor substrate so as to cover the gate electrode and the sidewall, and the film thickness is 25 nm or more.

  In the above configuration, since the NMOS transistor has such a sidewall, when forming the stress liner film, the direction of the tensile force when the stress liner film is pulled laterally and the stress liner film upward. Even if the angle formed by the direction of the tensile force when pulled is greater than 90 degrees, and the film thickness of the stress liner film is 25 nm or more, the occurrence of film cracking in the stress liner film can be prevented. Therefore, it is possible to achieve both the thickening of the stress liner film and the prevention of film cracking in the stress liner film, and the carrier mobility in the channel region can be improved without causing film cracking in the stress liner film. . The stress liner film is preferably 25 nm or more and 100 nm or less.

  In the semiconductor device of the present invention, the isolation region for separating the NMOS transistor and the PMOS transistor is provided in the semiconductor substrate, and the height of the side wall provided beside the gate electrode is the gate electrode in the NMOS transistor. However, it is preferable that the height of the gate electrode of the PMOS transistor is substantially the same as that of the gate electrode.

  As a result, in the NMOS transistor, it is possible to achieve both the thickening of the stress liner film and the prevention of film cracking in the stress liner film. In the PMOS transistor, the tensile stress applied from the stress liner film to the channel region can be reduced. Can be suppressed.

  In the semiconductor device of the present invention, the offset sidewall may be formed by oxidizing the gate electrode.

  Thereby, the adhesion between the offset sidewall and the gate electrode can be improved. Therefore, even if the stress applied to the channel region is increased by setting the thickness of the stress liner film to 25 nm or more, it is possible to prevent the offset sidewall from peeling off from the gate electrode.

  In the semiconductor device of the present invention, the second sidewall having an L-shaped cross section may be provided between the side surface of the offset sidewall and the upper surface of the semiconductor substrate and the sidewall.

  In the first method of manufacturing a semiconductor device according to the present invention, when the sidewall is formed beside the gate electrode of the NMOS transistor, the height of the sidewall is set to 1/3 or less of the height of the gate electrode. The width of the sidewall on the upper surface of the gate electrode is set to be equal to or smaller than the distance between the gate electrode and the n-type source region or the n-type drain region. A stress liner film having a tensile stress of 1.7 GPa or more is provided so as to cover the gate electrode, the offset sidewall, and the sidewall. At this time, the film thickness is set to 25 nm or more.

  In the above method, when the stress liner film is formed, the angle formed by the direction of the tensile force when the stress liner film is pulled laterally and the direction of the tensile force when the stress liner film is pulled upward is 90 degrees. Become bigger. Therefore, even if a stress liner film having a film thickness of 25 nm or more is provided, it is possible to prevent film cracking in the stress liner film. Therefore, a stress liner film can be provided without film cracking, and carrier mobility in the channel region can be improved.

  In the second method for manufacturing a semiconductor device of the present invention, first, an isolation region for separating the NMOS transistor formation region and the PMOS transistor formation region is provided in the semiconductor substrate. Thereafter, a sidewall is formed beside the gate electrode. When forming a sidewall beside the gate electrode of the NMOS transistor, the height of the sidewall is set to 1/3 or less of the height of the gate electrode. The width of the sidewall on the upper surface of the substrate is set to be equal to or smaller than the distance between the gate electrode and the n-type source region or the n-type drain region. On the other hand, when the sidewall is formed beside the gate electrode of the PMOS transistor, the height of the sidewall is made substantially the same as the height of the gate electrode. Then, a stress liner film having a tensile stress of 1.7 GPa or more is provided on the upper surface of the semiconductor substrate so as to cover the gate electrode, the offset sidewall, and the sidewall. At this time, the film thickness is set to 25 nm or more.

  In the above method, a thick stress liner film can be provided in the NMOS transistor formation region without causing film cracking. Therefore, carrier mobility in the channel region of the NMOS transistor can be improved.

  In the PNMO transistor, the tensile stress applied from the stress liner film to the channel region can be suppressed.

  Carrier mobility in the channel region can be improved without causing film cracking in a stress liner film or the like.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, below, the same code | symbol may be attached | subjected to the same component and the description may be abbreviate | omitted. Further, the present invention is not limited to the following embodiment.

(First embodiment)
FIG. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention. 2A to 2E show a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

  In the present embodiment, an NMOS transistor is taken as an example of a semiconductor device, and its manufacturing method and configuration will be described. Below, the manufacturing method of the semiconductor device concerning this embodiment is shown first.

In the step shown in FIG. 2A, first, a shallow trench (isolation region) 101 is formed in a semiconductor substrate (for example, a silicon substrate) 100 using a known method, and then the upper surface of the semiconductor substrate 100 is formed. A gate insulating film 102 and a gate electrode 103 are formed in order, and then an offset sidewall 104 is formed on the side surface of the gate electrode 103. Here, a metal such as polysilicon or TiN can be used as the electrode material of the gate electrode 103, and a SiO ₂ film can be used as the offset sidewall 104.

In the step shown in FIG. 2B, first, an n-type extension region 105 is formed in the semiconductor substrate 100 by using an ion implantation method. Next, after depositing a SiO ₂ film on the upper surface of the semiconductor substrate 100 so as to be flush with the upper surface of the gate electrode 103, dry etching is performed on the SiO ₂ film. As a result, a sidewall (second sidewall) 106 having an L-shaped cross section is formed so as to cover the surface of the offset sidewall 104 and a part of the upper surface of the semiconductor substrate 100. Thereafter, a SiN film is deposited on the upper surface of the semiconductor substrate 100 so as to be flush with the upper surface of the gate electrode 103, and then dry etching is performed on the SiN film. For example, a SiN film of about 30 nm is formed by LP-CVD and then etched back by dry etching. Thereby, the sidewall 107 is formed so as to cover the sidewall 106.

  In the step shown in FIG. 2C, first, n-type source / drain regions 108 are formed in the semiconductor substrate 100 by ion implantation and activation annealing. At this time, the sidewall 107 functions as a self-alignment mask when the n-type source / drain region 108 is formed by ion implantation. Thereafter, the gate electrode 103 and the n-type source / drain region 108 are silicided to form a silicide layer 109.

  In the step shown in FIG. 2D, the sidewall 107 is etched to form the sidewall 110. By this etching, the height of the sidewall 110 is set to 1/3 or less of the height of the gate electrode 103, and the width of the sidewall 110 on the upper surface of the semiconductor substrate 100 is set to the n-type source region (or drain region) 108 and the gate electrode 103. Or less. As an etching method, for example, wet etching using hot phosphoric acid can be employed.

In the step shown in FIG. 2E, the stress liner film 111 is provided on the upper surface of the semiconductor substrate 100 so as to cover the gate electrode 103 and the sidewall 110. As the stress liner film 111, a SiN film having a tensile stress of 1.7 GPa or more is preferably used, and the stress liner film 111 is preferably provided so that the film thickness is 25 nm or more and 100 nm or less. Specifically, an H-rich SiN film is formed by CVD (Chemical Vapor Deposition) by flowing SiH ₄ gas and NH ₃ gas at 300 ° C, and then ultraviolet light is irradiated at 400 ° C to desorb H. Then, film shrinkage occurs in the SiN film, and as a result, the tensile stress of the SiN film can be 1.7 GPa or more. At this time, the film shrinkage rate of the SiN film is preferably 10% or more. Thereby, the semiconductor device according to the present embodiment can be manufactured.

Briefly describing the structure of a semiconductor device manufactured using the above method, a gate insulating film 102 and a gate electrode 103 are sequentially provided on the upper surface of the semiconductor substrate 100, and an offset side is provided on a side surface of the gate electrode 103. A wall 104 is provided. A side wall 106 made of an SiO ₂ film having an L-shaped cross section is provided beside the offset side wall 104, and a side wall 110 made of a SiN film is provided on the side wall 106. A stress liner film 111 is provided on the semiconductor substrate 100 so as to cover the gate electrode 103 and the sidewall 110.

  The height of the sidewall 110 is 1/3 or less of the height of the gate electrode 103, and the width of the sidewall 110 on the upper surface of the semiconductor substrate 100 is not more than the distance between the gate electrode 103 and the n-type source region or drain region 108. . The stress liner film 111 has a tensile stress of 1.7 GPa or more, and its film thickness is 25 nm or more and 100 nm or less.

  As described above, in the semiconductor device of this embodiment, the height of the sidewall 110 is 1/3 or less of the height of the gate electrode 103, and the width of the sidewall 110 on the upper surface of the semiconductor substrate 100 is equal to that of the gate electrode 103. It is equal to or less than the distance from the source region or drain region 108. Therefore, even when the stress liner film 111 is thickened (for example, the film thickness is 25 nm or more), when the stress liner film 111 is formed, the direction of the tensile force when the stress liner film is pulled in the lateral direction and the stress liner film The angle formed by the direction of the pulling force when pulling up is greater than 90 degrees. Therefore, since the stress liner film 111 can be made thick without causing any film cracking in the stress liner film 111, the stress applied to the channel region of the NMOS transistor can be effectively increased. Thereby, in this embodiment, the carrier mobility in the channel region of the semiconductor device can be improved.

  In the present embodiment, the side wall 106 having an L-shaped cross section may not be provided. In that case, the sidewall 110 may be provided beside the offset sidewall 104.

(Second Embodiment)
In the first embodiment, an NMOS transistor is taken as an example of a semiconductor device, and its configuration and manufacturing method are described. In the second embodiment of the present invention, a complementary mental-oxide semiconductor (CMOS) transistor is taken as an example of a semiconductor device, and its configuration and manufacturing method will be described.

  FIG. 3 shows the structure of a CMOS transistor according to the second embodiment of the present invention. 4A to 5C show a method for manufacturing a CMOS transistor according to the second embodiment of the present invention.

  4A, first, a shallow trench 101 is formed in the semiconductor substrate 100, and the semiconductor substrate 100 is separated into an NMOS transistor formation region Tr._N and a PMOS transistor formation region Tr._P. Next, in the NMOS transistor formation region Tr._N, the gate insulating film 102 and the gate electrode 103 are sequentially formed on the upper surface of the semiconductor substrate 100, and then the offset sidewall 104 is formed on the side surface of the gate electrode 103. An n-type extension region 105 is formed in the semiconductor substrate 100 by an implantation method. In the PMOS transistor formation region Tr._P, after forming the gate insulating film 102 and the gate electrode 203 in order on the upper surface of the semiconductor substrate 100, the offset sidewall 104 is formed on the side surface of the gate electrode 203, and then ion implantation is performed. A p-type extension region 205 is formed in the semiconductor substrate 100 by the method.

  In the step shown in FIG. 4B, after the sidewall 106 having an L-shaped cross section is formed beside the gate electrodes 103 and 203 in the NMOS transistor formation region Tr._N and the PMOS transistor formation region Tr._P, respectively. The sidewall 107 is formed on the sidewall 106. Thereafter, n-type source / drain regions 108 are formed in the semiconductor substrate 100 in the NMOS transistor formation region Tr._N, and p-type source / drain regions 208 are formed in the semiconductor substrate 100 in the PMOS transistor formation region Tr._P. Form.

  In the step shown in FIG. 4C, the gate electrodes 103 and 203, the n-type source / drain region 108 and the p-type source / drain region 208 are silicided to form a silicide layer 109.

In the step shown in FIG. 5A, a SiO ₂ film is provided on the upper surface of the semiconductor substrate 100 so as to cover the gate electrodes 103 and 203 and the sidewalls 107, and then a PMOS transistor formation region Tr._P in the SiO ₂ film. The SiO ₂ film is etched so that only the portion provided inside remains. Thereby, the mask 212 can be formed in the PMOS transistor formation region Tr._P. At this time, the thickness of the mask is preferably about 20 nm.

  In the step shown in FIG. 5B, the sidewall 107 is etched. By this etching, the sidewall 107 formed in the NMOS transistor formation region Tr._N is etched to become the sidewall 110. Specifically, as described in the first embodiment, the height of the sidewall 110 is 1/3 or less of the height of the gate electrode 103, and the width of the sidewall 110 on the upper surface of the semiconductor substrate 100 is the gate. The distance is less than or equal to the distance between the electrode 103 and the n-type source region or drain region 108. On the other hand, the sidewall 107 formed in the PMOS transistor formation region Tr._P is covered with the mask 212 and is not etched. Thereafter, the mask 212 is removed.

  In the step shown in FIG. 5C, as in the step shown in FIG. 2E, the stress liner film 111 is provided on the upper surface of the semiconductor substrate 100 so as to cover the gate electrodes 103 and 203 and the sidewalls 107 and 110.

  Briefly describing the structure of a semiconductor device manufactured using the above method, the semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor has the same structure as the semiconductor device according to the first embodiment, and the shape of the sidewall is different between the PMOS transistor and the NMOS transistor. Specifically, in the NMOS transistor, the height is 1/3 or less of the height of the gate electrode 103 beside the side wall 106 having an L-shaped cross section, and the width of the upper surface of the semiconductor substrate 100 is the gate electrode 103. Side walls 110 that are equal to or smaller than the distance between the n-type source / drain regions 108 are provided. On the other hand, in the PMOS transistor, a side wall 107 having a height substantially equal to the height of the gate electrode 203 is provided beside the side wall 106 having an L-shaped cross section.

  As described above, in the semiconductor device according to the present embodiment, the sidewall 110 is provided on the side surface of the gate electrode 103 of the NMOS transistor, as in the first embodiment. Therefore, even when the thickness of the stress liner film 111 is 25 nm or more, when the stress liner film 111 is formed, the direction of the tensile force when the stress liner film is pulled laterally and the tensile force when the stress liner film is pulled upward The angle formed by the direction of force is greater than 90 degrees. Therefore, since the stress liner film 111 can be made thick without causing film cracks in the stress liner film 111, the stress applied to the channel region of the NMOS transistor can be effectively increased.

  In the semiconductor device of this embodiment, the sidewall 107 having the same height as the gate electrode 203 is provided on the side surface of the gate electrode 203 of the PMOS transistor. Therefore, the tensile stress applied from the stress liner film 111 to the channel region can be suppressed. Thereby, in this embodiment, the carrier mobility in the channel region of the semiconductor device can be improved.

  In the present embodiment, as in the first embodiment, the sidewall 106 having an L-shaped cross section may not be provided. In that case, the side walls 107 and 110 may be provided beside the offset side wall 104.

(Third embodiment)
The third embodiment of the present invention is a modification of the second embodiment. Specifically, the SiO ₂ film is deposited on the side surface of the gate electrode in the _second embodiment, but the side surface of the gate electrode is oxidized in this embodiment. This will be specifically described below.

  6A to 7C show a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

  In the step shown in FIG. 6A, first, a shallow trench 101 is formed in the semiconductor substrate 100, and the semiconductor substrate 100 is separated into an NMOS transistor formation region Tr._N and a PMOS transistor formation region Tr._P. Next, in the NMOS transistor formation region Tr._N, a gate insulating film 102 and a gate electrode 103 are sequentially formed on the upper surface of the semiconductor substrate 100, and in the PMOS transistor formation region Tr._P, gate insulation is formed on the upper surface of the semiconductor substrate 100. A film 102 and a gate electrode 203 are formed in this order.

  In the step shown in FIG. 6B, first, plasma oxidation is performed to oxidize exposed portions of the upper surface of the substrate and the surfaces of the gate electrodes 103 and 203. Thereby, for example, an oxide film 304 having a thickness of 5 nm is formed. Next, an n-type extension region 105 is formed in the semiconductor substrate 100 in the NMOS transistor formation region Tr._N and a p-type extension region 205 is formed in the semiconductor substrate 100 in the PMOS transistor formation region Tr._P by ion implantation. To do.

  In the step shown in FIG. 6C, first, a SiN film is provided on the upper surface of the semiconductor substrate 100, and then dry etching is performed on the SiN film. As a result, the sidewall 107 is formed so as to cover portions of the oxide film 304 formed on the side surfaces of the gate electrodes 103 and 203. Thereafter, an n-type source / drain region 108 is formed in the semiconductor substrate 100 in the NMOS transistor formation region Tr._N by an ion implantation method and an activation annealing method, and p is formed in the semiconductor substrate 100 in the PMOS transistor formation region Tr._P. A type source / drain region 208 is formed.

  In the step shown in FIG. 6D, first, the oxide film 304 is dry etched using the sidewall 107 as a mask. As a result, the oxide film 304 remains only between the side surfaces of the gate electrodes 103 and 203 and the side wall 107 and between the side wall 107 and the semiconductor substrate 100. Here, portions of the oxide film 304 provided on the side surfaces of the gate electrodes 103 and 203 have substantially the same function as the offset sidewall 104 in the first embodiment. Thereafter, the portion where the oxide film 304 has been removed is silicided to form a silicide layer 109.

In the step shown in FIG. 7A, as in the step shown in FIG. 5A, an SiO ₂ film is provided on the upper surface of the semiconductor substrate 100 so as to cover the gate electrodes 103 and 203 and the sidewall 107, and thereafter to etch the SiO ₂ film so as to leave only the portion provided on the PMOS transistor forming region Tr._P of SiO ₂ film. Thereby, the mask 212 can be formed in the PMOS transistor formation region Tr._P.

  In the step shown in FIG. 7B, the sidewall 107 is etched as in the step shown in FIG. By this etching, the sidewall 107 is etched to become the sidewall 110 in the NMOS transistor formation region Tr._N. On the other hand, in the PMOS transistor formation region Tr._P, the sidewall 107 is covered with the mask 212 and is not etched. Thereafter, the mask 212 is removed.

  In the step shown in FIG. 7C, as in the step shown in FIG. 2E, the stress liner film 111 is provided on the upper surface of the semiconductor substrate 100 so as to cover the gate electrodes 103 and 203.

  The structure of the semiconductor device manufactured using the above method is very similar to the structure of the semiconductor device in the second embodiment, but in the second embodiment, the offset sidewall 104 and the sidewall 107 or the side The side wall 106 having a substantially L-shaped cross section is provided between the wall 110 and the side wall 106 having a substantially L-shaped cross section is not provided in the present embodiment. Therefore, the sidewall 107 or 110 is provided on the oxide film 304.

  As described above, even if the semiconductor device does not include the sidewall having the L-shaped cross section, the semiconductor device according to the present embodiment has substantially the same effect as the semiconductor device according to the second embodiment. . Specifically, in the NMOS transistor, even if the thickness of the stress liner film 111 is 25 nm or more, when the stress liner film 111 is formed, the direction of the tensile force when the stress liner film is pulled in the lateral direction and the stress liner film are increased. The angle formed by the direction of the tensile force when pulled in the direction is greater than 90 degrees. Therefore, the stress liner film 111 can be made thick without causing film cracking of the stress liner film 111. In the PMOS transistor, the tensile stress applied from the stress liner film 111 to the channel region can be suppressed. Thereby, in this embodiment, the carrier mobility in the channel region of the semiconductor device can be improved.

  Furthermore, in this embodiment, since the oxide film 304 formed by oxidation of the gate electrodes 103 and 203 is used as an offset sidewall, film peeling of the offset sidewall due to stress application can be suppressed.

  As described above, the present invention is useful for a method of manufacturing a semiconductor device including a MOS transistor having a liner SiN film having a film stress and a gate width of about 40 nm or less.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor device concerning the 1st Embodiment of this invention. Sectional drawing which shows the structure of the semiconductor device concerning the 2nd Embodiment of this invention. Sectional drawing which shows the first half part of the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. Sectional drawing which shows the latter half part of the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. Sectional drawing which shows the first half part of the manufacturing method of the semiconductor device concerning the 3rd Embodiment of this invention. Sectional drawing which shows the second half part of the manufacturing method of the semiconductor device concerning the 3rd Embodiment of this invention.

Explanation of symbols

100 Semiconductor substrate
101 Shallow trench
102 Gate insulation film
103 Gate electrode
104 Offset sidewall
105 n-type extension region
106 sidewall
107 sidewall
108 n-type source / drain regions
109 Silicide layer
110 sidewall
111 Stress liner film
203 Gate electrode
205 p-type extension region
208 p-type source / drain regions
212 Mask
304 Oxide film

Claims (8)

With NMOS transistors,
The NMOS transistor is
An n-type source region and an n-type drain region that are spaced apart from each other in a semiconductor substrate;
A gate electrode provided on a channel region sandwiched between the n-type source region and the n-type drain region of the semiconductor substrate via a gate insulating film;
An offset sidewall provided on a side surface of the gate electrode;
A sidewall made of a SiN film, provided on the upper surface of the semiconductor substrate so as to cover a part of a side surface of the offset sidewall;
A stress liner film provided on the upper surface of the semiconductor substrate so as to cover the gate electrode and the sidewall, and having a tensile stress of 1.7 GPa or more;
The height of the sidewall is 1/3 or less of the height of the gate electrode,
The width of the sidewall on the upper surface of the semiconductor substrate is equal to or less than the distance between the gate electrode and the n-type source region or the n-type drain region,
The semiconductor device, wherein the stress liner film has a thickness of 25 nm or more. The semiconductor device according to claim 1,
In the semiconductor substrate, an isolation region for separating the NMOS transistor and the PMOS transistor is provided,
The PMOS transistor is
A p-type source region and a p-type drain region that are spaced apart from each other in the semiconductor substrate;
A gate electrode provided on a channel region sandwiched between the p-type source region and the p-type drain region of the semiconductor substrate via a gate insulating film;
An offset sidewall provided on a side surface of the gate electrode;
Provided on a side surface of the offset sidewall, and a sidewall made of a SiN film;
A stress liner film provided on the upper surface of the semiconductor substrate so as to cover the gate electrode and the sidewall, and having a tensile stress of 1.7 GPa or more;
The height of the sidewall is substantially the same as the height of the gate electrode,
The semiconductor device, wherein the stress liner film has a thickness of 25 nm or more. The semiconductor device according to claim 1 or 2,
The offset sidewall is a semiconductor device formed by oxidizing the gate electrode. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein a second sidewall having an L-shaped cross section is provided between a side surface of the offset sidewall and between the upper surface of the semiconductor substrate and the sidewall. A method of manufacturing a semiconductor device having an NMOS transistor,
A step of sequentially providing a gate insulating film and a gate electrode on the upper surface of the semiconductor substrate;
Providing an offset sidewall on the side surface of the gate electrode;
Providing a sidewall made of a SiN film on the upper surface of the semiconductor substrate so as to cover a part of a side surface of the offset sidewall;
Forming an n-type source region and an n-type drain region in the semiconductor substrate by ion implantation after providing the sidewall; and
Providing a stress liner film having a tensile stress of 1.7 GPa or more on the upper surface of the semiconductor substrate so as to cover the gate electrode and the sidewall,
In the step of providing the sidewall, the height of the sidewall is set to 1/3 or less of the height of the gate electrode, and the width of the sidewall on the upper surface of the semiconductor substrate is set to the gate electrode and the n-type. The distance between the source region or the n-type drain region is less than or equal to
A method of manufacturing a semiconductor device, wherein, in the step of providing the stress liner film, the thickness of the stress liner film is 25 nm or more. A method of manufacturing a semiconductor device having an NMOS transistor and a PMOS transistor,
Providing a separation region for separating the PMOS transistor formation region and the NMOS transistor formation region in the semiconductor substrate;
A step of sequentially providing a gate insulating film and a gate electrode in the PMOS transistor formation region and the NMOS transistor formation region in the upper surface of the semiconductor substrate;
Providing an offset sidewall on each side surface of the gate electrode;
Providing a sidewall made of a SiN film on the top surface of the semiconductor substrate so as to cover a side surface of the offset sidewall; and
After providing the sidewall, a p-type source region and a p-type drain region are formed in the PMOS transistor formation region in the semiconductor substrate by an ion implantation method, and an n-type source region and an n-type region are formed in the NMOS transistor formation region. Forming a mold drain region;
Providing a stress liner film having a tensile stress of 1.7 GPa or more on the upper surface of the semiconductor substrate, so as to cover the gate electrode and the sidewall,
In the step of providing the sidewall, in the NMOS transistor formation region, the height of the sidewall is set to 1/3 or less of the height of the gate electrode, while in the PMOS transistor formation region, the height of the sidewall is set. Is substantially the same as the height of the gate electrode,
The method of manufacturing a semiconductor device, wherein in the step of providing the stress liner film, the thickness of the stress liner film is 25 nm or more. In the manufacturing method of the semiconductor device according to claim 5 or 6,
A method of manufacturing a semiconductor device, wherein, in the step of forming the offset sidewall, the sidewall of the gate electrode is oxidized. In the manufacturing method of the semiconductor device according to any one of claims 5 to 7,
After providing the offset sidewall, the second sidewall covers the side surface of the offset sidewall and the upper surface of the semiconductor substrate,
A method of manufacturing a semiconductor device, wherein the sidewall is provided on the second sidewall after the second sidewall is provided.

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