JP2008130963A - Semiconductor device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve current characteristics or to prevent the current characteristics from degrading without making its manufacturing process more complex in a semiconductor device comprising a stress applying insulating film on the top surface of a gate electrode of a MOS type transistor element. <P>SOLUTION: The semiconductor device, in which two kinds of MOS type transistor elements, that is a P-channel type MOS transistor 118 and an N-channel type MOS transistor 119, are formed in an identical chip, having a stress applying insulating film 112 having either of tensile stress or compression stress on the top surface of a gate electrode 106 of the MOS type transistor element formed in a predetermined region on a semiconductor substrate 101, wherein the semiconductor device is configured so that the film thickness of a sidewall insulating film 109 of the MOS type transistor element in which the current characteristics are lowered by the stress applying insulating film 112 is greater than the film thickness of the sidewall insulating film 109 of the MOS type transistor element in which the current characteristics improve by the stress applying insulting film 112. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, a side wall insulating film (hereinafter referred to as a side wall as appropriate) on a side wall of a gate electrode, and a stress applying insulating film having a stress having a predetermined attribute on the gate electrode. The present invention relates to a semiconductor device provided and a manufacturing method thereof.

  In recent years, with miniaturization of semiconductor devices, demands for on-current of CMOS (complementary MOS transistor elements) have become more severe, and it has become difficult to meet the demands of conventional semiconductor device structures. . Therefore, on-current improvement techniques represented by the use of high mobility materials, surface orientation control of Si substrates, strain application techniques, and the like have been proposed. In particular, as a strain application technique, a buried SiGe source / drain technique in which stress from the source / drain on both sides of the gate electrode is applied to the channel portion, or a stress applying insulating film having a high tensile stress or compressive stress (hereinafter, referred to as a stress application insulating film) A technique has been proposed in which a contact etching stopper film is appropriately formed on the gate electrode and stress is applied to the channel portion.

  Here, FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device in a technique in which a stress applying insulating film having high tensile stress or compressive stress is formed on a gate electrode and stress is applied to a channel portion. In this semiconductor device, a P-channel MOS transistor 518 is formed in a PMOS region (N-type well) 503 on a silicon substrate 501, and an N-channel MOS transistor 519 is formed in an NMOS region (P-type well) 504. The P channel type MOS transistor 518 and the N channel type MOS transistor 519 are arranged via an element isolation region 502. The MOS transistor element includes a gate electrode 506 formed on a silicon substrate 501 via a gate oxide film 505, source / drain regions 507 formed on both sides of a channel portion formed below the gate electrode 506, and A side wall 509 is formed on the side wall of the gate electrode 506 with a silicon oxide film 508 interposed therebetween. This semiconductor device further includes a contact etching stopper film 513 formed so as to cover two types of MOS transistor elements, an interlayer insulating film 514 formed above the MOS transistor elements, a gate electrode 506, or source / drain regions. The contact hole 515 connecting the metal wiring 516 and the passivation film 517 is provided.

  In this semiconductor device, when a silicon nitride film having tensile stress is formed on the gate electrode as the stress application insulating film, the tensile stress is applied to the channel portion through the gate electrode. The on-current is improved. This is because the tensile stress of the silicon nitride film formed on the gate electrode widens the distance between Si lattices in the channel portion of the N-channel MOS transistor and improves the mobility of electrons. However, the on-current of the P-channel MOS transistor decreases. This is because the tensile stress of the insulating film formed on the gate electrode widens the distance between the Si lattices of the channel portion of the P-channel MOS transistor and decreases the mobility of holes.

  On the other hand, when a silicon nitride film having compressive stress is formed on the gate electrode as the stress applying insulating film, the compressive stress is applied to the channel portion through the gate electrode. The on-current is improved. This is because the compressive stress of the silicon nitride film formed on the gate electrode reduces the distance between the Si lattices in the channel portion of the P-channel MOS transistor and improves the hole mobility. However, the on-current of the N-channel MOS transistor decreases. This is because the compressive stress of the insulating film formed on the gate electrode shortens the distance between the Si lattices in the channel portion of the N-channel MOS transistor and decreases the mobility of electrons.

  Therefore, as a technique for improving the on-current of both the N-channel MOS transistor and the P-channel MOS transistor, an insulating film having a tensile stress is formed on the upper surface of the gate electrode of the N-channel MOS transistor, and the P-channel type There is a technique for forming an insulating film having a compressive stress on the upper surface of the gate electrode of the MOS transistor (for example, see Non-Patent Document 1).

S. Pidin et al., “A novel strain enhanced CMOS architecture using selective developed high tensil and high compressive silicon nitride films,” EDDM, pp. 213-16.

  However, in the technique described in Non-Patent Document 1, a stress applying insulating film having a stress that improves current characteristics is formed in each of the two types of MOS transistor elements. A lot of complexity. Furthermore, processing accuracy is required at the boundary between the NMOS region for forming the N-channel MOS transistor and the PMOS region for forming the P-channel MOS transistor, which is not suitable for mass production.

  On the other hand, when only one type of stress application insulating film is formed, the manufacturing process can be prevented from becoming many and complicated, but the same stress is applied to any channel portion of the two types of MOS transistor elements. Therefore, as described above, only the on-current of one of the N-channel MOS transistor and the P-channel MOS transistor can be improved, and the other MOS transistor can be improved. The on-state current of the transistor element is reduced.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a current characteristic of a semiconductor device having a stress applying insulating film on the upper surface of a gate electrode of a MOS transistor element without complicating the manufacturing process. The object is to provide a semiconductor device capable of improving or preventing deterioration of current characteristics. Another object is to provide a specific method for manufacturing the semiconductor device.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which two types of MOS transistor elements, a P-channel MOS transistor and an N-channel MOS transistor, are formed in the same chip. A stress applying insulating film having either a tensile stress or a compressive stress is provided on the upper surface of the gate electrode of the MOS transistor element formed in the predetermined region above, and current characteristics are provided by the stress applying insulating film. The film thickness of the side wall insulating film formed on the side wall of the gate electrode of the MOS type transistor element is reduced on the side wall of the gate electrode of the MOS type transistor element whose current characteristics are improved by the stress applying insulating film. The first characteristic is that the thickness is set to be larger than the thickness of the sidewall insulating film.

  The semiconductor device according to the present invention having the above characteristics is characterized in that the stress of the stress applying insulating film is 0.1 GPa to 3.0 GPa.

  The semiconductor device according to the present invention having any one of the above characteristics is characterized in that the thickness of the stress applying insulating film is 30 nm to 100 nm.

  In the semiconductor device according to the first to third aspects of the present invention, the stress is a tensile stress, and the thickness of the sidewall insulating film of the P-channel MOS transistor is equal to that of the N-channel MOS transistor. A fourth feature is that the thickness is set to be larger than the thickness of the sidewall insulating film.

  In the semiconductor device according to the first to third aspects of the present invention, the stress is a compressive stress, and the thickness of the sidewall insulating film of the N-channel MOS transistor is equal to that of the P-channel MOS transistor. A fifth feature is that the thickness is set to be larger than the thickness of the sidewall insulating film.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device of the fourth feature, wherein the two types of MOS transistor elements in the predetermined region are manufactured. Forming a resist having a resist pattern in which an NMOS region for forming the N-channel MOS transistor located in the predetermined region is formed after forming a first sidewall insulating film on the sidewall of the gate electrode; Using the resist as a mask, a first sidewall insulating film removing step for removing the first sidewall insulating film in the NMOS region by chemical etching, a resist removing step for removing the resist, and nitriding the entire surface in the predetermined region A silicon nitride film forming step of forming a silicon film, and anisotropically etching the silicon nitride film, A second sidewall insulating film forming step of forming a second sidewall insulating film on the sidewall of the gate electrode of the N-channel MOS transistor and the sidewall of the first sidewall insulating film of the P-channel MOS transistor in the predetermined region; A stress applying insulating film forming step of forming the stress applying insulating film having a tensile stress so as to cover the two types of MOS transistor elements in the predetermined region is performed in order. And

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device of the fourth feature, wherein the two types of MOS transistor elements in the predetermined region are manufactured. A resist forming step of forming a resist having a resist pattern in which an NMOS region for forming the N-channel MOS transistor located in the predetermined region is formed after forming a sidewall insulating film on the sidewall of the gate electrode; A sidewall insulating film forming step of chemically etching the sidewall insulating film so as to reduce the film thickness of the sidewall insulating film of the N channel type MOS transistor in the NMOS region, and removing the resist to remove the resist And a tensile stress so as to cover the two types of MOS transistor elements in the predetermined region And the stress applying insulating film forming step of forming the stress applying insulating film having, that the run in sequence as a second feature.

  In the semiconductor device manufacturing method according to the first or second feature of the present invention, in the stress applying insulating film forming step, a silicon nitride film is formed as the stress applying insulating film by using plasma CVD or thermal CVD. This is a third feature.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device having the fifth feature, wherein the two types of MOS transistor elements in the predetermined region are manufactured. Forming a resist having a resist pattern in which a PMOS region for forming the P-channel MOS transistor located in the predetermined region is formed after forming a first sidewall insulating film on the sidewall of the gate electrode; Using the resist as a mask, a first sidewall insulating film removing step for removing the first sidewall insulating film in the PMOS region by chemical etching, a resist removing step for removing the resist, and nitriding the entire surface in the predetermined region A silicon nitride film forming step of forming a silicon film, and anisotropically etching the silicon nitride film, A second sidewall insulating film forming step of forming a second sidewall insulating film on the sidewall of the gate electrode of the P-channel MOS transistor and the sidewall of the first sidewall insulating film of the N-channel MOS transistor in the predetermined region; A stress applying insulating film forming step of forming the stress applying insulating film having compressive stress so as to cover the two types of MOS transistor elements in the predetermined region is performed in order. And

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device having the fifth feature, wherein the two types of MOS transistor elements in the predetermined region are manufactured. Forming a resist having a resist pattern in which a PMOS region for forming the P-channel MOS transistor located in the predetermined region is formed after forming a sidewall insulating film on the sidewall of the gate electrode; and A sidewall insulating film forming step of chemically etching the sidewall insulating film so as to reduce the film thickness of the sidewall insulating film of the P-channel MOS transistor in the PMOS region, and removing the resist to remove the resist A compressive stress so as to cover the two types of MOS transistor elements in the predetermined region. Wherein the stress applying insulating film stress applying insulating film forming step of forming a the a fifth feature to run in order that.

  In the method of manufacturing a semiconductor device according to the fourth or fifth aspect of the present invention, in the stress applying insulating film forming step, a silicon nitride film is formed as the stress applying insulating film by using plasma CVD. The sixth feature.

  According to the present invention, the side wall of the MOS transistor element whose current characteristics are lowered depending on whether the stress of the stress applying insulating film covering the two types of MOS transistor elements is a tensile stress or a compressive stress. The film thickness of each type of MOS transistor element is adjusted so that the film thickness of the insulating film (side wall) is larger than the film thickness of the side wall insulating film of the MOS transistor element that improves current characteristics. That is, in the semiconductor device according to the prior art, the thickness of the sidewall of each type of MOS transistor element is the same (i = j in FIG. 5), whereas in the semiconductor device according to the present invention, the current characteristics are reduced. By increasing the film thickness of the sidewall insulating film of the MOS transistor element, the transmission of stress to the channel portion can be attenuated, and the deterioration of power characteristics can be suppressed. Alternatively, in the semiconductor device according to the present invention, by reducing the film thickness of the sidewall insulating film of the MOS transistor element that improves the current characteristics, the stress can be transmitted to the channel portion and the power characteristics can be improved. Can do.

  Specifically, when the stress application insulating film (contact etching stopper film) has a tensile stress, the thickness of the sidewall of the P-channel MOS transistor is larger than the sidewall of the N-channel MOS transistor. adjust. As a result, the stress applied to the channel portion of the P-channel MOS transistor can be reduced, and the decrease in the current characteristics (ON current) of the P-channel MOS transistor due to the tensile stress can be suppressed. Alternatively, the stress applied to the channel portion of the N-channel MOS transistor can be effectively applied in a state where the stress applied to the channel portion of the P-channel MOS transistor is suppressed. Can be improved.

  Further, when the stress applying insulating film has compressive stress, the thickness of the sidewall of the N-channel MOS transistor is adjusted to be thicker than that of the P-channel MOS transistor. As a result, the stress applied to the channel portion of the N-channel MOS transistor can be reduced, and a decrease in on-current of the N-channel MOS transistor due to compressive stress can be suppressed. Alternatively, the stress applied to the channel portion of the P-channel MOS transistor can be effectively applied in a state where the stress applied to the channel portion of the N-channel MOS transistor is suppressed. Can be improved.

  When the stress of the stress application insulating film is less than 0.1 GPa, the stress applied to the channel portion is small and does not contribute to the improvement of the current characteristics of the MOS transistor element. There is a problem that a defect occurs in the application insulating film itself and stress cannot be applied to the channel portion. Therefore, as in the present invention, by configuring the semiconductor device so that the stress of the stress applying insulating film is 0.1 GPa to 3.0 GPa, the current characteristics of the MOS transistor element can be improved more reliably. become.

  Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention (hereinafter, abbreviated as “device of the present invention” and “method of the present invention” as appropriate) will be described below with reference to the drawings. In addition, a well-known means is used about the part which is not explained in full detail in a manufacturing process. The materials, chemicals, ratios, operating conditions, and the like shown in the following examples can be appropriately changed without departing from the present invention, and the scope of the present invention is not limited to the following examples.

  The device of the present invention is a semiconductor device in which two types of MOS transistor elements, a P-channel MOS transistor and an N-channel MOS transistor, are formed in the same chip, and is a MOS type formed in a predetermined region on a semiconductor substrate. A side wall of the gate electrode of the MOS transistor element having a stress applying insulating film having a tensile stress or a compressive stress on the upper surface of the gate electrode of the transistor element, and current characteristics are lowered by the stress applying insulating film The thickness of the sidewall insulating film formed on the gate electrode is larger than the thickness of the sidewall insulating film formed on the sidewall of the gate electrode of the MOS transistor element whose current characteristics are improved by the stress applying insulating film. Yes.

<First Embodiment>
A first embodiment of the device of the present invention will be described with reference to FIGS.

  First, the configuration of the device of the present invention according to this embodiment will be described with reference to FIG. Here, FIG. 1 schematically shows a cross-sectional structure of the device of the present invention in the present embodiment. As shown in FIG. 1, the device according to the present invention includes a P channel type MOS transistor 118 in a PMOS region (N type well) 103 on a silicon substrate 101 and an N channel type MOS transistor in an NMOS region (P type well) 104. 119 is formed, and the P-channel MOS transistor 118 and the N-channel MOS transistor 119 are arranged via the element isolation region 102. The MOS transistor element includes a gate electrode 106 formed on a silicon substrate 101 via a gate oxide film 105, source / drain regions 107 formed on both sides of a channel portion formed below the gate electrode 106, and A side wall insulating film (side wall 109 and side wall 111a) formed via a silicon oxide film 108 is provided on the side wall of the gate electrode 106. The device of the present invention further includes a contact etching stopper film 112 (corresponding to a stress applying insulating film) formed so as to cover two types of MOS transistor elements, and an interlayer insulating film 114 formed on the upper part of the MOS transistor elements. A contact hole 115 for connecting the gate electrode 106 or the source / drain region 107 and the metal wiring 116, and a passivation film 117.

  In the present embodiment, the case where the contact etching stopper film 112 is a silicon nitride film having a tensile stress will be described. Furthermore, the device according to the present embodiment of the present invention has a sidewall insulating film (side wall 109 and sidewall 111a) of the P channel type MOS transistor 118 based on the film thickness a of the side wall insulating film (side wall 111a) of the N channel type MOS transistor 119. ) Is set to be thicker (a <b).

  Next, the method of the present invention of this embodiment will be described with reference to FIG. Here, FIG. 2 schematically shows a cross-sectional structure of the device of the present invention in each step of the method of the present invention in the present embodiment.

First, before executing the method of the present invention, as shown in FIG. 2A, the sidewalls of the gate electrodes 106 of two types of MOS transistor elements in a predetermined region on the silicon substrate 101 are formed by a known CMOS transistor manufacturing method. Steps until the side wall 109 (corresponding to the first side wall insulating film) is formed are performed. Here, the sidewall 109 is formed by using, for example, LPCVD (Low Pressure Chemical Vapor Deposition), using SiH ₂ Cl ₂ gas and NH ₃ gas, setting the temperature condition to 700 to 800 ° C., and having a film thickness of 50 nm. A silicon nitride film is deposited so that Further, the deposited silicon nitride film is anisotropically etched using a C _X H _Y F _Z gas, Ar gas, and O ₂ gas by a magnetron RIE (Reactive Ion Etching) apparatus to form a sidewall 109. _{Incidentally,} C _X H Y _{F Z} gas X 1-2 integer, Y is an integer of from 0 to 3, Z is an integer from 1 to 8.

Subsequently, as shown in FIG. 2B, a resist 110 having a resist pattern in which the NMOS region 104 is opened is formed (corresponding to a resist formation step), and the sidewalls in the NMOS region 104 are formed using the resist 110 as a mask. 109 is removed by chemical etching (corresponding to a first sidewall insulating film removing step). More specifically, after the resist 110 is formed, chemical dry etching is performed using C _X F _Z gas and N ₂ gas to remove only the sidewall 109 in the NMOS region 104.

Subsequently, as shown in FIG. 2C, the resist is removed by an ashing device (corresponding to a resist removing step), and a silicon nitride film is formed on the entire surface in a predetermined region (silicon nitride film forming step). Specifically, after removing the resist, for example, by LPCVD, using SiH ₂ Cl ₂ gas and NH ₃ gas, setting the temperature condition to 700 to 800 ° C., and the silicon nitride film 111 so that the film thickness becomes 50 nm. To deposit.

Subsequently, as shown in FIG. 2D, the silicon nitride film 111 is anisotropically etched to form a sidewall of the gate electrode 106 of the N-channel MOS transistor 119 in the predetermined region and the P-channel MOS transistor in the predetermined region. A sidewall 111a (corresponding to a second sidewall insulating film) is formed on the sidewall of the sidewall 109 (corresponding to a second sidewall insulating film forming step). More specifically, the silicon nitride film 111 is anisotropically etched using a C _X H _{Y FW} gas, an Ar gas, and an O ₂ gas by a magnetron RIE apparatus to form the sidewall 111a. In addition, W is an integer of 1-6. As a result, the thickness of the sidewall insulating film of the P-channel MOS transistor 118 is the combined thickness of the sidewall 109 and the sidewall 111a, and the thickness of the sidewall insulating film of the N-channel MOS transistor 119 is the sidewall 111a. It becomes the thickness of. Therefore, the thickness of the sidewall insulating film of the P-channel MOS transistor 118 is larger than the thickness of the sidewall insulating film of the N-channel MOS transistor 119.

Subsequently, as shown in FIG. 2E, a contact etching stopper film 112 having a tensile stress is formed so as to cover two types of MOS transistor elements in a predetermined region (corresponding to a stress applying insulating film forming step). ). Specifically, in order to relieve the compressive stress of the silicon oxide-based interlayer insulating film 114 formed in a later process, for example, LPCVD (corresponding to thermal CVD) and HCD (Hexa-chloro-disilane) gas and Using a NH ₃ gas, the temperature condition is set to 400 to 500 ° C., a silicon nitride film is deposited so as to have a film thickness of 50 nm, and a contact etching stopper film 112 is formed. In this case, the contact etching stopper film 112 has a tensile stress of 0.1 GPa to 1.5 GPa. The film thickness of the contact etching stopper film 112 is appropriately set in the range of 30 nm to 100 nm according to the process, transistor size, and the like.

  After the execution of the method of the present invention, the interlayer insulating film 114, the contact hole 115, the metal wiring 116, and the passivation film 117 are formed by a known CMOS transistor manufacturing method. In this way, by increasing the thickness of the sidewall insulating film of the P-channel MOS transistor 118 whose current characteristics are degraded by the stress application insulating film 112 having tensile stress, the current characteristics of the N-channel MOS transistor 119 are stressed. While improving by the application insulating film 112, in the P-channel MOS transistor 118, the transmission of stress can be suppressed and the deterioration of the current characteristics can be suppressed.

Second Embodiment
A second embodiment of the device of the present invention will be described with reference to FIGS. In the present embodiment, a case will be described in which the side wall forming method of each MOS transistor element is different from that of the first embodiment.

  First, the configuration of the inventive device of the present embodiment will be described. Here, FIG. 3 schematically shows a cross-sectional structure of the device of the present invention in the present embodiment. As shown in FIG. 3, the device of the present invention includes a P-channel MOS transistor 218 in a PMOS region (N-type well) 203 on a silicon substrate 201 and an N-channel MOS transistor in an NMOS region (P-type well) 204. 219 is formed, and the P-channel MOS transistor 218 and the N-channel MOS transistor 219 are arranged via the element isolation region 202. The MOS transistor element includes a gate electrode 206 formed on a silicon substrate 201 via a gate oxide film 205, a source / drain region 207 formed on both sides of a channel portion formed below the gate electrode 206, and A side wall insulating film (side wall 209 or side wall 209 ′) formed through a silicon oxide film 208 is provided on the side wall of the gate electrode 206. The device of the present invention further includes a contact etching stopper film 212 (corresponding to a stress applying insulating film) formed so as to cover two types of MOS transistor elements, and an interlayer insulating film 214 formed on the upper part of the MOS transistor elements. , A contact hole 215 connecting the gate electrode 206 or the source / drain region 207 and the metal wiring 216, and a passivation film 217.

  The device of the present invention of this embodiment is a silicon nitride film in which the contact etching stopper film 212 has a tensile stress. From the film thickness c of the side wall insulating film (side wall 209 ′) of the N channel type MOS transistor 219, the P channel type is obtained. The thickness d of the sidewall insulating film (side wall 209) of the MOS transistor 218 is set to be thicker (c <d).

  Next, the method of the present invention of this embodiment will be described with reference to FIG. Here, FIG. 4 schematically shows a cross-sectional structure of the device of the present invention in each step of the method of the present invention in the present embodiment.

  First, before executing the method of the present invention, as shown in FIG. 4A, a sidewall 209 is formed on the side wall of the gate electrode 206 of two types of MOS transistor elements in a predetermined region by a known CMOS transistor manufacturing method. The process up to forming is executed. The method for forming the sidewall 209 is the same as the method for forming the sidewall 109 in the first embodiment.

Subsequently, as shown in FIG. 4B, a resist 210 having a resist pattern in which the NMOS region 204 is opened (corresponding to a resist forming step) is formed, and the sidewalls in the NMOS region 204 are formed using the resist 210 as a mask. The sidewall 209 is chemically etched so as to reduce the film thickness 209 (corresponding to a sidewall insulating film forming step). More specifically, after forming the resist 210, chemical dry etching is performed using C _X F _Z gas and N ₂ gas, and the sidewall 209 in the NMOS region 204 is etched by 25 nm to form a sidewall 209 ′. . As a result, the thickness of the sidewall insulating film of the P-channel MOS transistor 218 becomes the thickness of the sidewall 209, and the thickness of the sidewall insulating film of the N-channel MOS transistor 219 becomes the thickness of the sidewall 209 ′. Since the thickness of the sidewall 209 is larger than that of the sidewall 209 ′, the thickness of the sidewall insulating film of the P-channel MOS transistor 218 is larger than the thickness of the sidewall insulating film of the N-channel MOS transistor 219. Become thicker.

Subsequently, as shown in FIG. 4C, the resist 210 is removed (corresponding to a resist removing step), and a contact etching stopper film 212 having a tensile stress is formed so as to cover two types of MOS transistor elements in a predetermined region. (Corresponding to a stress applying insulating film forming step). Specifically, in order to relieve the compressive stress of the silicon oxide film-based interlayer insulating film 214 formed in a later step, for example, LPCVD is used to set the temperature condition to 400 to 500 using HCD gas and NH ₃ gas. A silicon nitride film is deposited to a temperature of 50 nm and a contact etching stopper film 212 is formed. In this case, the contact etching stopper film 212 has a tensile stress of 0.1 GPa to 1.5 GPa. The film thickness of the contact etching stopper film 212 is appropriately set in the range of 30 nm to 100 nm according to the process, transistor size, and the like.

  After the execution of the method of the present invention, the interlayer insulating film 214, the contact 215, the metal wiring 216, and the passivation film 217 are formed by a known CMOS transistor manufacturing method. As described above, by thinning the sidewall insulating film of the N-channel MOS transistor 219, it is possible to improve the transmission of stress and improve the current characteristics of the N-channel MOS transistor 219.

<Third Embodiment>
A third embodiment of the device of the present invention will be described with reference to FIGS. In the first and second embodiments, the case where the stress of the stress application insulating film is a tensile stress has been described. In the present embodiment, the case where the stress of the stress application insulating film is a compressive stress will be described. .

  First, the configuration of the device of the present invention of this embodiment will be described with reference to FIG. Here, FIG. 5 schematically shows a cross-sectional structure of the device of the present invention in the present embodiment. As shown in FIG. 5, the device of the present invention has a P-channel MOS transistor 318 in the PMOS region (N-type well) 303 on the silicon substrate 301 and an N-channel MOS transistor in the NMOS region (P-type well) 304. 319 is formed, and the P-channel MOS transistor 318 and the N-channel MOS transistor 319 are arranged via the element isolation region 302. The MOS transistor element includes a gate electrode 306 formed on a silicon substrate 301 via a gate oxide film 305, source / drain regions 307 formed on both sides of a channel portion formed below the gate electrode 306, and A side wall insulating film (side wall 309 and side wall 311a) formed through a silicon oxide film 308 is provided on the side wall of the gate electrode 306. The device according to the present invention further includes a contact etching stopper film 313 (corresponding to a stress applying insulating film) formed so as to cover two types of MOS transistor elements, and an interlayer insulating film 314 formed on the MOS transistor elements. , A contact hole 315 connecting the gate electrode 306 or the source / drain region 307 and the metal wiring 316, and a passivation film 317.

  In the device of the present invention of this embodiment, the contact etching stopper film 313 is a silicon nitride film having a compressive stress, and an N channel type MOS is determined from the film thickness f of the side wall insulating film (side wall 311a) of the P channel type MOS transistor 318. The film thickness e of the sidewall insulating film (side wall 309 and side wall 311a) of the transistor 319 is set to be thicker (f <e).

  Next, the method of the present invention of this embodiment will be described with reference to FIG. Here, FIG. 6 schematically shows a cross-sectional structure of the device of the present invention in each step of the method of the present invention in the present embodiment.

  First, before executing the method of the present invention, as shown in FIG. 6A, the sidewalls of the gate electrodes 306 of two types of MOS transistor elements in a predetermined region on the silicon substrate 301 are formed by a known CMOS transistor manufacturing method. Steps until the side wall 309 (corresponding to the first side wall insulating film) is formed are performed. The method for forming the sidewalls 309 is the same as the method for forming the sidewalls 109 and 209 in the first and second embodiments.

Subsequently, as shown in FIG. 6B, a resist 310 having a resist pattern in which the PMOS region 303 is opened is formed (corresponding to a resist formation step), and the sidewalls in the PMOS region 303 are formed using the resist 310 as a mask. 309 is removed by chemical etching (corresponding to a first sidewall insulating film removing step). More specifically, after the resist 310 is formed, chemical dry etching is performed using C _X F _Z gas and N ₂ gas to remove only the sidewall 309 in the PMOS region 303.

Subsequently, as shown in FIG. 6C, the resist is removed by an ashing device (corresponding to a resist removing process), and a silicon nitride film is formed on the entire surface in a predetermined region (corresponding to a silicon nitride film forming process). Specifically, after removing the resist, for example, by LPCVD, using a SiH ₂ Cl ₂ gas and an NH ₃ gas, the temperature condition is set to 700 to 800 ° C., and the silicon nitride film 311 has a thickness of 50 nm. To deposit.

Subsequently, as shown in FIG. 6D, the silicon nitride film 311 is anisotropically etched, and the sidewall of the gate electrode 306 of the P-channel MOS transistor 318 in the predetermined region and the N-channel MOS transistor 319 in the predetermined region. A side wall 311a is formed on the side wall of the side wall 309 (corresponding to the second side wall insulating film forming step). More specifically, the silicon nitride film 311 is anisotropically etched using C _X H _Y F _W gas, Ar gas, and O ₂ gas by a magnetron RIE apparatus to form a sidewall 311a. As a result, the thickness of the sidewall insulating film of the P-channel MOS transistor 318 is the thickness of the sidewall 311a, and the thickness of the sidewall insulating film of the N-channel MOS transistor 319 is the sum of the sidewall 309 and the sidewall 311a. Thickness. Therefore, the thickness of the sidewall insulating film of the N-channel MOS transistor 319 is larger than the thickness of the sidewall insulating film of the P-channel MOS transistor 318.

Subsequently, as shown in FIG. 6E, a contact etching stopper film 313 having compressive stress is formed so as to cover two types of MOS transistor elements in a predetermined region (corresponding to a stress applying insulating film forming step). ). Specifically, the contact etching stopper film 313 is formed of SiH ₄ by PECVD (Plasma Enhanced Chemical Vapor Deposition), for example, in order to relieve the compressive stress of the silicon oxide-based interlayer insulating film 314 formed in a later step. Using a gas and NH ₃ gas, the temperature condition is set to 400 to 500 ° C., and a silicon nitride film is deposited to have a film thickness of 50 nm. In this case, the contact etching stopper film 313 has a compressive stress of 0.1 GPa to 3.0 GPa. The film thickness of the contact etching stopper film 313 is appropriately set in the range of 30 nm to 100 nm according to the process, transistor size, and the like.

In LPCVD used in the first and second embodiments, only an insulating film having tensile stress can be formed. However, in PECVD used in this embodiment, an insulating film having tensile stress and compressive stress can be used depending on conditions. It is possible to form an insulating film having This is because, in principle, LPCVD (thermal LPCVD) includes Si ₃ N ₄ , Si—H, and NH as substances contained in the insulating film to be formed. As a result, the range of change of each content is narrowed. Furthermore, since Si ₃ N ₄ is predominantly formed due to the gas phase reaction, only an insulating film having a tensile stress can be formed. On the other hand, in PECVD, there are Si _X N _Y , Si-H, and NH as substances contained in the insulating film to be formed. wide. Furthermore, since any Si _X N _Y (X and Y are integers) can be formed without being limited to Si ₃ N ₄ , both an insulating film having a tensile stress and an insulating film having a compressive stress can be formed depending on conditions. It can be formed.

  After the execution of the method of the present invention, the interlayer insulating film 314, the contact 315, the metal wiring 316, and the passivation film 317 are formed by a known CMOS transistor manufacturing method. As described above, by increasing the thickness of the sidewall insulating film of the N-channel MOS transistor 319 whose current characteristics are deteriorated by the stress application insulating film 313 having compressive stress, the current characteristics of the P-channel MOS transistor 318 are changed to stress. While improving by the application insulating film 313, in the N-channel MOS transistor 319, the transmission of stress can be suppressed, and the deterioration of the current characteristics can be suppressed.

<Fourth embodiment>
A fourth embodiment of the device of the present invention will be described with reference to FIGS. In the present embodiment, a case will be described in which the side wall forming method of each MOS transistor element is different from that of the third embodiment.

  First, the configuration of the inventive device of the present embodiment will be described. Here, FIG. 7 schematically shows a cross-sectional structure of the device of the present invention in the present embodiment. As shown in FIG. 7, the device of the present invention includes a P-channel MOS transistor 418 in a PMOS region (N-type well) 403 on a silicon substrate 401 and an N-channel MOS transistor in an NMOS region (P-type well) 404. 419 is formed, and the P-channel MOS transistor 418 and the N-channel MOS transistor 419 are arranged via the element isolation region 402. The MOS transistor element includes a gate electrode 406 formed on a silicon substrate 401 via a gate oxide film 405, a source / drain region 407 formed on both sides of a channel portion formed below the gate electrode 406, and A side wall insulating film (side wall 409 or side wall 409 ′) formed through a silicon oxide film 408 is provided on the side wall of the gate electrode 406. The device of the present invention further includes a contact etching stopper film 413 (corresponding to a stress applying insulating film) formed so as to cover two types of MOS transistor elements, and an interlayer insulating film 414 formed above the MOS transistor elements. , A contact hole 415 for connecting the gate electrode 406 or the source / drain region 407 and the metal wiring 416, and a passivation film 417.

  In the device of the present invention of this embodiment, the contact etching stopper film 413 is a silicon nitride film having a compressive stress. From the film thickness h of the side wall insulating film (side wall 409 ′) of the P channel type MOS transistor 418, an N channel type is obtained. The film thickness g of the sidewall insulating film (sidewall 409) of the MOS transistor 419 is set to be thicker (h <g).

  Next, the method of the present invention of this embodiment will be described with reference to FIG. Here, FIG. 8 schematically shows a cross-sectional structure of the device of the present invention in each step of the method of the present invention in the present embodiment.

  First, before executing the method of the present invention, as shown in FIG. 8A, a sidewall 409 is formed on the side wall of the gate electrode 406 of two types of MOS transistor elements in a predetermined region by a known CMOS transistor manufacturing method. The process up to forming is executed. The method for forming the sidewall 409 is the same as the method for forming the sidewalls 109, 209, and 309 in the first to third embodiments.

Subsequently, as shown in FIG. 8B, a resist 410 having a resist pattern in which the PMOS region 403 is opened is formed (corresponding to a resist formation step), and the sidewalls in the PMOS region 403 are formed using the resist 410 as a mask. The sidewall 409 is chemically etched so as to reduce the film thickness of 409 (corresponding to a sidewall insulating film forming step). More specifically, after the resist 410 is formed, chemical dry etching is performed using C _X F _Z gas and N ₂ gas to etch the sidewall 409 in the NMOS region 404 by 25 nm to form a sidewall 409 ′. . As a result, the thickness of the sidewall insulating film of the P-channel MOS transistor 418 becomes the thickness of the sidewall 409 ′, and the thickness of the sidewall insulating film of the N-channel MOS transistor 419 becomes the thickness of the sidewall 409. Since the sidewall 409 is thicker than the sidewall 409 ′, the sidewall insulating film of the N-channel MOS transistor 419 is thicker than the sidewall insulating film of the P-channel MOS transistor 418. Become thicker.

Subsequently, as shown in FIG. 8C, the resist 410 is removed (corresponding to a resist removing step), and a contact etching stopper film 413 having a compressive stress so as to cover two types of MOS transistor elements in a predetermined region. (Corresponding to a stress applying insulating film forming step). Specifically, in order to relieve the compressive stress of the silicon oxide film-based interlayer insulating film 414 formed in a later step, the temperature condition is set to 400 to 400 by using SiH ₄ gas and NH ₃ gas by PECVD, for example. A silicon nitride film is deposited at a temperature of 500 ° C. so that the film thickness is 50 nm, and a contact etching stopper film 413 is formed. In this case, the contact etching stopper film 413 has a compressive stress of 0.1 GPa to 3.0 GPa. The film thickness of the contact etching stopper film 413 is appropriately set in the range of 30 nm to 100 nm according to the process, transistor size, and the like.

  After the execution of the present invention, the interlayer insulating film 414, the contact 415, the metal wiring formation 416, and the passivation film 417 are formed by a known CMOS transistor manufacturing method. Thus, by reducing the side wall insulating film of the P-channel MOS transistor 418, it is possible to improve the transmission of stress and improve the current characteristics of the P-channel MOS transistor 418.

<Another embodiment>
<1> In the first and second embodiments, the contact etching stopper films 112 and 212 as the stress application insulating films having a tensile stress are formed by LPCVD. However, the present invention is not limited to this.

For example, the silicon nitride film may be deposited by PECVD using SiH ₄ gas and NH ₃ gas, setting the temperature condition to 400 to 500 ° C., and having a film thickness of 50 nm. In this case, the contact etching stopper films 112 and 212 have a tensile stress of 0.1 GPa to 1.5 GPa.

Further, for example, by using SiH ₄ gas and NH ₃ gas by PECVD and setting the temperature condition to 400 to 500 ° C. and depositing a silicon nitride film, UV irradiation is performed and the temperature condition is set to 300 to 400 ° C. You may set and perform a modification process. In this case, the contact etching stopper films 112 and 212 have a tensile stress of 0.1 GPa to 3.0 GPa.

  <2> In each of the above-described embodiments, the thickness of the sidewall insulating film of the MOS transistor element in which the current characteristic is lowered in order to prevent or reduce the deterioration of the current characteristic in the first and third embodiments. In the fourth embodiment, the case where the sidewall insulating film of the MOS transistor element whose current characteristics are improved in order to further improve the current characteristics has been described. However, the first and second embodiments are combined, or the third and The fourth embodiment may be executed in combination.

Sectional drawing which shows schematic structure in 1st Embodiment of the semiconductor device which concerns on this invention. Process drawing which shows the cross section of the semiconductor device in each process of 1st Embodiment in the manufacturing method of the semiconductor device which concerns on this invention Sectional drawing which shows schematic structure in 2nd Embodiment of the semiconductor device which concerns on this invention. Process drawing which shows the cross section of the semiconductor device in each process of 2nd Embodiment in the manufacturing method of the semiconductor device which concerns on this invention Sectional drawing which shows schematic structure in 3rd Embodiment of the semiconductor device which concerns on this invention. Process drawing which shows the cross section of the semiconductor device in each process of 3rd Embodiment in the manufacturing method of the semiconductor device which concerns on this invention Sectional drawing which shows schematic structure in 4th Embodiment of the semiconductor device which concerns on this invention. Process drawing which shows the cross section of the semiconductor device in each process of 4th Embodiment in the manufacturing method of the semiconductor device which concerns on this invention Sectional drawing which shows schematic structure of the semiconductor device which concerns on a prior art

Explanation of symbols

101, 201, 301, 401, 501 Silicon substrates 102, 202, 302, 402, 502 Element isolation regions 103, 203, 303, 403, 503 PMOS regions 104, 204, 304, 404, 504 NMOS regions 105, 205, 305 , 405, 505 Gate oxide films 106, 206, 306, 406, 506 Gate electrodes 107, 207, 307, 407, 507 Source / drain regions 108, 208, 308, 408, 508 Silicon oxide films 109, 209, 309, 409 , 509 Side walls 110, 210, 310, 410, 510 Resist 111, 311 Silicon nitride film 111a, 311a Side walls 112, 212 Insulating film for applying tensile stress 313, 413 Insulating film for applying compressive stress 512 Film 114, 214, 314, 414, 514 Interlayer insulating film 115, 215, 315, 415, 515 Contact hole 116, 216, 316, 416, 516 Metal wiring 117, 217, 317, 417, 517 Passivation film 118, 218, 318, 418, 518 P-channel MOS transistors 119, 219, 319, 419, 519 N-channel MOS transistors

Claims (11)

A semiconductor device in which two types of MOS transistor elements, a P-channel MOS transistor and an N-channel MOS transistor, are formed in the same chip,
On the upper surface of the gate electrode of the MOS transistor element formed in a predetermined region on the semiconductor substrate, there is a stress applying insulating film having either a tensile stress or a compressive stress,
The MOS transistor in which the current characteristic is degraded by the stress application insulating film, and the current characteristic is improved by the stress application insulating film. A semiconductor device characterized in that it is set to be thicker than a film thickness of a sidewall insulating film formed on a sidewall of a gate electrode of the element.   The semiconductor device according to claim 1, wherein a stress of the stress application insulating film is 0.1 GPa to 3.0 GPa.   3. The semiconductor device according to claim 1, wherein the stress application insulating film has a thickness of 30 nm to 100 nm.   The stress is a tensile stress, and the thickness of the sidewall insulating film of the P-channel MOS transistor is set to be larger than the thickness of the sidewall insulating film of the N-channel MOS transistor. The semiconductor device according to claim 1.   The stress is a compressive stress, and the thickness of the sidewall insulating film of the N-channel MOS transistor is set to be larger than the thickness of the sidewall insulating film of the P-channel MOS transistor. The semiconductor device according to claim 1. A method of manufacturing a semiconductor device according to claim 4,
After forming the first sidewall insulating film on the sidewalls of the gate electrodes of the two types of MOS transistor elements in the predetermined region, an NMOS region for forming the N-channel MOS transistor located in the predetermined region is opened. A resist forming step of forming a resist having a resist pattern;
A first sidewall insulating film removing step of removing the first sidewall insulating film in the NMOS region by chemical etching using the resist as a mask;
A resist removing step for removing the resist;
A silicon nitride film forming step of forming a silicon nitride film on the entire surface in the predetermined region;
The silicon nitride film is anisotropically etched to form a sidewall on the sidewall of the gate electrode of the N-channel MOS transistor in the predetermined region and the sidewall of the first sidewall insulating film of the P-channel MOS transistor in the predetermined region. A second sidewall insulating film forming step of forming a two sidewall insulating film;
A stress applying insulating film forming step for sequentially forming the stress applying insulating film having a tensile stress so as to cover the two types of MOS transistor elements in the predetermined region. Device manufacturing method. A method of manufacturing a semiconductor device according to claim 4,
A resist in which an NMOS region for forming the N-channel MOS transistor located in the predetermined region is opened after a sidewall insulating film is formed on the side wall of the gate electrode of the two types of MOS transistor elements in the predetermined region. A resist forming step of forming a resist having a pattern;
A sidewall insulating film forming step of chemically etching the sidewall insulating film so as to reduce the film thickness of the sidewall insulating film of the N-channel MOS transistor in the NMOS region using the resist as a mask;
A resist removing step for removing the resist;
A stress applying insulating film forming step of forming the stress applying insulating film having a tensile stress so as to cover the two types of MOS transistor elements in the predetermined region. Device manufacturing method.   8. The method of manufacturing a semiconductor device according to claim 6, wherein, in the stress applying insulating film forming step, a silicon nitride film is formed as the stress applying insulating film by plasma CVD or thermal CVD. A method of manufacturing a semiconductor device according to claim 5,
After forming a first sidewall insulating film on the sidewalls of the gate electrodes of the two types of MOS transistor elements in the predetermined region, a PMOS region for forming the P-channel MOS transistor located in the predetermined region is opened. A resist forming step of forming a resist having a resist pattern;
A first sidewall insulating film removing step of removing the first sidewall insulating film in the PMOS region by chemical etching using the resist as a mask;
A resist removing step for removing the resist;
A silicon nitride film forming step of forming a silicon nitride film on the entire surface in the predetermined region;
The silicon nitride film is anisotropically etched to form a sidewall on the sidewall of the gate electrode of the P-channel MOS transistor in the predetermined region and the sidewall of the first sidewall insulating film of the N-channel MOS transistor in the predetermined region. A second sidewall insulating film forming step of forming a two sidewall insulating film;
A stress applying insulating film forming step of forming the stress applying insulating film having compressive stress so as to cover the two types of MOS transistor elements in the predetermined region. Device manufacturing method. A method of manufacturing a semiconductor device according to claim 5,
After forming a sidewall insulating film on the sidewalls of the gate electrodes of the two types of MOS transistor elements in the predetermined region, a resist in which a PMOS region for forming the P-channel MOS transistor located in the predetermined region is opened A resist forming step of forming a resist having a pattern;
A sidewall insulating film forming step of chemically etching the sidewall insulating film so as to reduce the film thickness of the sidewall insulating film of the P-channel MOS transistor in the PMOS region using the resist as a mask;
A resist removing step for removing the resist;
A stress applying insulating film forming step of forming the stress applying insulating film having compressive stress so as to cover the two types of MOS transistor elements in the predetermined region. Device manufacturing method.   11. The method of manufacturing a semiconductor device according to claim 9, wherein, in the stress applying insulating film forming step, a silicon nitride film is formed by plasma CVD as the stress applying insulating film.

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