JP2001093984A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small and high-reliability semiconductor device with a high-breakdown voltage MOS transistor and a low-voltage drive MOS transistor, and its manufacturing method. SOLUTION: LDD regions 114 and 124 are formed by forming a gate electrode 112 of a high-breakdown voltage MOS transistor 112 and a gate electrode 122 of a low-voltage drive MOS transistor and implanting impurities by using the gate electrodes 112 and 122 as masks. After that, an insulating film 202 is formed, in such a way that it covers the gate electrode 112. Then after forming an insulating film 203, sidewalls 123 ad thick sidewalls 113 are formed by an anisotropic etching of the insulating films 202 and 204. Then source-drain regions 115 and 125 are formed by implanting impurities using the sidewalls 113 and 123 as masks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a high breakdown voltage MOS transistor and a low voltage driving MOS transistor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Among semiconductor integrated circuits, a semiconductor device such as an LSI for driving a liquid crystal panel for driving a liquid crystal display device includes a general MOS type transistor operating at a low voltage of about several volts and a voltage of about several tens of volts. Of high-voltage MOS transistors to which the high voltage is applied at least temporarily. For example, an LSI for driving a liquid crystal panel is required to have a high output voltage in order to improve the image quality of the liquid crystal panel, and the withstand voltage of an internal circuit for output should be increased from 5 V to 10 V, and further to 20 V or more. Is required,
A logic circuit of 5 V or 3.3 V is required for operation control. Further, the liquid crystal panel driving LSI is usually used by being attached to the edge of the liquid crystal panel, and has an elongated shape and about 400 output terminals.

FIG. 5 is a sectional view showing an example of a conventional semiconductor device having a high breakdown voltage MOS transistor and a low voltage driving MOS transistor.

Referring to FIG. 5, a conventional semiconductor device includes a semiconductor substrate 1 having a well 1a, a high-voltage MOS transistor 2a and a low-voltage driving MOS transistor 2b formed on the semiconductor substrate 1, and a high-voltage MOS transistor 2b. Withstand voltage MOS transistor 2a and low voltage drive MOS transistor 2
b and a LOCOS film 2c formed to separate the LOCOS film from the LOCOS film b.

The high voltage MOS transistor 2a includes a gate insulating film 3a formed on the well 1a, a gate electrode 4a formed on the gate insulating film 3a, and a gate electrode 4a.
a, a resist 6a formed so as to cover the gate electrode 4a and the side wall 5a, and a gate electrode 4 in the well 1a.
LDD region 7a formed outside the position corresponding to a
And a high impurity concentration source / drain region 8a formed in the well 1a and outside the position corresponding to the resist 6a. On the other hand, the low voltage drive MOS type transistor 2b has a gate insulating film 3b formed on the well 1a.
And a gate electrode 4b formed on the gate insulating film 3b
A sidewall 5b formed on the side surface of the gate electrode 4b; an LDD region 7b formed outside the position corresponding to the gate electrode 5b in the well 1a;
a and a high impurity concentration source / drain region 8b formed outside the position corresponding to the side wall 5b.

The high breakdown voltage MOS type transistor 2a requires a horizontally long LDD region 7a to increase the breakdown voltage. Therefore, the high impurity concentration source / drain regions 8a
Is difficult to form in a self-aligned manner using the gate electrode 4a or the like as a mask. Conventionally, using a resist 6a as a mask, doping is performed at a position separated from the gate electrode 4a by an offset length L to obtain a high impurity concentration source.・
The drain region 8a was formed (the high voltage MOS transistor formed in this manner is called a mask offset high voltage MOS transistor).

On the other hand, in a semiconductor device such as an LSI for driving a liquid crystal panel, the size of the semiconductor device is required to be small in order to narrow the edge of the liquid crystal panel. It is necessary to.

[0008]

However, conventionally, a high impurity concentration source / source is used with the resist 6a as a mask.
Since the drain region 8a was formed, it was difficult to reduce the size of the high breakdown voltage MOS transistor due to a mask shift when the resist 6a was formed.

That is, in order to secure a certain breakdown voltage, it is necessary to secure a certain offset length L. However, considering that a mask shift occurs when forming the resist 6a, the required breakdown voltage is reduced. The mask length (for example, 0.3 μm) is added to the offset length L required to secure
m) must be determined in consideration of the offset length L. For this reason, the conventional semiconductor device in which the high impurity concentration source / drain regions are formed using the resist 6a has a problem that it is difficult to reduce the size. Further, in the conventional semiconductor device in which the offset length L is set in consideration of the mask shift, the offset length L becomes longer than originally required, so that the resistance of the LDD region increases and the current driving capability of the transistor decreases. I do. In order to compensate for this decrease in current driving capability, it is necessary to increase the channel width of the transistor, and there has been a problem that miniaturization becomes more difficult.

[0010] In order to solve the above problems, an object of the present invention is to provide a small and highly reliable semiconductor device having a high breakdown voltage MOS transistor and a low voltage driving MOS transistor, and a method of manufacturing the same. I do.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate, a high-voltage MOS transistor and a low-voltage driving MOS transistor formed on a part of the semiconductor substrate. A high withstand voltage MOS transistor, wherein the high withstand voltage MOS transistor includes a first gate electrode and a first gate electrode formed on a side surface of the first gate electrode.
And L formed in the semiconductor substrate.
A source region having a higher impurity concentration than a DD (Lightly Doped Drain) region and the LDD region;
A drain region, wherein the low-voltage-drive MOS transistor includes a second gate electrode, and a second sidewall formed on a side surface of the second gate electrode. The width (the distance between the side surface in contact with the gate electrode and the side surface facing the gate electrode among the side surfaces of the side wall) is larger than the width of the second side wall by 0.03 μm or more, and the LDD region is the first side wall.
The source / drain regions are formed by implanting impurities using the gate electrode of
Is formed by implanting impurities using the gate electrode and the first side wall as a mask. In the semiconductor device of the present invention, since the LDD region of the high breakdown voltage MOS transistor is formed using the gate electrode and the thick side wall as a mask, the offset gate length of the high breakdown voltage MOS transistor is always set to a substantially constant length. it can. Therefore, according to the semiconductor device of the present invention, a small and highly reliable semiconductor device including the high breakdown voltage MOS transistor and the low voltage driving MOS transistor can be obtained.

In the semiconductor device of the present invention, the LDD
It is preferable that a second LDD region having an impurity concentration higher than that of the LDD region is further provided outside the region (a side of the semiconductor substrate remote from a position corresponding to the gate electrode). With the above configuration, a high withstand voltage MOS with particularly high withstand voltage
A semiconductor device including the type transistor is obtained.

In the semiconductor device of the present invention, it is preferable that the width of the first side wall is not less than 0.04 μm and not more than 2 μm. With the above configuration, a semiconductor device including a high-breakdown-voltage MOS transistor having higher withstand voltage can be obtained.

In the method of manufacturing a semiconductor device according to the present invention, a semiconductor substrate and a high breakdown voltage M formed on a part of the semiconductor substrate are provided.
A method of manufacturing a semiconductor device comprising an OS transistor and a low voltage drive MOS transistor, comprising: forming a gate insulating film on a semiconductor substrate; and forming a first of the high breakdown voltage MOS transistor on the gate insulating film. Forming an LDD region by forming a first gate electrode and a second gate electrode of the low voltage drive MOS transistor, and implanting impurities using the first and second gate electrodes as a mask. Performing the second step;
A first sidewall disposed on the side surface of the second gate electrode, and a second sidewall disposed on the side surface of the second gate electrode, wherein the width of the first sidewall is the second side wall. A third step of forming the first and second gate electrodes and the first and second sidewalls as masks by forming a third step so as to be 0.03 μm or more larger than the width of the wall; Forming a source / drain region having an impurity concentration higher than that of the LDD region. In the manufacturing method of the present invention, since the LDD region of the high breakdown voltage MOS transistor is formed using the gate electrode and the thick side wall as a mask, the high breakdown voltage MOS transistor is formed.
The offset gate length of the S-type transistor can always be formed to be substantially constant. Therefore, according to the semiconductor device of the present invention, it is possible to manufacture a small and highly reliable semiconductor device including the high breakdown voltage MOS transistor and the low voltage driving MOS transistor. In particular, in the production method of the present invention,
Since the source / drain regions having a high impurity concentration of each of the high breakdown voltage MOS transistor and the low voltage driving MOS transistor can be simultaneously formed, manufacturing is easy.

In the above-mentioned manufacturing method, the third step is a step of forming a first insulating film so as to cover the first gate electrode, and the step of forming the second gate electrode and the first insulating film. It is preferable that the method includes a step of forming a second insulating film so as to cover and a step of anisotropically etching the first and second insulating films. With the above configuration, a semiconductor device including a high-voltage MOS transistor having a large width can be easily formed.

In the above manufacturing method, after the second step and before the third step, a side wall is formed on a side surface of the first gate electrode, and the first gate electrode and the side wall are formed. Forming a second LDD region having an impurity concentration higher than that of the LDD region by implanting an impurity as a mask, wherein in the third step, the first sidewall is formed by a side surface of the sidewall. Is further formed by forming an insulating film. According to the above configuration, LDD regions having different impurity concentrations can be formed, and a semiconductor device including a high withstand voltage MOS transistor having particularly high withstand voltage can be manufactured.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Embodiment 1 In Embodiment 1, an example of a semiconductor device of the present invention will be described. FIG. 1 is a cross-sectional view of the semiconductor device 100 according to the first embodiment. Note that, in FIG. 1, wiring of an Al alloy or the like formed on each transistor is omitted.

Referring to FIG. 1, a semiconductor device 100 includes a semiconductor substrate 102 having a well 101 (hatching is omitted), a high-breakdown-voltage MOS transistor 110 formed in a part of the semiconductor substrate 102, and a low-voltage drive. MOS
(Local) that separates the high-voltage MOS transistor 110 and the low-voltage drive MOS transistor 120 formed in the well 101 from the high-voltage MOS transistor 110.
oxidation of silicon) membrane 130
And

The high withstand voltage MOS transistor 110 has a gate insulating film 111 formed on the well 101, a gate electrode (first gate electrode) 112 formed on the gate insulating film 111, and a gate electrode 112 facing the gate electrode 112. Sidewalls (first sidewalls) 113 formed on two side surfaces to be formed, and a gate electrode 11 in the well 101.
LDD (Light) formed outside the portion corresponding to
a high impurity concentration source / drain region (hereinafter sometimes referred to as a high impurity concentration region) 115 formed outside the portion corresponding to the sidewall 113 in the well 101.

Low voltage drive MOS type transistor 120
Represents a gate insulating film 121 formed on the well 101
And the gate electrode 12 formed on the gate insulating film 121
2, sidewalls (second sidewalls) 123 formed on two opposing side surfaces of the gate electrode (second gate electrode) 122, and a portion inside the well 101 and outside a portion corresponding to the gate electrode 122. Region 124 formed in the well 101 and the side wall 1 in the well 101
And a high impurity concentration source / drain region (hereinafter, also referred to as a high impurity concentration region) 125 formed outside the portion corresponding to 23.

Gate insulating films 111 and 121 are made of, for example, SiO ₂ . Gate electrodes 112 and 12
2 is made of, for example, polysilicon or amorphous silicon. Note that a three-layer insulating film of silicon oxide film: silicon nitride film: silicon oxide film may be used as the gate insulating film 111 or 121 (the same applies to the following embodiments).

The sidewalls 113 and 123 are made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film. Side wall 1
13 has a width L1 (a distance between a side surface in contact with the gate electrode 112 and a side surface facing the gate electrode 112 among the side surfaces of the side wall 113) and a width L2 of the sidewall 123 (a distance in contact with the gate electrode 122 in the side surface of the side wall 123). 0.03μ from the distance between the side and the opposite side)
m or more. Also, the width L1 of the sidewall 113
Is preferably 0.04 μm or more and 2 μm or less.

The LDD regions 114 and 124 are regions having a low impurity concentration. LDD regions 114 and 124
The high-voltage MOS transistor 110 and the low-voltage driving MOS transistor 120 are either n-channel or p-
Depending on the channel, for example, phosphorus (P) or arsenic (A
s) and the like are doped. LDD region 1
14 and 124 are formed by implanting impurities using the gate electrodes 112 and 122 as masks, respectively.

The high impurity concentration regions 115 and 125 are
These are source / drain regions having a higher impurity concentration than the LDD regions 114 and 124. High impurity concentration region 115
As in the LDD regions 114 and 124, phosphorus and arsenic are also doped in the layers 125 and 125. The impurity concentration of high impurity concentration regions 115 and 125 is, for example, about 10 ²⁰ / cm ³ . Further, the high impurity concentration regions 115 and 125
In addition, it is formed by implanting impurities using the side wall 113, the gate electrode 122 and the side wall 123 as a mask.

From the side surface of the LDD region 114 on the gate electrode 112 side, the high impurity concentration region 11 on the gate electrode 112 side
5 to the side surface (high voltage MOS transistor 11
0 offset length) is the width L1 of the sidewall 113.
Is approximately equal to The LDD region 1 on the gate electrode 122 side
24 (offset length of the low-voltage drive MOS transistor 120) from the side surface of the gate electrode 122 to the side surface of the high impurity concentration region 125 on the side of the gate electrode 122.
3 is substantially equal to the width L2.

In the semiconductor device 100 of the first embodiment,
Since the LDD region 114 and the high-impurity-concentration region 115 can be formed in a self-alignment manner, unlike a conventional semiconductor device in which the amount of mask shift must be taken into consideration, the withstand voltage reliability is high even if the offset length L1 is set short. Withstand voltage MOS
A semiconductor device including the type transistor is obtained. Therefore, according to the semiconductor device 100, a small and highly reliable semiconductor device including the high breakdown voltage MOS transistor and the low voltage driving MOS transistor can be obtained.

The thickness of the gate insulating film 111 may be larger than that of the gate insulating film 121 in accordance with the withstand voltage specification required for the semiconductor device (semiconductor integrated circuit).

In the semiconductor device of the present invention, the LDD region may be formed by two or more regions. LD
Semiconductor device 100a when D region is composed of two regions
Is shown in FIG. Semiconductor device 10
0a differs from the semiconductor device 100 only in the high-breakdown-voltage MOS-type transistor, and thus redundant description is omitted.

Referring to FIG. 2, high voltage MOS type transistor 110a of semiconductor device 100a has a gate insulating film 111 formed on well 101 and a gate insulating film 11
1 and a gate electrode 112 formed on
2 sidewalls 1 formed on two opposing side surfaces
13a and an LDD region 114a formed in the well 101 and outside a portion corresponding to the gate electrode 112.
And a high impurity concentration region 115 formed in the well 101 and outside a portion corresponding to the sidewall 113.
And Here, the side wall 113a is a side wall 113b arranged from the gate electrode 112 side.
And 113c. Also, the LDD region 114a
The LDD region 114b disposed inside the well 101 and outside the portion corresponding to the gate electrode 112, and the LDD region 114c disposed inside the well 101 and outside the portion corresponding to the sidewall 113b are Prepare. That is, the LDD region 114a is
LDD regions 114b and 114c arranged from two sides
Is provided. The LDD region 114c is an LDD region 114b.
Than the impurity concentration.

Note that, similarly to the semiconductor device 100 of the first embodiment, the width L1 of the sidewall 113a is larger than the width L2 of the sidewall 123 by 0.03 μm or more.
The width L1 of the side wall 113a is 0.04 μm.
It is preferably from m to 2 μm.

The LDD region 114b is formed on the gate electrode 112
Is formed by implanting impurities using the mask as a mask. The LDD region 114c is formed by implanting impurities using the gate electrode 112 and the side wall 113b as a mask. The high impurity concentration region 115 is formed by implanting an impurity using the gate electrode 112 and the sidewall 113a as a mask.

In the semiconductor device 110a shown in FIG.
The D region 114a is an LDD region 11 having a different impurity concentration.
4b and the LDD region 114c, the impurity concentration profile of the LDD region can be changed stepwise in the horizontal direction (direction substantially parallel to the direction of movement of carriers in the channel), and a high withstand voltage which is particularly excellent in withstand voltage characteristics A semiconductor device including a MOS transistor is obtained.

Embodiment 2 In Embodiment 2, an example of a method for manufacturing a semiconductor device of the present invention will be described. According to the manufacturing method of the second embodiment, the semiconductor device 100 described in the first embodiment can be easily manufactured.

FIG. 3 schematically shows a process chart of the manufacturing method according to the second embodiment. In FIG. 3, the illustration of the semiconductor substrate other than the well 101 is omitted.

In the manufacturing method according to the second embodiment, first, FIG.
As shown in (a), the LOCOS film 130, the gate electrodes 112 and 122, the gate insulating film 201, and the LD
D regions 114 and 124 are formed. In particular,
First, LO on well 101 (hatching is omitted)
A COS film 130 is formed, and the gate insulating film 20
1. The gate electrodes 112 and 122 are formed. next,
Using the gate electrodes 112 and 122 as a mask, LDD implantation (impurity implantation) is performed in the self-aligned LDD region 1
14 and 124 are formed. Here, the gate insulating film 2
01 is to be the gate insulating films 111 and 121, for example, Si formed by a thermal oxidation method or the like.
O _{2 and the} like. Also, the gate electrodes 112 and 12
2 can be formed according to a conventional method.

Next, as shown in FIG.
02 is formed. The insulating film 202 is made of, for example, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film, and can be formed by a vapor deposition method (CVD method) or the like. The thickness of the insulating film 202 is preferably 0.03 μm or more, for example, 0.03 μm or more and 1 μm or less.

Next, as shown in FIG. 3C, the portion of the insulating film 202 where the low voltage drive MOS transistor 120 is to be formed is removed, and an insulating film 202 formed so as to cover the gate electrode 112 is obtained. Can be The partial removal of the insulating film 202 may be performed by forming a resist on the insulating film 202 in a region where the high-withstand-voltage MOS transistor 110 is formed, and isotropically etching the resist using the resist as a mask. Here, the range for forming the resist (the insulating film 20)
The range where 2 is left in principle) may be a range including the thickness of the insulating film 202 formed on the side wall of the gate electrode 112 in principle.・ Since the surface of the semiconductor substrate on which the drain is to be formed is easily damaged by etching,
It is desirable to cover up to the S film 130. By the above etching, the insulating film 202 formed on the side surface of the gate electrode 122 and the end of the LOCOS film 130 can be almost completely removed. At this time, the portion of the gate insulating film 201 where the gate electrode 122 is not formed is also etched, so that the gate insulating film 121 is formed.

Since it may take a relatively long time to remove the insulating film 202 by isotropic selective etching (dry etching), the etching selectivity is improved so that the LOCOS film 130 is not much etched. There is a need. Therefore, it is preferable to use a silicon nitride film or a silicon oxynitride film for the insulating film 202. When a silicon oxide film is used as the material of the insulating film 202, first, the insulating film 2 is formed with a hydrofluoric acid-based solution.
02, isotropically dry-etched after performing wet etching halfway through the LOCOS film 130.
Can be suppressed from being etched.

Next, as shown in FIG. 3D, an insulating film 203 is formed on the entire surface of the substrate so as to cover the gate electrode 122 and the insulating film 202. The insulating film 203 is, for example,
It is made of a silicon oxide film or the like and can be formed by a CVD method or the like. The thickness of the insulating film 203 is preferably 0.01 μm or more, for example, 0.01 μm or more and 2 μm or less.

Next, as shown in FIG. 3E, a sidewall 113 and a sidewall 123 are formed, and impurities are self-aligned by using the gate electrode 112 and the sidewall 113, and the gate electrode 122 and the sidewall 123 as a mask. By injecting
High impurity concentration regions 115 and 125 are formed. Here, the side walls 113 and 123 are
2 and the insulating film 203 can be formed by performing anisotropic etching to such an extent that the surface of the semiconductor substrate is exposed over the entire surface. At this time, by forming the insulating films 202 and 203 around the gate electrode 112,
The width L1 of the side wall 113 is the side wall 123
Is larger than the width L2 by 0.03 μm or more (see FIG. 1). Note that the width L1 of the sidewall 113 and the width L2 of the sidewall 123 can be changed depending on the thicknesses of the insulating films 202 and 203 and etching conditions.

At the time of the above-mentioned etching, a part of the gate insulating film 201 is also etched so that the gate insulating film 11 is removed.
1 is formed. Thus, a semiconductor device including the high breakdown voltage MOS transistor and the low voltage driving MOS transistor is formed.

As described above, according to the manufacturing method of the second embodiment, the side wall 113 having a larger width than the side wall 123 can be formed. Then, by implanting impurities using the thick sidewall 113 as a mask, an LDD having an offset length (substantially equal to the width L1) sufficient to secure the breakdown voltage of the high breakdown voltage MOS transistor is obtained.
Region 114 can be formed. Further, as is apparent from the manufacturing process, since the sidewalls 113 are always formed almost symmetrically in the left and right directions, one of the sidewalls 113 does not become extremely thin due to the conventional mask shift of the resist.

In the manufacturing method of the second embodiment, it is not necessary to take a margin for the length (offset length) of the LDD region 114 in consideration of the mask misalignment, so that the high breakdown voltage MOS transistor can be formed small. Therefore, according to the manufacturing method of the second embodiment, a small and highly reliable semiconductor device can be easily manufactured.

When a transistor having three or more types of sidewall widths is formed in a semiconductor device, FIG.
By repeating the steps (c) and (d) and finally forming a sidewall of the insulating film by anisotropic etching, a transistor having an optimum LDD length (offset length) required in terms of withstand voltage can be formed on the same chip. It can be easily formed on top.

Embodiment 3 In Embodiment 3, another example of the method for manufacturing a semiconductor device of the present invention will be described.
According to the manufacturing method of the third embodiment, the semiconductor device 100a described in the first embodiment can be easily manufactured. The same parts as those in the above embodiment will not be described repeatedly.

FIG. 4 schematically shows a process chart of the manufacturing method according to the third embodiment. In FIG. 4, the illustration of the semiconductor substrate other than the well 101 is omitted.

In the manufacturing method of the third embodiment, first, FIG.
As shown in (a), a LOCOS film 130, gate electrodes 112 and 122, an LDD region 114b, an insulating film 301, and a gate insulating film 302 are formed. LOC
The OS film 130, the gate electrodes 112 and 122, and the gate insulating film 302 can be formed in the same manner as in the second embodiment. The gate electrodes 112 and 122 are
No. 02 according to a conventional method. LDD region 114b
Can be formed by forming a photoresist or the like in a portion where a low-voltage drive MOS transistor is to be formed, and then performing LDD implantation (impurity implantation) into the self-alignment using the photoresist and the gate electrode 112 as a mask. The insulating film 301 serves as a side wall. After the LDD region 114b is formed, the entire surface of the substrate is covered with C to cover the gate electrodes 112 and 122 and the like.
It is formed using a VD method or the like. The thickness of the insulating film 301 is
It is preferably at least 0.01 μm, for example,
It is 0.01 μm or more and 2 μm or less.

Next, as shown in FIG. 4B, after forming the side wall 113b and the side wall 303, the portion where the high breakdown voltage MOS transistor is to be formed is covered with the photoresist 304. The sidewalls 113b and 303 can be formed by anisotropically etching the insulating film 301.

Next, as shown in FIG. 4C, the side wall 303 and a part of the gate insulating film 302 are removed to remove the gate electrode 122 and the gate insulating film 1.
21 are formed, and an LDD region 114c and an LDD region 124 are further formed. Part of the sidewall 303 and the gate insulating film 302 can be removed by isotropic selective etching using the gate electrode 122 and the photoresist 304 as a mask. As in the case of the manufacturing method of the second embodiment, it may take a relatively long time to remove the gate insulating film 302 of the low-voltage drive MOS transistor portion by isotropic selective etching.
It is necessary to improve the etching selectivity so that the LOCOS film 130 is not etched too much. for that reason,
It is preferable to use a silicon nitride film or a silicon oxynitride film for the gate insulating film 302. LDD region 11
4c and 124 are formed by removing the photoresist 304 and then removing the gate electrode 112 and the side wall 11
3b and the gate electrode 122 as a mask to form a self-aligned impurity.
At this time, the LDD region 114c is
Since impurities are further implanted in addition to the impurities at the time of forming b, the impurity concentration of LDD region 114c is
It is higher than the impurity concentration of the region 114b. After removing the side wall 303, the photoresist 3
By implanting impurities while leaving LD 04, LD
Only the D region 124 can be formed.

Next, as shown in FIG. 4D, an insulating film 305 is formed so as to cover the entire surface of the semiconductor substrate on which the LDD region 114c and the like are formed. The insulating film 305 is to be a part of the sidewall, and is formed by, for example, CVD.
It is formed of a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like formed by a method or the like. Insulating film 3
The film thickness of 05 is preferably 0.03 μm or more, for example, 0.03 μm or more and 1 μm or less.

Next, as shown in FIG. 4E, the side walls 113a and 123 and the high impurity concentration region 11 are formed.
5 and 125 are formed. Side wall 113a
And 123 can be formed by anisotropically etching the insulating film 305. At this time, the gate electrode 11
2 is formed on the side surface of the insulating film 305 which remains without being etched.
Are formed, and the side wall 113b formed in the step of FIG. 4B is formed, and these become the side wall 113a. In this way, the width L1 of the sidewall 113a is formed to be larger than the width L2 of the sidewall 123 by 0.03 μm or more (see FIG. 2). High impurity concentration region 11
5 and 125 can be formed by implanting impurities into the self-alignment using gate electrode 112 and sidewall 113a and gate electrode 122 and sidewall 123 as a mask. In this way,
A semiconductor device including a high breakdown voltage MOS transistor and a low voltage driving MOS transistor can be manufactured.

In the above manufacturing method, since the two side walls 113b and 113c are formed on the side wall of the gate electrode 112 of the high breakdown voltage MOS transistor, the width L1 of the side wall 113a can be increased. Further, by forming the high impurity concentration region 115 using the side wall 113a as a mask, the LDD length (offset length) can be increased, and a high withstand voltage MOS with high withstand voltage can be obtained.
Type transistor can be obtained. Furthermore, since the photoresist 113 does not need to be mask-aligned when the sidewalls 113a are formed, an LDD region having a stable LDD length can always be formed. A high semiconductor device can be easily manufactured. .

Further, according to the manufacturing method of the third embodiment, the impurity concentration profile of the LDD region below the sidewall 113a of the high breakdown voltage MOS transistor is adjusted in the horizontal direction (the direction substantially parallel to the direction in which carriers move in the channel).
Since the impurity concentration profile is relatively steep, a semiconductor device including a high-breakdown-voltage MOS transistor having particularly high withstand voltage can be formed as compared with the manufacturing method of the second embodiment.

Although the embodiments of the present invention have been described with reference to the examples, the present invention is not limited to the above embodiments, but can be applied to other embodiments based on the technical idea of the present invention.

[0056]

As described above, in the semiconductor device according to the present invention, the width of the sidewall of the high breakdown voltage MOS transistor is larger than the width of the sidewall of the low voltage driving MOS transistor by 0.03 μm or more. Withstand voltage MOS
Region is formed by implanting impurities using the gate electrode as a mask, and a high breakdown voltage M
High impurity concentration source / drain regions of the OS type transistor are formed by implanting impurities using the gate electrode and the sidewalls as a mask. Therefore, according to the semiconductor device of the present invention, a small and highly reliable semiconductor device including the high breakdown voltage MOS transistor and the low voltage driving MOS transistor can be obtained. Further, in the semiconductor device of the present invention, since the respective LDD regions or the high impurity concentration source / drain regions of the high breakdown voltage MOS transistor and the low voltage driving MOS transistor can be simultaneously formed by one-time impurity implantation, Particularly easy to manufacture.

In the method of manufacturing a semiconductor device according to the present invention, the width of the sidewall of the high breakdown voltage MOS transistor is set to be at least 0.03 μm larger than the width of the sidewall of the low voltage driving MOS transistor. Then, impurities are implanted using the sidewalls as a mask to form source / drain regions having a high impurity concentration. Therefore, according to the method for manufacturing a semiconductor device of the present invention, a small and highly reliable semiconductor device can be manufactured. Further, in the method of manufacturing a semiconductor device according to the present invention, the LDD regions or the high impurity concentration source / drain regions of the high breakdown voltage MOS transistor and the low voltage driving MOS transistor are simultaneously formed by one-time impurity implantation. Can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing one example of a semiconductor device of the present invention.

FIG. 2 is a partial cross-sectional view showing another example of the semiconductor device of the present invention.

FIG. 3 is a process chart showing an example of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a process chart showing another example of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating an example of a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 semiconductor device 101 well 102 semiconductor substrate 110, 110a high withstand voltage MOS transistor 111, 121, 201, 302 gate insulating film 112, 122 gate electrode 113, 113a, 113b, 113c, 123, 30
3 Side wall 114, 114a, 114b, 114c, 124 LD
D region 115, 125 High impurity concentration source / drain region 120 Low voltage drive MOS transistor 130 LOCOS film 202, 203, 301, 305 Insulating film 304 Photoresist

Claims (6)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; a high-voltage MOS transistor and a low-voltage driving MOS transistor formed on a part of the semiconductor substrate; A gate electrode, a first sidewall formed on a side surface of the first gate electrode, and an LDD formed in the semiconductor substrate.
And a source / drain region having an impurity concentration higher than that of the LDD region. The low-voltage-drive MOS transistor includes a second gate electrode and a second gate electrode formed on a side surface of the second gate electrode.
The width of the first sidewall is larger than the width of the second sidewall by 0.03 μm or more, and the LDD region is doped with impurities using the first gate electrode as a mask. Wherein the source / drain regions are formed by implanting impurities using the first gate electrode and the first sidewall as a mask. 2. The semiconductor device according to claim 1, further comprising a second LDD region having an impurity concentration higher than that of said LDD region outside said LDD region. 3. The method according to claim 1, wherein the width of the first side wall is 0.
The semiconductor device according to claim 1, wherein the thickness is not less than 04 μm and not more than 2 μm. 4. A method of manufacturing a semiconductor device, comprising: a semiconductor substrate; a high-voltage MOS transistor and a low-voltage driving MOS transistor formed on a part of the semiconductor substrate, wherein a gate insulating film is formed on the semiconductor substrate. Forming a first gate electrode of the high breakdown voltage MOS transistor and a second gate electrode of the low voltage drive MOS transistor on the gate insulating film; A second step of forming an LDD region by injecting impurities using the first and second gate electrodes as a mask; a first sidewall disposed on a side surface of the first gate electrode; A second sidewall disposed on a side surface of the gate electrode, the width of the first sidewall being 0.03 μm larger than the width of the second sidewall.
a third step of forming the first and second gate electrodes and the first and second gate electrodes and the first and second sidewalls as a mask, thereby forming an impurity concentration higher than that of the LDD region. Forming a source / drain region having a high density. 5. The method according to claim 5, wherein the third step is a step of forming a first insulating film so as to cover the first gate electrode, and a step of covering the second gate electrode and the first insulating film. The method of manufacturing a semiconductor device according to claim 4, further comprising: forming a second insulating film; and anisotropically etching the first and second insulating films. 6. After the second step and before the third step, a sidewall is formed on a side surface of the first gate electrode, and impurities are formed using the first gate electrode and the sidewall as a mask. Forming a second LDD region having an impurity concentration higher than that of the LDD region by implanting the first sidewall. In the third step, the first sidewall is further insulated on a side surface of the sidewall. The method according to claim 4, wherein the semiconductor device is formed by forming a film.