JP3391176B2 - Method for manufacturing thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art In an active matrix substrate of a liquid crystal display device, a large off-leakage current of a pixel switching TFT causes a display defect such as a reduction in contrast. Therefore, as a pixel switching TFT, use of a TFT having an offset structure in which the ends of the source / drain regions are displaced from the ends of the gate electrode in the channel length direction has been studied.

TFTs having such an offset structure have hitherto been used for the purpose of improving withstand voltage rather than reduction of off-leakage current in the field of ICs, LSIs, etc. in which the semiconductor is a single crystal. The TFT used in this field was manufactured by the following method.

First, as shown in FIG.
After forming the semiconductor film 11C on C, the semiconductor film 11C
The gate insulating film 12C is formed on the surface of the gate insulating film 12C, and then the gate electrode 13C is formed on the surface of the gate insulating film 12C.

Next, as shown in FIG. 7B, a silicon oxide film 21C is formed on the surface side of the gate electrode 13C (silicon oxide film forming step).

Next, as shown in FIG. 7C, the silicon oxide film 21C is anisotropically etched until the surface of the gate electrode 13C is exposed. As a result, the silicon oxide film 21C is uniformly etched, so that the silicon oxide film 21C is thicker on the side surface of the gate electrode 13C by the thickness of the silicon oxide film 21C.
It remains as C. Here, since the angle of the outer slope of the sidewall 15C is approximately 45 °, the sidewall 1
The length dimension of 5C in the channel length direction substantially matches the thickness of the gate electrode 13C.

Next, as shown in FIG. 7D, high-concentration impurities are introduced into the semiconductor film 11C by using the sidewalls 15C and the gate electrode 13C as masks to form high-concentration source / drain regions 161C and 162C. To do. Here, the portion where the impurities are not introduced is the channel region 17
It becomes C.

As a result, as shown in FIG. 7E, the ends of the source / drain regions 161C and 162C are displaced from the ends of the gate electrode 13C in the channel length direction, and the TFT having the offset gate structure is formed. It can be manufactured.

The sidewall 15C is not removed thereafter, and is integrated with an interlayer insulating film to be formed later.

On the other hand, after the gate electrode 13C is formed and before the silicon oxide film 21C is formed, the gate electrode 13C is formed.
If a low-concentration impurity is introduced using the mask as a mask, a low-concentration source / drain region can be formed in a portion facing the end of the gate electrode 13C through the gate insulating film 12C. It can be manufactured.

[0011]

Among the TFTs having the offset gate structure or the LDD structure manufactured as described above, the TFTs used in the fields of IC, LSI and the like are as follows.
The objective of improving the withstand voltage can be achieved only by setting the offset length and the LDD length (low-concentration source / drain region length) to relatively short dimensions of 0.2 μm to 0.3 μm.

However, unlike the fields of IC and LSI,
In a TFT using polysilicon as a semiconductor such as in the field of liquid crystal display devices, when an offset gate structure or an LDD structure is adopted for the purpose of reducing the off-leakage current, the offset length or the LDD length is It is necessary to set a relatively long dimension such as 0.5 μm or more. Therefore, the conventional manufacturing method has the following problems.

TF having an offset gate structure or an LDD structure
In the manufacturing method of T, it is apparent that the offset length Loff and the LDD length are defined by the length of the sidewall 15C, but in the conventional manufacturing method, the length of the sidewall 15C is the same as that of the gate electrode 13C. Since the thickness is almost the same as the thickness, in order to extend the offset length Loff and the LDD length for the purpose of reducing the off-leakage current of the TFT,
The gate electrode 13C also needs to be thicker accordingly.
However, if the gate electrode 13C is thickened, the scanning line formed at the same time as the gate electrode 13C is also thickened, so that the step formed on the front surface side of the scanning line becomes large and a disconnection occurs at the intersection of the scanning line and the data line. There is a problem that it is easy to get up. Conversely, the conventional offset gate structure and L
In a method of manufacturing a TFT having a DD structure, a gate electrode 1 is provided for the purpose of preventing disconnection at a step portion of a scanning line surface.
When 3C is thinned, the offset length Loff and the LDD length are shortened, which causes a problem that the off-leak current of the TFT is increased.

That is, in the conventional manufacturing method, as long as the side wall is used, making the gate electrode 13C thin and making the offset length Loff and LDD length long are in a trade-off relationship.

As a manufacturing method which does not use sidewalls, a region for forming the offset region and the low concentration source / drain regions is covered with a resist mask, and in this state, the high concentration source / drain regions are formed. There is also a method of introducing impurities. However, in such a method, the number of photo processes is increased and the productivity is reduced. In addition, the offset length and the low-concentration source / drain region length (the length in the channel length direction of the low-concentration source / drain region) vary depending on the accuracy of the photo process. If the length of the concentration source / drain region is too short, the effect is small and the off-leakage current is large. Further, if the offset length and the low-concentration source / drain region length fluctuate and become too long, there arises a disadvantage that the on-current becomes small.

In view of the above problems, the object of the present invention is to:
In a method of manufacturing a TFT using a sidewall,
It is an object of the present invention to provide a method for manufacturing a TFT which can extend the offset length and the low-concentration source / drain region length even if the gate electrode is thinned so that the surface step difference between the gate electrode and the scanning line does not become large.

[0017]

A method of manufacturing a thin film transistor according to the present invention comprises a step of forming a semiconductor film on a substrate,
Forming a gate insulating film on the semiconductor film, forming a gate electrode on the gate insulating film, forming a resist layer so as to cover the gate electrode, and etching the resist layer. A step of forming sidewalls on both sides of the gate electrode, a step of forming a source / drain region by implanting an impurity into the semiconductor film using the gate electrode and the sidewall as a mask, and a step of forming the source / drain region. After the step of forming, the step of etching the gate electrode to adjust the thickness to a predetermined thickness and the step of removing the sidewall after the step of adjusting the gate electrode are provided. .

Further, in the method of manufacturing a thin film transistor of the present invention, a low concentration impurity is added to the semiconductor film by using the gate electrode as a mask between the step of forming the gate electrode and the step of forming the resist layer. It is characterized by injecting.

Further, etching is performed so that the gate insulating film located on the surface of the source / drain regions is also removed simultaneously with the step of adjusting the thickness of the gate electrode.

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. Although the present invention can be applied to an active matrix substrate using a coplanar type TFT, the embodiments described below are all examples of manufacturing a TFT on a drive circuit built-in type active matrix substrate in a liquid crystal display device. To explain. Therefore, before describing each embodiment, the configuration of the active matrix substrate will be described with reference to FIG.

In FIG. 1A, the liquid crystal display device has a pixel region defined by data lines 90 and scanning lines 91 on the active matrix substrate, and pixel regions are formed there through a pixel TFT 92. There is a liquid crystal capacitor 94 of a liquid crystal cell to which an image signal is input. Also, the data line 90
To the shift register 84, the level shifter 85,
A data driver unit 82 including a video line 87 and an analog switch 86 is formed on the active matrix substrate. For the scanning line 91, the shift register 8
8 and a level shifter 89
Are formed on the active matrix substrate. In addition, in the pixel region, a storage capacitor 93 is provided between the pixel line and the preceding scanning line.
Is also formed. Here, the TFT for the drive circuit is used in a shift register, a level shifter, an analog switch, and the like. For example, the shift register 8
In Nos. 4 and 88, as shown in the two-stage inverter in FIG. 1B, the first conductivity type TFTs n1 and n2 and the second conductivity type TFTs p1 and p2 form CMOS circuits.

Example 1 FIGS. 2 and 3 show Example 1
6A to 6C are process cross-sectional views showing the method of manufacturing the TFT according to the first embodiment. It should be noted that the manufacturing method of this example is performed by using either N-type or P-type TF.
Although it can be applied to T, the case of manufacturing an N-type TFT will be described as an example. This example and Examples 2 and 3 to be described later are examples of manufacturing a pixel switching TFT in a liquid crystal display device, and the drive circuit and the active matrix substrate are separately configured, not limited to the drive circuit built-in active matrix substrate. It is also applicable when it is.

First, in FIG. 2A, an amorphous silicon thin film is formed on the surface side of a glass substrate 10 (insulating substrate) which is a base of an active matrix substrate by using an LPCVD method or a plasma CVD method, and then,
Crystal grains are grown by a laser annealing method or a solid phase growth method to form an intrinsic semiconductor film (polysilicon thin film). Next, the semiconductor film is patterned by the photolithography method to form the island-shaped semiconductor film 11 (semiconductor film forming step). In addition, on the surface of the substrate 10,
It is common to form an underlayer protective film, but in this example, the underlayer protective film is not shown.

Next, with respect to the island-shaped semiconductor film 11, TE
OS-CVD method, LPCVD method, plasma CVD method, H
The gate insulating film 12 made of a silicon oxide film having a thickness of about 0.02 μm to about 0.15 μm is formed by the TO method or the like (gate insulating film forming step).

Next, in order to form a gate electrode on the surface side of the gate insulating film 12, a conductor film made of a metal thin film such as a tantalum film is formed, and then this conductor film is patterned by a photolithography technique. A gate electrode 13 having a thickness of 0.5 μm or more, for example, 0.8 μm is formed on the gate insulating film 12 (gate electrode forming step). The gate electrode 13 is formed at the same time as the scanning line of the active matrix substrate.

Next, as shown in FIG. 2B, a resist layer 14 is formed on the surface side of the gate electrode 13 (resist layer forming step).

Next, as shown in FIG. 2C, the resist layer 14 is anisotropically etched until the surface of the gate electrode 13 is exposed. For example, an etching method (RIE) using O ₂ gas or the like is used. Here, the resist layer 1
Since No. 4 is uniformly etched, the resist layer 14 remains on the side surface of the gate electrode 13 by the amount of the thick resist layer 14. As a result, on the side surface of the gate electrode 13,
Sidewalls 15 as the rest of the resist layer 14
Are formed (sidewall forming step). Here, since the angle of the outer slope of the sidewall 15 is approximately 45 °, the length dimension of the sidewall 15 is approximately 0.8 μm, which is approximately the same as the thickness of the gate electrode 13.

Next, as shown in FIG. 2D, high-concentration N-type impurities such as phosphorus ions are introduced into the semiconductor film 11 using the sidewalls 15 and the gate electrodes 13 as masks (high-concentration impurities). Introduction process). As a result, the high-concentration source / drain regions 161 and 162 are formed, and the portion where impurities are not introduced is the channel region 1.
It becomes 7.

In this impurity introducing step, a method of implanting all ions generated from the dopant gas without mass separation, that is, a so-called ion shower doping method is used. For example, the PH ₃ comprises from about 1% to about 20%, using a mixed gas and the balance being a hydrogen gas, helium gas, implanting all ions generated from the mixed gas without mass separation. Note that as a method for introducing impurities, an ion implantation method, a plasma doping method, a laser doping method, or the like may be used instead of the ion shower doping method.

Next, as shown in FIG. 3A, the gate electrode 13 is selectively etched to reduce the thickness of the gate electrode 13 to 0.4 μm or less (gate electrode thickness adjusting step). In such etching, for example, an etching method (CDE) using a CF ₄ + O ₂ mixed gas is used as a dry etching method capable of selectively etching tantalum.

Thereafter, as shown in FIG. 3B, the side wall 15 is removed.

Thereafter, as shown in FIG. 3C, an interlayer insulating film 18 and contact holes 181, 182 are formed on the surface side of the gate electrode 13, and the contact hole 18 is formed.
A source electrode 191 (a data line in the active matrix substrate) and a drain electrode 192 (a pixel electrode in the active matrix substrate) made of an ITO film are formed through the electrodes 1 and 182.

In the TFT thus formed, the end portion of the gate electrode 13 and the high concentration source / drain regions 161, 1 are formed.
It has an offset structure in which the end portion with 62 is displaced in the channel length direction. Moreover, the offset length Loff is 0.5 μ.
m or more, for example, 0.8 μm, which is long. Therefore, the TFT
Although the TFT is formed by a low temperature process, the off-leakage current is small. Therefore, when such a TFT is used for pixel switching, display quality is improved. Further, since the withstand voltage between the source and drain of the TFT is high, the channel length can be shortened. Also, from the viewpoint of small parasitic capacitance, when such a TFT is used for a drive circuit, the operating speed of the drive circuit can be increased. Moreover, even though the offset length Loff is set to 0.5 μm or more, since the thickness of the gate electrode 13 is 0.4 μm or less, the step formed on the surface side of the gate electrode 13 (scanning line) Is small. Therefore, even at the intersection of the gate electrode 13 (scanning line) and the source electrode 191 (data line), disconnection or the like does not occur.

Further, when manufacturing such a TFT,
When the ion shower doping method is used in the step of introducing impurities into the source / drain regions, the channel region 17
It is necessary to prevent impurities and hydrogen from entering into. Therefore, in this example, as shown in FIG. 2D, in the high-concentration impurity introduction step, the gate electrode 13 is still performed in a thick state such as 0.8 μm. Therefore, even if the implantation energy for introducing the impurities is increased, the impurities do not reach the channel region 17, so that it is possible to achieve both the improvement in productivity and the securing of the electrical characteristics of the TFT.

Moreover, since the sidewall 15 is made of a resist, it can be easily peeled and removed.

[Embodiment 2] FIG. 4 is a process sectional view showing only characteristic steps in the method of manufacturing a TFT of this embodiment. The manufacturing method of the TFT according to the first embodiment described above is
In contrast to the method of manufacturing a TFT having an offset gate structure, the method of manufacturing a TFT of this example is a method of manufacturing a TFT having an LDD structure. However, in the method of manufacturing the TFT of this example, the basic steps are the same as those of the first embodiment, and therefore, corresponding parts will be denoted by the same reference numerals and description thereof will be omitted.

In this example, in order to manufacture a TFT having an LDD structure, after performing the gate electrode forming step described in Example 1 with reference to FIG. 2A, referring to FIG. Before performing the described resist layer forming step, FIG.
As shown in, a low concentration N-type impurity is introduced into the semiconductor film 11 using the gate electrode 13 as a mask. as a result,
Low-concentration source / drain regions 163 and 164 are formed in the semiconductor film 11 in self-alignment with the gate electrode 13 (low-concentration impurity introduction step).

After that, as in the first embodiment, as shown in FIG.
-Each step described with reference to FIG. As a result, as shown in FIG. 4B, when the high-concentration source / drain regions 161 and 162 are formed in the source / drain regions, the end portions of the gate electrode 13 are opposed to each other via the gate insulating film 12. Is a low concentration source / drain region 16
3,164 remain.

In the thus-formed TFT, LDs are low-concentration source / drain regions 163 and 164 where the end portions of the gate electrode 13 which face each other with the gate insulating film 12 interposed therebetween are low concentration source / drain regions 163 and 164.
It has a D structure. Moreover, the low concentration source / drain region length Lldd (low concentration source / drain regions 163, 1
The dimension of 64 in the channel length direction) is 0.5 μm or more, for example 0.8 μm, which is long. For this reason, the TFT has a small off-leakage current even though it is formed by a low-temperature process. Therefore, when such a TFT is used for pixel switching, display quality is improved. In addition, low concentration sauce
Even though the drain region length Lldd is set to 0.5 μm or more, since the thickness of the gate electrode 13 is 0.4 μm or less, the step formed on the surface side of the gate electrode 13 (scan line) is small. Therefore, even at the intersection of the gate electrode 13 (scanning line) and the source electrode 191 (data line), the same effect as that of the first embodiment is obtained, such as no breakage.

[Embodiment 3] FIG. 5 is a process sectional view showing only characteristic steps in the method for manufacturing a TFT of this embodiment. The method of manufacturing the TFT of this example is characterized in that the source electrode and the drain electrode are directly connected to the high-concentration source / drain regions, and the other configurations are the same as in the first embodiment. Therefore, corresponding parts are denoted by the same reference numerals and the description thereof will be omitted. First,
Also in the manufacturing method of the TFT of this example, FIG. 2 (A) to FIG. 2 (C)
As described above, the resist layer 14 formed on the surface side of the gate electrode 13 is anisotropically etched until the surface of the gate electrode 13 is exposed, and the resist left on the side surface of the gate electrode 13 is exposed. The side wall 15 is formed by the layer 13. Further, as shown in FIG. 2D, a high-concentration source / drain is introduced into the semiconductor film 11 by introducing a high-concentration N-type impurity into the semiconductor film 11 using the sidewall 15 and the gate electrode 13 as a mask. Regions 161 and 162 are formed. The steps up to this point are the same as in Example 1.

Next, as shown in FIG. 5A, in the step of adjusting the gate electrode thickness, when the gate electrode 13 is etched to reduce the thickness of the gate electrode 13 to 0.4 μm or less, The gate insulating film 12 exposed from the electrodes 13 and the sidewalls 15 is also etched to expose the high concentration source / drain regions 161 and 162. In this etching, as a dry etching method capable of etching both tantalum and the gate insulating film, for example, etching using CHF ₃ gas or the like (RIE) is used.

Next, as shown in FIG. 5B, the sidewall 15 is removed.

Thereafter, as shown in FIG. 5C, the source electrode 191 (data line in the active matrix substrate) is directly connected to the source region side of the high-concentration source / drain regions 161, 162, and the drain is formed. The drain electrode 192 (pixel electrode on the active matrix substrate) is directly connected to the region side. Such a connection structure is
For example, after a metal layer for forming the source electrode 191 is formed on the entire surface, patterning is performed by a photolithography technique, and similarly, an ITO layer for forming the drain electrode 192 is formed on the entire surface, and then a photolithography technique is used. It is performed by patterning. Finally, or before forming the source electrode 191 and the drain electrode 192, a protective film or the like is formed on the surface side of the gate electrode 13, but the illustration thereof is omitted.

Also in the TFT thus formed, the end portion of the gate electrode 13, the high concentration source / drain region 161,
It has an offset structure in which the end portion with 162 is displaced in the channel length direction. Moreover, the offset length Loff is 0.5
The length is longer than μm, for example, 0.8 μm. Therefore, TF
Since the off leak current of T is small, the use of this TFT for pixel switching improves the display quality. In addition, even though the offset length Loff is set to 0.5 μm or more, the thickness of the gate electrode 13 is 0.4 μm.
Because of the following, the step formed on the surface side of the gate electrode 13 (scanning line) is small. Therefore, on the active matrix substrate, the same effect as that of the first embodiment can be obtained, such as disconnection does not occur even near the intersection of the gate electrode 13 (scanning line) and the source electrode 191 (data line).

Furthermore, in this example, when the gate electrode 13 is etched, the gate insulating film 12 is also etched to expose the high-concentration source / drain regions 161 and 162, so that the high-concentration source / drain regions 16 are exposed.
The source electrode 191 and the drain electrode 192 are directly connected to the Nos. 1 and 162, respectively. Therefore, unlike the case where the source electrode 191 and the drain electrode 192 are electrically connected to the high-concentration source / drain regions 161, 162 through the interlayer insulating film, it is necessary to newly form the contact hole in another step. The number of steps can be reduced as much as there is no.

Although this example is applied to the TFT having the offset gate structure, it can be applied to the TFT having the LDD structure as described in the second embodiment.

[Embodiment 4] Among the N-type TFTs and P-type TFTs forming the CMOS circuit of the drive circuit on the active matrix substrate of the liquid crystal display device,
For N-type TFT, TFT for pixel switching
It is manufactured in the same process as the above.
It is often manufactured by using a part of the manufacturing process of the mold TFT. Therefore, in this example, a method of manufacturing a P-type TFT while using the method of manufacturing an N-type TFT according to the first embodiment will be described.

6A to 6C are process sectional views showing a method of manufacturing the TFT of this embodiment. Of the two TFT formation regions shown in FIG. 6, the left side of the drawing is a P-type TFT (driving circuit TFT) formation region, and the right side of the drawing is an N-type TFT (pixel switching TFT). / TF for drive circuit
It is a formation region of T).

First, in FIG. 6A, an amorphous silicon thin film is formed on the surface side of a glass substrate 10 which is a base of an active matrix substrate by using the LPCVD method or the plasma CVD method, and then the laser annealing method or Crystal grains are grown by a solid phase growth method to form an intrinsic semiconductor film (polysilicon thin film). Next, the semiconductor film is patterned by photolithography to form a first semiconductor film 11N for manufacturing an N-type TFT and a second semiconductor film 11P for manufacturing a P-type TFT. (Semiconductor film forming step). The substrate 1
It is general to preliminarily form an underlayer protective film on the surface of 0, but in this example, the underlayer protective film is not shown.

Next, the first semiconductor film 11N and the second semiconductor film 11N
TEOS-CVD method, LP
The first gate insulating film 12N and the second gate insulating film 12 are formed by the CVD method, the plasma CVD method, the HTO method, or the like.
P is formed (gate insulating film forming step).

Next, in order to form a gate electrode, a conductor film made of a metal thin film such as a tantalum film is formed, and then this conductor film is patterned by a photolithography technique to form a first gate insulating film 12N. A first layer having a thickness of 0.5 μm or more, for example 0.8 μm.
The gate electrode 13N is formed (first gate electrode forming step). The gate electrode 13N is formed at the same time as the scanning line of the active matrix substrate.

At this time, in the formation region of the P-type TFT,
The conductor film 130P is left on the second gate insulating film 12P so as to cover the entire formation region of the second semiconductor film 11P. The thickness of the conductor film 130P is equal to that of the first gate insulating film 12
Is equal to the thickness of N and has a thickness of 0.5 μm or more, for example,
The thickness is 0.8 μm.

Next, as shown in FIG. 6B, a resist layer 14 is formed on the surface side of the first gate electrode 13N and the conductor film 130P (resist layer forming step).

Next, as shown in FIG. 6C, the resist layer 14 is anisotropically etched until the surface of the first gate electrode 13N is exposed. Here, the resist layer 14 is
Since it is uniformly etched, the first gate electrode 13N
On the side surface of, the resist layer 14 remains as much as the resist layer 14 was thick. As a result, the sidewall 15N formed of the remaining portion of the resist layer 14 is formed on the side surface of the first gate electrode 13N (sidewall forming step). Here, since the angle of the outer slope of the sidewall 15N is approximately 45 °, the length dimension of the sidewall 15N is approximately 0.8 μm, which is approximately the same as the thickness of the first gate electrode 13N.

Next, as shown in FIG. 6D, a high-concentration N-type impurity such as phosphorus ions is introduced into the semiconductor film 11N using the sidewall 15N and the first gate electrode 13N as a mask (high-concentration first). 1 conductivity type impurity introduction step). As a result, a high concentration source /
The drain regions 161N and 162N are formed, and the portion into which the impurities are not introduced becomes the channel region 17N. However, since the second semiconductor film 11P is covered with the thick conductor film 130P, N-type impurities are not introduced.

Next, as shown in FIG. 6E, the tantalum film forming the first gate electrode 13N is selectively etched to reduce the thickness of the gate electrode 13N to 0.4 μm or less. Thin (gate electrode thickness adjustment step). At this time, the conductor film 130P is also selectively etched,
The thickness is reduced to 0.4 μm or less.

Next, as shown in FIG. 6F, the sidewall 15 is removed.

Next, as shown in FIG. 6G, the gate electrode formation planned region of the conductor film 130P and the N-type TF are formed.
The surface of the T formation region is covered with the resist mask 20, the conductor film 130P is patterned, and the second gate electrode 13 is formed.
Form P.

Next, as shown in FIG. 6H, P-type impurities are introduced with the surface of the second gate electrode 13P and the N-type TFT formation region covered with the resist mask 20. , High-concentration source / drain regions 161P and 162P are formed in the second semiconductor film 11P (second conductivity type impurity introducing step). Incidentally, of the second semiconductor film 11P,
The region into which the impurities are not introduced becomes the channel region 17P.

In this impurity introducing step, a method of implanting all ions generated from the dopant gas without mass separation, that is, a so-called ion shower doping method is used. For example, a mixed gas containing B ₂ H _{6 in an amount} of about 1% to about 20% and the balance of hydrogen gas or helium gas is used, and all ions generated from this mixed gas are implanted without mass separation. Note that as a method for introducing impurities, an ion implantation method, a plasma doping method, a laser doping method, or the like may be used instead of the ion shower doping method.

As a result, as shown in FIG. 6 (I), the second
Of the semiconductor film 11P of the high-concentration source / drain region 16 in self-alignment with the second gate electrode 13P.
1P and 162P are formed, and a P-type TFT having a self-aligned structure and an N-type TFT having an offset gate structure are formed. Of these TFTs, the N-type TFT is
It is used as a pixel switching TFT and a drive circuit TFT, and a P-type TFT is used as a drive circuit TFT.

Therefore, according to the method of manufacturing the TFT of this example, as shown in FIG. 6D, when the N-type impurity is introduced, the second conductive film 11P is formed by using the thick conductive film 130P.
As shown in FIG. 6H, the first semiconductor film 11N is covered with the resist mask 20 when covering P and introducing the P-type impurity, so that the impurity can be introduced only into a predetermined region. Moreover, even with a P-type TFT, the second gate electrode 13P
Since the thickness is thin, the step on the surface can be made small, and even in this case,
As shown in FIG. 6H, even if impurities are introduced with a large implantation energy, since the second semiconductor film 11P is covered with the second gate electrode 13P and the resist mask 20, the channel region is formed. It is possible to prevent impurities from entering 17P.

Therefore, an N-type TFT having an offset gate structure having a long offset length Loff of 0.5 μm or more, for example 0.8 μm, can be constructed as a pixel switching TFT which is required to have a small off-leakage current. The display quality is improved. In addition, N-type TFT
The offset length Loff of the first gate electrode 13N and the second gate electrode 13N is set to 0.5 μm or more.
Since the thickness of the gate electrode 13P is 0.4 μm or less, the step formed on the surface side of the first gate electrode 13N (scan line) and the second gate electrode 13P is small.
Therefore, on the active matrix substrate, disconnection or the like does not occur even at the intersection of the gate electrode 13 (scanning line) and the source electrode 191 (data line).

When the ion shower doping method is used in the step of introducing impurities into the source / drain regions when manufacturing this TFT, the channel regions 17N, 1
It is necessary to prevent impurities and hydrogen from entering 7P. Therefore, in the high-concentration first conductivity type impurity introduction step shown in FIG. 6D, the gate electrode 13 has a thickness of 0.8 μm.
As shown in Fig. 6, impurities are introduced in a thick state such as
In the second conductivity type impurity introducing step shown in (H), the second gate electrode 13P and the resist mask 20 after being thinned
Impurities are introduced in a state where and are stacked. Therefore, even if the implantation energy for introducing the impurities is increased, the impurities and hydrogen do not reach the channel regions 17N and 17P, so that it is possible to achieve both the improvement in productivity and the securing of the electrical characteristics of the TFT.

[Modification of Fourth Embodiment] In the fourth embodiment as well, description will be given with reference to FIG. 6B after the first gate electrode forming step described with reference to FIG. Before performing the above-described resist layer forming step, a low concentration N-type impurity may be introduced into the semiconductor film 11N using the first gate electrode 13N as a mask. By doing this, as in the second embodiment, the low concentration source / drain regions can be formed in the semiconductor film 11N in a self-aligned manner with respect to the first gate electrode 13N, so that an N-type TFT having an LDD structure is manufactured. it can.

[Other Embodiments] In any of the embodiments,
Although the method of manufacturing the TFT in which the channel region is composed of an intrinsic silicon film (semiconductor film) has been described as an example, for example, a method in which a channel doping step is added, or a semiconductor film containing an extremely low concentration of impurities is used as a substrate. Formed on the
It may then be applied to the method of manufacturing the TFT.

Further, N is used as a pixel switching TFT.
Although an example of using a P-type TFT has been described, a P-type TFT may be used as a pixel switching TFT.

[0076]

As described above, the TF according to the present invention
The manufacturing method of T is characterized in that the impurity is introduced by using the side wall made of the resist layer and the gate electrode which is still thick as a mask, and after the introduction of the impurity is completed, the gate electrode is thinned. Therefore, according to the present invention, in order to extend the offset length of the TFT and the low-concentration source / drain length in the LDD structure to reduce the off-leakage current of the TFT, the gate electrode is formed thick and the side long in the channel direction is formed. Even if the wall is formed, since the gate electrode is thinned after the introduction of the impurities, the step formed on the surface side of the gate electrode (scanning line) is small. Therefore, even at the intersection of the gate electrode (scanning line) and the source electrode (data line), disconnection or the like does not occur. Also, when introducing impurities, it is necessary to prevent impurities from reaching the channel region.
In the present invention, impurities are introduced when the gate electrode is still thick. Therefore, in the ion implantation technology (ion shower doping technology) that does not perform mass separation,
Even when the implantation energy for introducing impurities is increased when using an impurity gas diluted with hydrogen, unnecessary impurities and hydrogen do not reach the channel region. Therefore, it is possible to achieve both the improvement in productivity and the securing of the electrical characteristics of the TFT. Moreover, the resist layer used as a mask at the time of introducing impurities is a material that is usually used as a mask for ion implantation, even though it needs to be removed later,
It is easy to peel and remove.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing an active matrix substrate of a liquid crystal display device according to each embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing the method of manufacturing a TFT according to the first embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing each process performed subsequent to the process shown in FIG. 2 in the method of manufacturing a TFT according to the first embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing a characteristic process in the method for manufacturing a TFT according to the second embodiment of the present invention.

FIG. 5 is a process cross-sectional view showing a characteristic process in a method of manufacturing a TFT according to a third embodiment of the present invention.

FIG. 6 is a process sectional view showing a method of manufacturing a complementary TFT according to a fourth embodiment of the present invention.

7A to 7C are process cross-sectional views showing a conventional TFT manufacturing method.

[Explanation of symbols]

10 ... Substrate 11 ... Semiconductor film 12 ... Gate insulating film 13 ... Gate electrode 14 ... Resist layer 15 ... Sidewalls 161, 162 ... High concentration source / drain regions 17 ... ..Channel regions 18 ... Interlayer insulating films 181, 182 ... Contact holes 191 ... Source electrodes (data lines in active matrix substrate) 192 ... Drain electrodes (pixel electrodes in active matrix substrate)

Claims (3)

(57) [Claims] 1. A step of forming a semiconductor film on a substrate, a step of forming a gate insulating film on the semiconductor film, a step of forming a gate electrode on the gate insulating film, and a step of covering the gate electrode. A step of forming a resist layer on the substrate, a step of etching the resist layer to form sidewalls on both sides of the gate electrode, and implanting an impurity into the semiconductor film using the gate electrode and the sidewall as a mask. A step of forming a source / drain region, a step of forming the source / drain region, a step of adjusting the gate electrode thickness by etching the gate electrode to a predetermined thickness, and a step of adjusting the gate electrode, And a step of removing the sidewalls. 2. A low-concentration impurity is implanted into the semiconductor film using the gate electrode as a mask between the step of forming the gate electrode and the step of forming the resist layer. 1. The method for manufacturing a thin film transistor according to 1. 3. The manufacturing of a thin film transistor according to claim 1, wherein etching is performed so as to also remove the gate insulating film located on the surface of the source / drain regions at the same time as the gate electrode thickness adjusting step. Method.